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[/] [a-z80/] [trunk/] [cpu/] [control/] [memory_ifc.v] - Blame information for rev 4

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1 3 gdevic 
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors.  Please refer to the
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// applicable agreement for further details.
14 
 
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// PROGRAM              "Quartus II 64-Bit"
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// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED              "Sun Nov 16 21:11:14 2014"
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19 
module memory_ifc(
20 
        clk,
21 
        nM1_int,
22 
        ctl_mRead,
23 
        ctl_mWrite,
24 
        in_intr,
25 
        nreset,
26 
        fIORead,
27 
        fIOWrite,
28 
        setM1,
29 
        ctl_iorw,
30 
        timings_en,
31 
        iorq_Tw,
32 
        hold_clk_wait,
33 
        nM1_out,
34 
        nRFSH_out,
35 
        nMREQ_out,
36 
        nRD_out,
37 
        nWR_out,
38 
        nIORQ_out,
39 
        latch_wait
40 
);
41 
 
42 
 
43 
input wire      clk;
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input wire      nM1_int;
45 
input wire      ctl_mRead;
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input wire      ctl_mWrite;
47 
input wire      in_intr;
48 
input wire      nreset;
49 
input wire      fIORead;
50 
input wire      fIOWrite;
51 
input wire      setM1;
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input wire      ctl_iorw;
53 
input wire      timings_en;
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input wire      iorq_Tw;
55 
input wire      hold_clk_wait;
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output wire     nM1_out;
57 
output wire     nRFSH_out;
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output wire     nMREQ_out;
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output wire     nRD_out;
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output wire     nWR_out;
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output wire     nIORQ_out;
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output wire     latch_wait;
63 
 
64 
wire    intr_iorq;
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wire    ioRead;
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wire    iorq;
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wire    ioWrite;
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wire    m1_mreq;
69 
wire    mrd_mreq;
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wire    mwr_mreq;
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reg     mwr_wr;
72 
wire    nMEMRQ_int;
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wire    nq2;
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reg     q1;
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reg     q2;
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reg     wait_iorq;
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reg     wait_m1;
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reg     wait_mrd;
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reg     wait_mwr;
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wire    SYNTHESIZED_WIRE_0;
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reg     DFFE_m1_ff3;
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wire    SYNTHESIZED_WIRE_1;
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reg     SYNTHESIZED_WIRE_15;
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reg     DFFE_iorq_ff4;
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reg     SYNTHESIZED_WIRE_16;
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reg     DFFE_mrd_ff3;
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reg     DFFE_intr_ff3;
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wire    SYNTHESIZED_WIRE_2;
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reg     SYNTHESIZED_WIRE_17;
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reg     SYNTHESIZED_WIRE_18;
91 
wire    SYNTHESIZED_WIRE_19;
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wire    SYNTHESIZED_WIRE_4;
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reg     DFFE_iorq_ff1;
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reg     DFFE_m1_ff1;
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reg     DFFE_mrd_ff1;
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reg     DFFE_mwr_ff1;
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reg     DFFE_mreq_ff2;
98 
 
99 
assign  nM1_out = SYNTHESIZED_WIRE_18;
100 
 
101 
 
102 
 
103 
assign  nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
104 
 
105 
assign  ioRead = iorq & fIORead;
106 
 
107 
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m1);
108 
 
109 
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
110 
 
111 
assign  iorq = SYNTHESIZED_WIRE_15 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_16;
112 
 
113 
assign  ioWrite = iorq & fIOWrite;
114 
 
115 
assign  latch_wait = wait_mrd | wait_iorq | wait_m1 | wait_mwr;
116 
 
117 
assign  nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
118 
 
119 
assign  nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
120 
 
121 
assign  mrd_mreq = DFFE_mrd_ff3 | wait_mrd;
122 
 
123 
assign  nWR_out = ~(ioWrite | mwr_wr);
124 
 
125 
assign  mwr_mreq = mwr_wr | wait_mwr;
126 
 
127 
assign  nIORQ_out = ~(intr_iorq | iorq);
128 
 
129 
assign  SYNTHESIZED_WIRE_4 =  ~hold_clk_wait;
130 
 
131 
assign  intr_iorq = DFFE_intr_ff3 | wait_iorq;
132 
 
133 
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_17);
134 
 
135 
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_18);
136 
 
137 
 
138 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
139 
begin
140 
if (!nreset)
141 
        begin
142 
        wait_iorq <= 0;
143 
        end
144 
else
145 
        begin
146 
        wait_iorq <= iorq_Tw;
147 
        end
148 
end
149 
 
150 
 
151 
always@(posedge clk or negedge nreset)
152 
begin
153 
if (!nreset)
154 
        begin
155 
        DFFE_intr_ff3 <= 0;
156 
        end
157 
else
158 
if (SYNTHESIZED_WIRE_4)
159 
        begin
160 
        DFFE_intr_ff3 <= wait_iorq;
161 
        end
162 
end
163 
 
164 
 
165 
always@(posedge clk or negedge nreset)
166 
begin
167 
if (!nreset)
168 
        begin
169 
        DFFE_iorq_ff1 <= 0;
170 
        end
171 
else
172 
if (timings_en)
173 
        begin
174 
        DFFE_iorq_ff1 <= ctl_iorw;
175 
        end
176 
end
177 
 
178 
 
179 
always@(posedge clk or negedge nreset)
180 
begin
181 
if (!nreset)
182 
        begin
183 
        SYNTHESIZED_WIRE_16 <= 0;
184 
        end
185 
else
186 
if (timings_en)
187 
        begin
188 
        SYNTHESIZED_WIRE_16 <= DFFE_iorq_ff1;
189 
        end
190 
end
191 
 
192 
 
193 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
194 
begin
195 
if (!nreset)
196 
        begin
197 
        SYNTHESIZED_WIRE_15 <= 0;
198 
        end
199 
else
200 
if (timings_en)
201 
        begin
202 
        SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_16;
203 
        end
204 
end
205 
 
206 
 
207 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
208 
begin
209 
if (!nreset)
210 
        begin
211 
        DFFE_iorq_ff4 <= 0;
212 
        end
213 
else
214 
if (timings_en)
215 
        begin
216 
        DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_15;
217 
        end
218 
end
219 
 
220 
 
221 
always@(posedge clk or negedge nreset)
222 
begin
223 
if (!nreset)
224 
        begin
225 
        SYNTHESIZED_WIRE_18 <= 0;
226 
        end
227 
else
228 
if (timings_en)
229 
        begin
230 
        SYNTHESIZED_WIRE_18 <= nM1_int;
231 
        end
232 
end
233 
 
234 
 
235 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
236 
begin
237 
if (!nreset)
238 
        begin
239 
        DFFE_m1_ff1 <= 1;
240 
        end
241 
else
242 
if (timings_en)
243 
        begin
244 
        DFFE_m1_ff1 <= setM1;
245 
        end
246 
end
247 
 
248 
 
249 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
250 
begin
251 
if (!nreset)
252 
        begin
253 
        wait_m1 <= 0;
254 
        end
255 
else
256 
if (timings_en)
257 
        begin
258 
        wait_m1 <= DFFE_m1_ff1;
259 
        end
260 
end
261 
 
262 
 
263 
always@(posedge clk or negedge nreset)
264 
begin
265 
if (!nreset)
266 
        begin
267 
        DFFE_m1_ff3 <= 0;
268 
        end
269 
else
270 
if (timings_en)
271 
        begin
272 
        DFFE_m1_ff3 <= wait_m1;
273 
        end
274 
end
275 
 
276 
 
277 
always@(posedge clk or negedge nreset)
278 
begin
279 
if (!nreset)
280 
        begin
281 
        DFFE_mrd_ff1 <= 0;
282 
        end
283 
else
284 
if (timings_en)
285 
        begin
286 
        DFFE_mrd_ff1 <= ctl_mRead;
287 
        end
288 
end
289 
 
290 
 
291 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
292 
begin
293 
if (!nreset)
294 
        begin
295 
        wait_mrd <= 0;
296 
        end
297 
else
298 
if (timings_en)
299 
        begin
300 
        wait_mrd <= DFFE_mrd_ff1;
301 
        end
302 
end
303 
 
304 
 
305 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
306 
begin
307 
if (!nreset)
308 
        begin
309 
        DFFE_mrd_ff3 <= 0;
310 
        end
311 
else
312 
if (timings_en)
313 
        begin
314 
        DFFE_mrd_ff3 <= wait_mrd;
315 
        end
316 
end
317 
 
318 
 
319 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
320 
begin
321 
if (!nreset)
322 
        begin
323 
        SYNTHESIZED_WIRE_17 <= 0;
324 
        end
325 
else
326 
if (timings_en)
327 
        begin
328 
        SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_18;
329 
        end
330 
end
331 
 
332 
 
333 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
334 
begin
335 
if (!nreset)
336 
        begin
337 
        DFFE_mreq_ff2 <= 0;
338 
        end
339 
else
340 
if (timings_en)
341 
        begin
342 
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
343 
        end
344 
end
345 
 
346 
 
347 
always@(posedge clk or negedge nreset)
348 
begin
349 
if (!nreset)
350 
        begin
351 
        DFFE_mwr_ff1 <= 0;
352 
        end
353 
else
354 
if (timings_en)
355 
        begin
356 
        DFFE_mwr_ff1 <= ctl_mWrite;
357 
        end
358 
end
359 
 
360 
 
361 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
362 
begin
363 
if (!nreset)
364 
        begin
365 
        wait_mwr <= 0;
366 
        end
367 
else
368 
if (timings_en)
369 
        begin
370 
        wait_mwr <= DFFE_mwr_ff1;
371 
        end
372 
end
373 
 
374 
 
375 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
376 
begin
377 
if (!nreset)
378 
        begin
379 
        mwr_wr <= 0;
380 
        end
381 
else
382 
if (timings_en)
383 
        begin
384 
        mwr_wr <= wait_mwr;
385 
        end
386 
end
387 
 
388 
assign  SYNTHESIZED_WIRE_19 =  ~clk;
389 
 
390 
assign  nq2 =  ~q2;
391 
 
392 
assign  SYNTHESIZED_WIRE_2 =  ~DFFE_mreq_ff2;
393 
 
394 
 
395 
always@(posedge clk or negedge nreset)
396 
begin
397 
if (!nreset)
398 
        begin
399 
        q1 <= 0;
400 
        end
401 
else
402 
if (timings_en)
403 
        begin
404 
        q1 <= SYNTHESIZED_WIRE_18;
405 
        end
406 
end
407 
 
408 
 
409 
always@(posedge clk or negedge nreset)
410 
begin
411 
if (!nreset)
412 
        begin
413 
        q2 <= 0;
414 
        end
415 
else
416 
if (timings_en)
417 
        begin
418 
        q2 <= q1;
419 
        end
420 
end
421 
 
422 
 
423 
endmodule

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