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[/] [a-z80/] [trunk/] [cpu/] [control/] [sequencer.v] - Blame information for rev 14

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1 3 gdevic 
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors.  Please refer to the
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// applicable agreement for further details.
14 
 
15 
// PROGRAM              "Quartus II 64-Bit"
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// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
17 8 gdevic 
// CREATED              "Sat Feb 13 17:56:57 2016"
18 3 gdevic 
 
19 
module sequencer(
20 
        clk,
21 
        nextM,
22 
        setM1,
23 
        nreset,
24 
        hold_clk_iorq,
25 
        hold_clk_wait,
26 
        hold_clk_busrq,
27 
        M1,
28 
        M2,
29 
        M3,
30 
        M4,
31 
        M5,
32 
        T1,
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        T2,
34 
        T3,
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        T4,
36 
        T5,
37 
        T6,
38 
        timings_en
39 
);
40 
 
41 
 
42 
input wire      clk;
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input wire      nextM;
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input wire      setM1;
45 
input wire      nreset;
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input wire      hold_clk_iorq;
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input wire      hold_clk_wait;
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input wire      hold_clk_busrq;
49 
output wire     M1;
50 
output wire     M2;
51 
output wire     M3;
52 
output wire     M4;
53 8 gdevic 
output reg      M5;
54 3 gdevic 
output wire     T1;
55 
output wire     T2;
56 
output wire     T3;
57 
output wire     T4;
58 
output wire     T5;
59 
output reg      T6;
60 
output wire     timings_en;
61 
 
62 
wire    ena_M;
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wire    ena_T;
64 
reg     DFFE_M4_ff;
65 8 gdevic 
wire    SYNTHESIZED_WIRE_18;
66 3 gdevic 
reg     DFFE_T1_ff;
67 8 gdevic 
wire    SYNTHESIZED_WIRE_19;
68 3 gdevic 
reg     DFFE_T2_ff;
69 
reg     DFFE_T3_ff;
70 
reg     DFFE_T4_ff;
71 
reg     DFFE_T5_ff;
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reg     DFFE_M1_ff;
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reg     DFFE_M2_ff;
74 
reg     DFFE_M3_ff;
75 8 gdevic 
wire    SYNTHESIZED_WIRE_9;
76 3 gdevic 
wire    SYNTHESIZED_WIRE_10;
77 
wire    SYNTHESIZED_WIRE_11;
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wire    SYNTHESIZED_WIRE_12;
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wire    SYNTHESIZED_WIRE_13;
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wire    SYNTHESIZED_WIRE_14;
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wire    SYNTHESIZED_WIRE_15;
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wire    SYNTHESIZED_WIRE_16;
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wire    SYNTHESIZED_WIRE_17;
84 
 
85 
assign  M1 = DFFE_M1_ff;
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assign  M2 = DFFE_M2_ff;
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assign  M3 = DFFE_M3_ff;
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assign  M4 = DFFE_M4_ff;
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assign  T1 = DFFE_T1_ff;
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assign  T2 = DFFE_T2_ff;
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assign  T3 = DFFE_T3_ff;
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assign  T4 = DFFE_T4_ff;
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assign  T5 = DFFE_T5_ff;
94 
 
95 
 
96 
 
97 8 gdevic 
assign  ena_M = nextM | setM1;
98 3 gdevic 
 
99 8 gdevic 
assign  SYNTHESIZED_WIRE_12 = DFFE_M4_ff & SYNTHESIZED_WIRE_18;
100 3 gdevic 
 
101 8 gdevic 
assign  SYNTHESIZED_WIRE_13 = DFFE_T1_ff & SYNTHESIZED_WIRE_19;
102 3 gdevic 
 
103 8 gdevic 
assign  SYNTHESIZED_WIRE_14 = DFFE_T2_ff & SYNTHESIZED_WIRE_19;
104 3 gdevic 
 
105 8 gdevic 
assign  SYNTHESIZED_WIRE_15 = DFFE_T3_ff & SYNTHESIZED_WIRE_19;
106 3 gdevic 
 
107 8 gdevic 
assign  SYNTHESIZED_WIRE_16 = DFFE_T4_ff & SYNTHESIZED_WIRE_19;
108 3 gdevic 
 
109 8 gdevic 
assign  SYNTHESIZED_WIRE_17 = DFFE_T5_ff & SYNTHESIZED_WIRE_19;
110 3 gdevic 
 
111 8 gdevic 
assign  SYNTHESIZED_WIRE_9 = DFFE_M1_ff & SYNTHESIZED_WIRE_18;
112 3 gdevic 
 
113 8 gdevic 
assign  SYNTHESIZED_WIRE_10 = DFFE_M2_ff & SYNTHESIZED_WIRE_18;
114 3 gdevic 
 
115 8 gdevic 
assign  SYNTHESIZED_WIRE_11 = DFFE_M3_ff & SYNTHESIZED_WIRE_18;
116 3 gdevic 
 
117 
assign  ena_T = ~(hold_clk_iorq | hold_clk_wait | hold_clk_busrq);
118 
 
119 
 
120 
always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_M1_ff <= 1;
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        end
126 
else
127 
if (ena_M)
128 
        begin
129 
        DFFE_M1_ff <= setM1;
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        end
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end
132 
 
133 
 
134 
always@(posedge clk or negedge nreset)
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begin
136 
if (!nreset)
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        begin
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        DFFE_M2_ff <= 0;
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        end
140 
else
141 
if (ena_M)
142 
        begin
143 8 gdevic 
        DFFE_M2_ff <= SYNTHESIZED_WIRE_9;
144 3 gdevic 
        end
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end
146 
 
147 
 
148 
always@(posedge clk or negedge nreset)
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begin
150 
if (!nreset)
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        begin
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        DFFE_M3_ff <= 0;
153 
        end
154 
else
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if (ena_M)
156 
        begin
157 8 gdevic 
        DFFE_M3_ff <= SYNTHESIZED_WIRE_10;
158 3 gdevic 
        end
159 
end
160 
 
161 
 
162 
always@(posedge clk or negedge nreset)
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begin
164 
if (!nreset)
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        begin
166 
        DFFE_M4_ff <= 0;
167 
        end
168 
else
169 
if (ena_M)
170 
        begin
171 8 gdevic 
        DFFE_M4_ff <= SYNTHESIZED_WIRE_11;
172 3 gdevic 
        end
173 
end
174 
 
175 
 
176 
always@(posedge clk or negedge nreset)
177 
begin
178 
if (!nreset)
179 
        begin
180 8 gdevic 
        M5 <= 0;
181 3 gdevic 
        end
182 
else
183 
if (ena_M)
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        begin
185 8 gdevic 
        M5 <= SYNTHESIZED_WIRE_12;
186 3 gdevic 
        end
187 
end
188 
 
189 8 gdevic 
assign  SYNTHESIZED_WIRE_19 =  ~ena_M;
190 3 gdevic 
 
191 8 gdevic 
assign  SYNTHESIZED_WIRE_18 =  ~setM1;
192 3 gdevic 
 
193 
 
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always@(posedge clk or negedge nreset)
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begin
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if (!nreset)
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        begin
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        DFFE_T1_ff <= 1;
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        end
200 
else
201 
if (ena_T)
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        begin
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        DFFE_T1_ff <= ena_M;
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        end
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end
206 
 
207 
 
208 
always@(posedge clk or negedge nreset)
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begin
210 
if (!nreset)
211 
        begin
212 
        DFFE_T2_ff <= 0;
213 
        end
214 
else
215 
if (ena_T)
216 
        begin
217 8 gdevic 
        DFFE_T2_ff <= SYNTHESIZED_WIRE_13;
218 3 gdevic 
        end
219 
end
220 
 
221 
 
222 
always@(posedge clk or negedge nreset)
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begin
224 
if (!nreset)
225 
        begin
226 
        DFFE_T3_ff <= 0;
227 
        end
228 
else
229 
if (ena_T)
230 
        begin
231 8 gdevic 
        DFFE_T3_ff <= SYNTHESIZED_WIRE_14;
232 3 gdevic 
        end
233 
end
234 
 
235 
 
236 
always@(posedge clk or negedge nreset)
237 
begin
238 
if (!nreset)
239 
        begin
240 
        DFFE_T4_ff <= 0;
241 
        end
242 
else
243 
if (ena_T)
244 
        begin
245 8 gdevic 
        DFFE_T4_ff <= SYNTHESIZED_WIRE_15;
246 3 gdevic 
        end
247 
end
248 
 
249 
 
250 
always@(posedge clk or negedge nreset)
251 
begin
252 
if (!nreset)
253 
        begin
254 
        DFFE_T5_ff <= 0;
255 
        end
256 
else
257 
if (ena_T)
258 
        begin
259 8 gdevic 
        DFFE_T5_ff <= SYNTHESIZED_WIRE_16;
260 3 gdevic 
        end
261 
end
262 
 
263 
 
264 
always@(posedge clk or negedge nreset)
265 
begin
266 
if (!nreset)
267 
        begin
268 
        T6 <= 0;
269 
        end
270 
else
271 
if (ena_T)
272 
        begin
273 8 gdevic 
        T6 <= SYNTHESIZED_WIRE_17;
274 3 gdevic 
        end
275 
end
276 
 
277 
assign  timings_en = ena_T;
278 
 
279 
endmodule

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