Subversion Repositories a-z80

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2013 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II 64-Bit

# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition

# Date created = 09:22:29  October 13, 2014

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               test_control_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone II"

set_global_assignment -name DEVICE EP2C20F484C7

set_global_assignment -name TOP_LEVEL_ENTITY execute

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:22:29  OCTOBER 13, 2014"

set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name USE_CONFIGURATION_DEVICE ON

set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"

set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON

set_global_assignment -name SMART_RECOMPILE ON

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON

set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF

set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005

set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF

set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON

set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON

set_global_assignment -name VERILOG_FILE pla_decode.v

set_global_assignment -name VERILOG_FILE execute.v

set_global_assignment -name BDF_FILE sequencer.bdf

set_global_assignment -name BDF_FILE resets.bdf

set_global_assignment -name BDF_FILE memory_ifc.bdf

set_global_assignment -name BDF_FILE ir.bdf

set_global_assignment -name BDF_FILE interrupts.bdf

set_global_assignment -name BDF_FILE decode_state.bdf

set_global_assignment -name BDF_FILE clk_delay.bdf

set_global_assignment -name BDF_FILE pin_control.bdf

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top