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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// PROGRAM              "Quartus II 64-Bit"
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED              "Sat Dec 10 09:05:10 2016"
 
module reg_control(
        ctl_reg_exx,
        ctl_reg_ex_af,
        ctl_reg_ex_de_hl,
        ctl_reg_use_sp,
        nreset,
        ctl_reg_sel_pc,
        ctl_reg_sel_ir,
        ctl_reg_sel_wz,
        ctl_reg_gp_we,
        ctl_reg_not_pc,
        use_ixiy,
        use_ix,
        ctl_reg_sys_we_lo,
        ctl_reg_sys_we_hi,
        ctl_reg_sys_we,
        clk,
        ctl_sw_4d,
        nhold_clk_wait,
        ctl_reg_gp_hilo,
        ctl_reg_gp_sel,
        ctl_reg_sys_hilo,
        reg_sel_bc,
        reg_sel_bc2,
        reg_sel_ix,
        reg_sel_iy,
        reg_sel_de,
        reg_sel_hl,
        reg_sel_de2,
        reg_sel_hl2,
        reg_sel_af,
        reg_sel_af2,
        reg_sel_wz,
        reg_sel_pc,
        reg_sel_ir,
        reg_sel_sp,
        reg_sel_gp_hi,
        reg_sel_gp_lo,
        reg_sel_sys_lo,
        reg_sel_sys_hi,
        reg_gp_we,
        reg_sys_we_lo,
        reg_sys_we_hi,
        reg_sw_4d_lo,
        reg_sw_4d_hi
);
 
 
input wire      ctl_reg_exx;
input wire      ctl_reg_ex_af;
input wire      ctl_reg_ex_de_hl;
input wire      ctl_reg_use_sp;
input wire      nreset;
input wire      ctl_reg_sel_pc;
input wire      ctl_reg_sel_ir;
input wire      ctl_reg_sel_wz;
input wire      ctl_reg_gp_we;
input wire      ctl_reg_not_pc;
input wire      use_ixiy;
input wire      use_ix;
input wire      ctl_reg_sys_we_lo;
input wire      ctl_reg_sys_we_hi;
input wire      ctl_reg_sys_we;
input wire      clk;
input wire      ctl_sw_4d;
input wire      nhold_clk_wait;
input wire      [1:0] ctl_reg_gp_hilo;
input wire      [1:0] ctl_reg_gp_sel;
input wire      [1:0] ctl_reg_sys_hilo;
output wire     reg_sel_bc;
output wire     reg_sel_bc2;
output wire     reg_sel_ix;
output wire     reg_sel_iy;
output wire     reg_sel_de;
output wire     reg_sel_hl;
output wire     reg_sel_de2;
output wire     reg_sel_hl2;
output wire     reg_sel_af;
output wire     reg_sel_af2;
output wire     reg_sel_wz;
output wire     reg_sel_pc;
output wire     reg_sel_ir;
output wire     reg_sel_sp;
output wire     reg_sel_gp_hi;
output wire     reg_sel_gp_lo;
output wire     reg_sel_sys_lo;
output wire     reg_sel_sys_hi;
output wire     reg_gp_we;
output wire     reg_sys_we_lo;
output wire     reg_sys_we_hi;
output wire     reg_sw_4d_lo;
output wire     reg_sw_4d_hi;
 
reg     bank_af;
reg     bank_exx;
reg     bank_hl_de1;
reg     bank_hl_de2;
wire    reg_sys_we_lo_ALTERA_SYNTHESIZED;
wire    SYNTHESIZED_WIRE_52;
wire    SYNTHESIZED_WIRE_53;
wire    SYNTHESIZED_WIRE_2;
wire    SYNTHESIZED_WIRE_54;
wire    SYNTHESIZED_WIRE_55;
wire    SYNTHESIZED_WIRE_5;
wire    SYNTHESIZED_WIRE_56;
wire    SYNTHESIZED_WIRE_10;
wire    SYNTHESIZED_WIRE_57;
wire    SYNTHESIZED_WIRE_58;
wire    SYNTHESIZED_WIRE_59;
wire    SYNTHESIZED_WIRE_60;
wire    SYNTHESIZED_WIRE_21;
wire    SYNTHESIZED_WIRE_23;
wire    SYNTHESIZED_WIRE_24;
wire    SYNTHESIZED_WIRE_25;
wire    SYNTHESIZED_WIRE_30;
wire    SYNTHESIZED_WIRE_31;
wire    SYNTHESIZED_WIRE_32;
wire    SYNTHESIZED_WIRE_61;
wire    SYNTHESIZED_WIRE_34;
wire    SYNTHESIZED_WIRE_36;
wire    SYNTHESIZED_WIRE_37;
wire    SYNTHESIZED_WIRE_38;
wire    SYNTHESIZED_WIRE_39;
wire    SYNTHESIZED_WIRE_40;
wire    SYNTHESIZED_WIRE_41;
wire    SYNTHESIZED_WIRE_42;
wire    SYNTHESIZED_WIRE_43;
wire    SYNTHESIZED_WIRE_44;
wire    SYNTHESIZED_WIRE_45;
wire    SYNTHESIZED_WIRE_46;
wire    SYNTHESIZED_WIRE_47;
wire    SYNTHESIZED_WIRE_48;
wire    SYNTHESIZED_WIRE_49;
wire    SYNTHESIZED_WIRE_50;
 
assign  reg_sel_wz = ctl_reg_sel_wz;
assign  reg_sel_ir = ctl_reg_sel_ir;
assign  reg_sel_gp_hi = ctl_reg_gp_hilo[1];
assign  reg_sel_gp_lo = ctl_reg_gp_hilo[0];
assign  reg_sel_sys_lo = ctl_reg_sys_hilo[0];
assign  reg_sel_sys_hi = ctl_reg_sys_hilo[1];
assign  reg_gp_we = ctl_reg_gp_we;
assign  reg_sw_4d_lo = ctl_sw_4d;
 
 
 
assign  reg_sel_bc = SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53;
 
assign  reg_sel_af = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_54;
 
assign  SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_55 & SYNTHESIZED_WIRE_5;
 
assign  reg_sel_sp = SYNTHESIZED_WIRE_55 & ctl_reg_use_sp;
 
assign  SYNTHESIZED_WIRE_5 =  ~ctl_reg_use_sp;
 
assign  reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;
 
assign  SYNTHESIZED_WIRE_50 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
 
assign  reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;
 
assign  reg_sel_af2 = bank_af & SYNTHESIZED_WIRE_54;
 
assign  SYNTHESIZED_WIRE_2 =  ~bank_af;
 
assign  SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
 
assign  SYNTHESIZED_WIRE_46 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
 
assign  SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
 
assign  SYNTHESIZED_WIRE_49 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
 
assign  SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
 
assign  reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;
 
assign  reg_sel_hl = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_23;
 
assign  reg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24;
 
assign  reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;
 
assign  SYNTHESIZED_WIRE_38 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
 
assign  SYNTHESIZED_WIRE_53 =  ~bank_exx;
 
assign  SYNTHESIZED_WIRE_45 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
 
assign  SYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
 
assign  SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;
 
assign  SYNTHESIZED_WIRE_60 =  ~bank_hl_de1;
 
assign  reg_sys_we_hi = ctl_reg_sys_we | ctl_reg_sys_we_hi;
 
assign  reg_sel_pc = ctl_reg_sel_pc & SYNTHESIZED_WIRE_32;
 
assign  SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_61 & SYNTHESIZED_WIRE_34;
 
assign  SYNTHESIZED_WIRE_32 =  ~ctl_reg_not_pc;
 
assign  SYNTHESIZED_WIRE_36 =  ~ctl_reg_gp_sel[1];
 
assign  reg_sys_we_lo_ALTERA_SYNTHESIZED = ctl_reg_sys_we_lo | ctl_reg_sys_we;
 
assign  SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;
 
assign  SYNTHESIZED_WIRE_42 =  ~ctl_reg_gp_sel[0];
 
assign  SYNTHESIZED_WIRE_43 = ctl_reg_ex_de_hl & bank_exx;
 
assign  SYNTHESIZED_WIRE_34 =  ~use_ixiy;
 
assign  SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        bank_af <= 0;
        end
else
if (nhold_clk_wait)
        begin
        bank_af <= bank_af ^ ctl_reg_ex_af;
        end
end
 
assign  SYNTHESIZED_WIRE_10 =  ~use_ix;
 
assign  SYNTHESIZED_WIRE_57 =  ~bank_hl_de2;
 
assign  SYNTHESIZED_WIRE_41 =  ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
assign  SYNTHESIZED_WIRE_40 =  ~SYNTHESIZED_WIRE_37;
 
assign  SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_38 | SYNTHESIZED_WIRE_39;
 
assign  reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_40;
 
assign  SYNTHESIZED_WIRE_37 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_41 & ctl_reg_sel_ir;
 
assign  SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_42 & ctl_reg_gp_sel[1];
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        bank_hl_de2 <= 0;
        end
else
if (nhold_clk_wait)
        begin
        bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;
        end
end
 
assign  SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_44 | SYNTHESIZED_WIRE_45;
 
assign  SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_46 | SYNTHESIZED_WIRE_47;
 
assign  SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_48 | SYNTHESIZED_WIRE_49;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        bank_hl_de1 <= 0;
        end
else
if (nhold_clk_wait)
        begin
        bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;
        end
end
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
        begin
        bank_exx <= 0;
        end
else
if (nhold_clk_wait)
        begin
        bank_exx <= bank_exx ^ ctl_reg_exx;
        end
end
 
assign  SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
 
assign  SYNTHESIZED_WIRE_30 =  ~ctl_reg_gp_sel[0];
 
assign  SYNTHESIZED_WIRE_31 =  ~ctl_reg_gp_sel[1];
 
assign  reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
 
assign  reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
endmodule

Line No.	Rev	Author	Line
1	3	gdevic	`// Copyright (C) 1991-2013 Altera Corporation`
2			`// Your use of Altera Corporation's design tools, logic functions`
3			`// and other software and tools, and its AMPP partner logic`
4			`// functions, and any output files from any of the foregoing`
5			`// (including device programming or simulation files), and any`
6			`// associated documentation or information are expressly subject`
7			`// to the terms and conditions of the Altera Program License`
8			`// Subscription Agreement, Altera MegaCore Function License`
9			`// Agreement, or other applicable license agreement, including,`
10			`// without limitation, that your use is for the sole purpose of`
11			`// programming logic devices manufactured by Altera and sold by`
12			`// Altera or its authorized distributors. Please refer to the`
13			`// applicable agreement for further details.`
14
15			`// PROGRAM "Quartus II 64-Bit"`
16			`// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"`
17	16	gdevic	`// CREATED "Sat Dec 10 09:05:10 2016"`
18	3	gdevic
19			`module reg_control(`
20			`ctl_reg_exx,`
21			`ctl_reg_ex_af,`
22			`ctl_reg_ex_de_hl,`
23			`ctl_reg_use_sp,`
24			`nreset,`
25			`ctl_reg_sel_pc,`
26			`ctl_reg_sel_ir,`
27			`ctl_reg_sel_wz,`
28			`ctl_reg_gp_we,`
29			`ctl_reg_not_pc,`
30			`use_ixiy,`
31			`use_ix,`
32			`ctl_reg_sys_we_lo,`
33			`ctl_reg_sys_we_hi,`
34			`ctl_reg_sys_we,`
35			`clk,`
36	8	gdevic	`ctl_sw_4d,`
37	16	gdevic	`nhold_clk_wait,`
38	3	gdevic	`ctl_reg_gp_hilo,`
39			`ctl_reg_gp_sel,`
40			`ctl_reg_sys_hilo,`
41			`reg_sel_bc,`
42			`reg_sel_bc2,`
43			`reg_sel_ix,`
44			`reg_sel_iy,`
45			`reg_sel_de,`
46			`reg_sel_hl,`
47			`reg_sel_de2,`
48			`reg_sel_hl2,`
49			`reg_sel_af,`
50			`reg_sel_af2,`
51			`reg_sel_wz,`
52			`reg_sel_pc,`
53			`reg_sel_ir,`
54			`reg_sel_sp,`
55			`reg_sel_gp_hi,`
56			`reg_sel_gp_lo,`
57			`reg_sel_sys_lo,`
58			`reg_sel_sys_hi,`
59			`reg_gp_we,`
60			`reg_sys_we_lo,`
61	8	gdevic	`reg_sys_we_hi,`
62			`reg_sw_4d_lo,`
63			`reg_sw_4d_hi`
64	3	gdevic	`);`
65
66
67			`input wire ctl_reg_exx;`
68			`input wire ctl_reg_ex_af;`
69			`input wire ctl_reg_ex_de_hl;`
70			`input wire ctl_reg_use_sp;`
71			`input wire nreset;`
72			`input wire ctl_reg_sel_pc;`
73			`input wire ctl_reg_sel_ir;`
74			`input wire ctl_reg_sel_wz;`
75			`input wire ctl_reg_gp_we;`
76			`input wire ctl_reg_not_pc;`
77			`input wire use_ixiy;`
78			`input wire use_ix;`
79			`input wire ctl_reg_sys_we_lo;`
80			`input wire ctl_reg_sys_we_hi;`
81			`input wire ctl_reg_sys_we;`
82			`input wire clk;`
83	8	gdevic	`input wire ctl_sw_4d;`
84	16	gdevic	`input wire nhold_clk_wait;`
85	3	gdevic	`input wire [1:0] ctl_reg_gp_hilo;`
86			`input wire [1:0] ctl_reg_gp_sel;`
87			`input wire [1:0] ctl_reg_sys_hilo;`
88			`output wire reg_sel_bc;`
89			`output wire reg_sel_bc2;`
90			`output wire reg_sel_ix;`
91			`output wire reg_sel_iy;`
92			`output wire reg_sel_de;`
93			`output wire reg_sel_hl;`
94			`output wire reg_sel_de2;`
95			`output wire reg_sel_hl2;`
96			`output wire reg_sel_af;`
97			`output wire reg_sel_af2;`
98			`output wire reg_sel_wz;`
99			`output wire reg_sel_pc;`
100			`output wire reg_sel_ir;`
101			`output wire reg_sel_sp;`
102			`output wire reg_sel_gp_hi;`
103			`output wire reg_sel_gp_lo;`
104			`output wire reg_sel_sys_lo;`
105			`output wire reg_sel_sys_hi;`
106			`output wire reg_gp_we;`
107			`output wire reg_sys_we_lo;`
108			`output wire reg_sys_we_hi;`
109	8	gdevic	`output wire reg_sw_4d_lo;`
110			`output wire reg_sw_4d_hi;`
111	3	gdevic
112			`reg bank_af;`
113			`reg bank_exx;`
114			`reg bank_hl_de1;`
115			`reg bank_hl_de2;`
116	8	gdevic	`wire reg_sys_we_lo_ALTERA_SYNTHESIZED;`
117	3	gdevic	`wire SYNTHESIZED_WIRE_52;`
118			`wire SYNTHESIZED_WIRE_53;`
119	8	gdevic	`wire SYNTHESIZED_WIRE_2;`
120	3	gdevic	`wire SYNTHESIZED_WIRE_54;`
121			`wire SYNTHESIZED_WIRE_55;`
122	8	gdevic	`wire SYNTHESIZED_WIRE_5;`
123	3	gdevic	`wire SYNTHESIZED_WIRE_56;`
124	8	gdevic	`wire SYNTHESIZED_WIRE_10;`
125	3	gdevic	`wire SYNTHESIZED_WIRE_57;`
126	8	gdevic	`wire SYNTHESIZED_WIRE_58;`
127			`wire SYNTHESIZED_WIRE_59;`
128			`wire SYNTHESIZED_WIRE_60;`
129	3	gdevic	`wire SYNTHESIZED_WIRE_21;`
130			`wire SYNTHESIZED_WIRE_23;`
131			`wire SYNTHESIZED_WIRE_24;`
132			`wire SYNTHESIZED_WIRE_25;`
133			`wire SYNTHESIZED_WIRE_30;`
134			`wire SYNTHESIZED_WIRE_31;`
135			`wire SYNTHESIZED_WIRE_32;`
136	8	gdevic	`wire SYNTHESIZED_WIRE_61;`
137	3	gdevic	`wire SYNTHESIZED_WIRE_34;`
138			`wire SYNTHESIZED_WIRE_36;`
139			`wire SYNTHESIZED_WIRE_37;`
140			`wire SYNTHESIZED_WIRE_38;`
141			`wire SYNTHESIZED_WIRE_39;`
142			`wire SYNTHESIZED_WIRE_40;`
143			`wire SYNTHESIZED_WIRE_41;`
144			`wire SYNTHESIZED_WIRE_42;`
145			`wire SYNTHESIZED_WIRE_43;`
146			`wire SYNTHESIZED_WIRE_44;`
147			`wire SYNTHESIZED_WIRE_45;`
148			`wire SYNTHESIZED_WIRE_46;`
149			`wire SYNTHESIZED_WIRE_47;`
150	8	gdevic	`wire SYNTHESIZED_WIRE_48;`
151			`wire SYNTHESIZED_WIRE_49;`
152			`wire SYNTHESIZED_WIRE_50;`
153	3	gdevic
154			`assign reg_sel_wz = ctl_reg_sel_wz;`
155			`assign reg_sel_ir = ctl_reg_sel_ir;`
156			`assign reg_sel_gp_hi = ctl_reg_gp_hilo[1];`
157			`assign reg_sel_gp_lo = ctl_reg_gp_hilo[0];`
158			`assign reg_sel_sys_lo = ctl_reg_sys_hilo[0];`
159			`assign reg_sel_sys_hi = ctl_reg_sys_hilo[1];`
160			`assign reg_gp_we = ctl_reg_gp_we;`
161	8	gdevic	`assign reg_sw_4d_lo = ctl_sw_4d;`
162	3	gdevic
163
164
165	8	gdevic	`assign reg_sel_bc = SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53;`
166	3	gdevic
167	8	gdevic	`assign reg_sel_af = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_54;`
168	3	gdevic
169	8	gdevic	`assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_55 & SYNTHESIZED_WIRE_5;`
170	3	gdevic
171	8	gdevic	`assign reg_sel_sp = SYNTHESIZED_WIRE_55 & ctl_reg_use_sp;`
172	3	gdevic
173			`assign SYNTHESIZED_WIRE_5 = ~ctl_reg_use_sp;`
174
175	8	gdevic	`assign reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;`
176	3	gdevic
177	13	gdevic	`assign SYNTHESIZED_WIRE_50 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;`
178	3	gdevic
179	8	gdevic	`assign reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;`
180	3	gdevic
181	8	gdevic	`assign reg_sel_af2 = bank_af & SYNTHESIZED_WIRE_54;`
182	3	gdevic
183			`assign SYNTHESIZED_WIRE_2 = ~bank_af;`
184
185	13	gdevic	`assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;`
186	3	gdevic
187	13	gdevic	`assign SYNTHESIZED_WIRE_46 = bank_hl_de2 & SYNTHESIZED_WIRE_59;`
188	3	gdevic
189	13	gdevic	`assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;`
190	3	gdevic
191	13	gdevic	`assign SYNTHESIZED_WIRE_49 = bank_hl_de2 & SYNTHESIZED_WIRE_58;`
192	3	gdevic
193	13	gdevic	`assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;`
194	3	gdevic
195	8	gdevic	`assign reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;`
196	3	gdevic
197	8	gdevic	`assign reg_sel_hl = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_23;`
198	3	gdevic
199			`assign reg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24;`
200
201			`assign reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;`
202
203	13	gdevic	`assign SYNTHESIZED_WIRE_38 = bank_hl_de1 & SYNTHESIZED_WIRE_59;`
204	3	gdevic
205	8	gdevic	`assign SYNTHESIZED_WIRE_53 = ~bank_exx;`
206	3	gdevic
207	13	gdevic	`assign SYNTHESIZED_WIRE_45 = bank_hl_de1 & SYNTHESIZED_WIRE_58;`
208	3	gdevic
209	13	gdevic	`assign SYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;`
210	3	gdevic
211	8	gdevic	`assign SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;`
212	3	gdevic
213	8	gdevic	`assign SYNTHESIZED_WIRE_60 = ~bank_hl_de1;`
214	3	gdevic
215			`assign reg_sys_we_hi = ctl_reg_sys_we \| ctl_reg_sys_we_hi;`
216
217			`assign reg_sel_pc = ctl_reg_sel_pc & SYNTHESIZED_WIRE_32;`
218
219	8	gdevic	`assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_61 & SYNTHESIZED_WIRE_34;`
220	3	gdevic
221			`assign SYNTHESIZED_WIRE_32 = ~ctl_reg_not_pc;`
222
223			`assign SYNTHESIZED_WIRE_36 = ~ctl_reg_gp_sel[1];`
224
225	8	gdevic	`assign reg_sys_we_lo_ALTERA_SYNTHESIZED = ctl_reg_sys_we_lo \| ctl_reg_sys_we;`
226	3	gdevic
227	8	gdevic	`assign SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;`
228	3	gdevic
229	13	gdevic	`assign SYNTHESIZED_WIRE_42 = ~ctl_reg_gp_sel[0];`
230	3	gdevic
231	13	gdevic	`assign SYNTHESIZED_WIRE_43 = ctl_reg_ex_de_hl & bank_exx;`
232	3	gdevic
233			`assign SYNTHESIZED_WIRE_34 = ~use_ixiy;`
234
235	8	gdevic	`assign SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;`
236	3	gdevic
237
238			`always@(posedge clk or negedge nreset)`
239			`begin`
240			`if (!nreset)`
241			`begin`
242	13	gdevic	`bank_af <= 0;`
243	3	gdevic	`end`
244			`else`
245	16	gdevic	`if (nhold_clk_wait)`
246	13	gdevic	`begin`
247			`bank_af <= bank_af ^ ctl_reg_ex_af;`
248			`end`
249	3	gdevic	`end`
250
251	13	gdevic	`assign SYNTHESIZED_WIRE_10 = ~use_ix;`
252	3	gdevic
253	13	gdevic	`assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2;`
254	8	gdevic
255	13	gdevic	`assign SYNTHESIZED_WIRE_41 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED;`
256
257			`assign SYNTHESIZED_WIRE_40 = ~SYNTHESIZED_WIRE_37;`
258
259			`assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_38 \| SYNTHESIZED_WIRE_39;`
260
261			`assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_40;`
262
263			`assign SYNTHESIZED_WIRE_37 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_41 & ctl_reg_sel_ir;`
264
265			`assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_42 & ctl_reg_gp_sel[1];`
266
267
268	3	gdevic	`always@(posedge clk or negedge nreset)`
269			`begin`
270			`if (!nreset)`
271			`begin`
272			`bank_hl_de2 <= 0;`
273			`end`
274			`else`
275	16	gdevic	`if (nhold_clk_wait)`
276	13	gdevic	`begin`
277			`bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;`
278			`end`
279	3	gdevic	`end`
280
281	13	gdevic	`assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_44 \| SYNTHESIZED_WIRE_45;`
282	3	gdevic
283	13	gdevic	`assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_46 \| SYNTHESIZED_WIRE_47;`
284	3	gdevic
285	13	gdevic	`assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_48 \| SYNTHESIZED_WIRE_49;`
286	3	gdevic
287
288			`always@(posedge clk or negedge nreset)`
289			`begin`
290			`if (!nreset)`
291			`begin`
292	13	gdevic	`bank_hl_de1 <= 0;`
293	3	gdevic	`end`
294			`else`
295	16	gdevic	`if (nhold_clk_wait)`
296	13	gdevic	`begin`
297			`bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;`
298			`end`
299	3	gdevic	`end`
300
301
302			`always@(posedge clk or negedge nreset)`
303			`begin`
304			`if (!nreset)`
305			`begin`
306	13	gdevic	`bank_exx <= 0;`
307	3	gdevic	`end`
308			`else`
309	16	gdevic	`if (nhold_clk_wait)`
310	13	gdevic	`begin`
311			`bank_exx <= bank_exx ^ ctl_reg_exx;`
312			`end`
313	3	gdevic	`end`
314
315	13	gdevic	`assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];`
316
317			`assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0];`
318
319			`assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];`
320
321			`assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;`
322
323	8	gdevic	`assign reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;`
324	3	gdevic
325			`endmodule`

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[/] [a-z80/] [trunk/] [cpu/] [registers/] [reg_control.v] - Blame information for rev 22