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[/] [a-z80/] [trunk/] [cpu/] [registers/] [reg_control.v] - Blame information for rev 8

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1 3 gdevic
// Copyright (C) 1991-2013 Altera Corporation
2
// Your use of Altera Corporation's design tools, logic functions 
3
// and other software and tools, and its AMPP partner logic 
4
// functions, and any output files from any of the foregoing 
5
// (including device programming or simulation files), and any 
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// associated documentation or information are expressly subject 
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// to the terms and conditions of the Altera Program License 
8
// Subscription Agreement, Altera MegaCore Function License 
9
// Agreement, or other applicable license agreement, including, 
10
// without limitation, that your use is for the sole purpose of 
11
// programming logic devices manufactured by Altera and sold by 
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// Altera or its authorized distributors.  Please refer to the 
13
// applicable agreement for further details.
14
 
15
// PROGRAM              "Quartus II 64-Bit"
16
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
17 8 gdevic
// CREATED              "Tue Mar 08 20:46:27 2016"
18 3 gdevic
 
19
module reg_control(
20
        ctl_reg_exx,
21
        ctl_reg_ex_af,
22
        ctl_reg_ex_de_hl,
23
        ctl_reg_use_sp,
24
        nreset,
25
        ctl_reg_sel_pc,
26
        ctl_reg_sel_ir,
27
        ctl_reg_sel_wz,
28
        ctl_reg_gp_we,
29
        ctl_reg_not_pc,
30
        use_ixiy,
31
        use_ix,
32
        ctl_reg_sys_we_lo,
33
        ctl_reg_sys_we_hi,
34
        ctl_reg_sys_we,
35
        clk,
36 8 gdevic
        ctl_sw_4d,
37 3 gdevic
        ctl_reg_gp_hilo,
38
        ctl_reg_gp_sel,
39
        ctl_reg_sys_hilo,
40
        reg_sel_bc,
41
        reg_sel_bc2,
42
        reg_sel_ix,
43
        reg_sel_iy,
44
        reg_sel_de,
45
        reg_sel_hl,
46
        reg_sel_de2,
47
        reg_sel_hl2,
48
        reg_sel_af,
49
        reg_sel_af2,
50
        reg_sel_wz,
51
        reg_sel_pc,
52
        reg_sel_ir,
53
        reg_sel_sp,
54
        reg_sel_gp_hi,
55
        reg_sel_gp_lo,
56
        reg_sel_sys_lo,
57
        reg_sel_sys_hi,
58
        reg_gp_we,
59
        reg_sys_we_lo,
60 8 gdevic
        reg_sys_we_hi,
61
        reg_sw_4d_lo,
62
        reg_sw_4d_hi
63 3 gdevic
);
64
 
65
 
66
input wire      ctl_reg_exx;
67
input wire      ctl_reg_ex_af;
68
input wire      ctl_reg_ex_de_hl;
69
input wire      ctl_reg_use_sp;
70
input wire      nreset;
71
input wire      ctl_reg_sel_pc;
72
input wire      ctl_reg_sel_ir;
73
input wire      ctl_reg_sel_wz;
74
input wire      ctl_reg_gp_we;
75
input wire      ctl_reg_not_pc;
76
input wire      use_ixiy;
77
input wire      use_ix;
78
input wire      ctl_reg_sys_we_lo;
79
input wire      ctl_reg_sys_we_hi;
80
input wire      ctl_reg_sys_we;
81
input wire      clk;
82 8 gdevic
input wire      ctl_sw_4d;
83 3 gdevic
input wire      [1:0] ctl_reg_gp_hilo;
84
input wire      [1:0] ctl_reg_gp_sel;
85
input wire      [1:0] ctl_reg_sys_hilo;
86
output wire     reg_sel_bc;
87
output wire     reg_sel_bc2;
88
output wire     reg_sel_ix;
89
output wire     reg_sel_iy;
90
output wire     reg_sel_de;
91
output wire     reg_sel_hl;
92
output wire     reg_sel_de2;
93
output wire     reg_sel_hl2;
94
output wire     reg_sel_af;
95
output wire     reg_sel_af2;
96
output wire     reg_sel_wz;
97
output wire     reg_sel_pc;
98
output wire     reg_sel_ir;
99
output wire     reg_sel_sp;
100
output wire     reg_sel_gp_hi;
101
output wire     reg_sel_gp_lo;
102
output wire     reg_sel_sys_lo;
103
output wire     reg_sel_sys_hi;
104
output wire     reg_gp_we;
105
output wire     reg_sys_we_lo;
106
output wire     reg_sys_we_hi;
107 8 gdevic
output wire     reg_sw_4d_lo;
108
output wire     reg_sw_4d_hi;
109 3 gdevic
 
110
reg     bank_af;
111
reg     bank_exx;
112
reg     bank_hl_de1;
113
reg     bank_hl_de2;
114 8 gdevic
wire    reg_sys_we_lo_ALTERA_SYNTHESIZED;
115 3 gdevic
wire    SYNTHESIZED_WIRE_52;
116
wire    SYNTHESIZED_WIRE_53;
117 8 gdevic
wire    SYNTHESIZED_WIRE_2;
118 3 gdevic
wire    SYNTHESIZED_WIRE_54;
119
wire    SYNTHESIZED_WIRE_55;
120 8 gdevic
wire    SYNTHESIZED_WIRE_5;
121 3 gdevic
wire    SYNTHESIZED_WIRE_56;
122 8 gdevic
wire    SYNTHESIZED_WIRE_10;
123 3 gdevic
wire    SYNTHESIZED_WIRE_57;
124 8 gdevic
wire    SYNTHESIZED_WIRE_58;
125
wire    SYNTHESIZED_WIRE_59;
126
wire    SYNTHESIZED_WIRE_60;
127 3 gdevic
wire    SYNTHESIZED_WIRE_21;
128
wire    SYNTHESIZED_WIRE_23;
129
wire    SYNTHESIZED_WIRE_24;
130
wire    SYNTHESIZED_WIRE_25;
131
wire    SYNTHESIZED_WIRE_30;
132
wire    SYNTHESIZED_WIRE_31;
133
wire    SYNTHESIZED_WIRE_32;
134 8 gdevic
wire    SYNTHESIZED_WIRE_61;
135 3 gdevic
wire    SYNTHESIZED_WIRE_34;
136
wire    SYNTHESIZED_WIRE_36;
137
wire    SYNTHESIZED_WIRE_37;
138
wire    SYNTHESIZED_WIRE_38;
139
wire    SYNTHESIZED_WIRE_39;
140
wire    SYNTHESIZED_WIRE_40;
141
wire    SYNTHESIZED_WIRE_41;
142
wire    SYNTHESIZED_WIRE_42;
143
wire    SYNTHESIZED_WIRE_43;
144
wire    SYNTHESIZED_WIRE_44;
145
wire    SYNTHESIZED_WIRE_45;
146
wire    SYNTHESIZED_WIRE_46;
147
wire    SYNTHESIZED_WIRE_47;
148 8 gdevic
wire    SYNTHESIZED_WIRE_48;
149
wire    SYNTHESIZED_WIRE_49;
150
wire    SYNTHESIZED_WIRE_50;
151 3 gdevic
 
152
assign  reg_sel_wz = ctl_reg_sel_wz;
153
assign  reg_sel_ir = ctl_reg_sel_ir;
154
assign  reg_sel_gp_hi = ctl_reg_gp_hilo[1];
155
assign  reg_sel_gp_lo = ctl_reg_gp_hilo[0];
156
assign  reg_sel_sys_lo = ctl_reg_sys_hilo[0];
157
assign  reg_sel_sys_hi = ctl_reg_sys_hilo[1];
158
assign  reg_gp_we = ctl_reg_gp_we;
159 8 gdevic
assign  reg_sw_4d_lo = ctl_sw_4d;
160 3 gdevic
 
161
 
162
 
163 8 gdevic
assign  reg_sel_bc = SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53;
164 3 gdevic
 
165 8 gdevic
assign  reg_sel_af = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_54;
166 3 gdevic
 
167 8 gdevic
assign  SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_55 & SYNTHESIZED_WIRE_5;
168 3 gdevic
 
169 8 gdevic
assign  reg_sel_sp = SYNTHESIZED_WIRE_55 & ctl_reg_use_sp;
170 3 gdevic
 
171
assign  SYNTHESIZED_WIRE_5 =  ~ctl_reg_use_sp;
172
 
173 8 gdevic
assign  reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;
174 3 gdevic
 
175 8 gdevic
assign  SYNTHESIZED_WIRE_37 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
176 3 gdevic
 
177 8 gdevic
assign  reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;
178 3 gdevic
 
179 8 gdevic
assign  reg_sel_af2 = bank_af & SYNTHESIZED_WIRE_54;
180 3 gdevic
 
181
assign  SYNTHESIZED_WIRE_2 =  ~bank_af;
182
 
183 8 gdevic
assign  SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
184 3 gdevic
 
185 8 gdevic
assign  SYNTHESIZED_WIRE_47 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
186 3 gdevic
 
187 8 gdevic
assign  SYNTHESIZED_WIRE_41 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
188 3 gdevic
 
189 8 gdevic
assign  SYNTHESIZED_WIRE_50 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
190 3 gdevic
 
191 8 gdevic
assign  SYNTHESIZED_WIRE_49 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
192 3 gdevic
 
193 8 gdevic
assign  reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;
194 3 gdevic
 
195 8 gdevic
assign  reg_sel_hl = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_23;
196 3 gdevic
 
197
assign  reg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24;
198
 
199
assign  reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;
200
 
201 8 gdevic
assign  SYNTHESIZED_WIRE_40 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
202 3 gdevic
 
203 8 gdevic
assign  SYNTHESIZED_WIRE_53 =  ~bank_exx;
204 3 gdevic
 
205 8 gdevic
assign  SYNTHESIZED_WIRE_46 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
206 3 gdevic
 
207 8 gdevic
assign  SYNTHESIZED_WIRE_45 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
208 3 gdevic
 
209 8 gdevic
assign  SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;
210 3 gdevic
 
211 8 gdevic
assign  SYNTHESIZED_WIRE_60 =  ~bank_hl_de1;
212 3 gdevic
 
213
assign  reg_sys_we_hi = ctl_reg_sys_we | ctl_reg_sys_we_hi;
214
 
215
assign  reg_sel_pc = ctl_reg_sel_pc & SYNTHESIZED_WIRE_32;
216
 
217 8 gdevic
assign  SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_61 & SYNTHESIZED_WIRE_34;
218 3 gdevic
 
219
assign  SYNTHESIZED_WIRE_32 =  ~ctl_reg_not_pc;
220
 
221
assign  SYNTHESIZED_WIRE_36 =  ~ctl_reg_gp_sel[1];
222
 
223 8 gdevic
assign  reg_sys_we_lo_ALTERA_SYNTHESIZED = ctl_reg_sys_we_lo | ctl_reg_sys_we;
224 3 gdevic
 
225 8 gdevic
assign  SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;
226 3 gdevic
 
227 8 gdevic
assign  SYNTHESIZED_WIRE_44 =  ~ctl_reg_gp_sel[0];
228 3 gdevic
 
229 8 gdevic
assign  SYNTHESIZED_WIRE_39 = ctl_reg_ex_de_hl & bank_exx;
230 3 gdevic
 
231
assign  SYNTHESIZED_WIRE_34 =  ~use_ixiy;
232
 
233 8 gdevic
assign  SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;
234 3 gdevic
 
235
assign  SYNTHESIZED_WIRE_10 =  ~use_ix;
236
 
237 8 gdevic
assign  SYNTHESIZED_WIRE_57 =  ~bank_hl_de2;
238 3 gdevic
 
239 8 gdevic
assign  SYNTHESIZED_WIRE_43 =  ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
240 3 gdevic
 
241 8 gdevic
 
242 3 gdevic
always@(posedge clk or negedge nreset)
243
begin
244
if (!nreset)
245
        begin
246
        bank_hl_de1 <= 0;
247
        end
248
else
249
        bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_37;
250
end
251
 
252 8 gdevic
assign  SYNTHESIZED_WIRE_42 =  ~SYNTHESIZED_WIRE_38;
253 3 gdevic
 
254 8 gdevic
 
255 3 gdevic
always@(posedge clk or negedge nreset)
256
begin
257
if (!nreset)
258
        begin
259
        bank_hl_de2 <= 0;
260
        end
261
else
262 8 gdevic
        bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_39;
263 3 gdevic
end
264
 
265 8 gdevic
assign  SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_40 | SYNTHESIZED_WIRE_41;
266 3 gdevic
 
267 8 gdevic
assign  reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_42;
268 3 gdevic
 
269 8 gdevic
assign  SYNTHESIZED_WIRE_38 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_43 & ctl_reg_sel_ir;
270 3 gdevic
 
271 8 gdevic
assign  SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_44 & ctl_reg_gp_sel[1];
272 3 gdevic
 
273 8 gdevic
assign  SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_45 | SYNTHESIZED_WIRE_46;
274 3 gdevic
 
275 8 gdevic
assign  SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_47 | SYNTHESIZED_WIRE_48;
276 3 gdevic
 
277 8 gdevic
assign  SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_49 | SYNTHESIZED_WIRE_50;
278
 
279
assign  SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
280
 
281 3 gdevic
assign  SYNTHESIZED_WIRE_30 =  ~ctl_reg_gp_sel[0];
282
 
283
assign  SYNTHESIZED_WIRE_31 =  ~ctl_reg_gp_sel[1];
284
 
285
 
286
always@(posedge clk or negedge nreset)
287
begin
288
if (!nreset)
289
        begin
290
        bank_exx <= 0;
291
        end
292
else
293
        bank_exx <= bank_exx ^ ctl_reg_exx;
294
end
295
 
296 8 gdevic
assign  reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
297 3 gdevic
 
298
 
299
always@(posedge clk or negedge nreset)
300
begin
301
if (!nreset)
302
        begin
303
        bank_af <= 0;
304
        end
305
else
306
        bank_af <= bank_af ^ ctl_reg_ex_af;
307
end
308
 
309 8 gdevic
assign  reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
310 3 gdevic
 
311
endmodule

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