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[/] [a-z80/] [trunk/] [cpu/] [registers/] [reg_file.v] - Blame information for rev 13

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1 3 gdevic
// Copyright (C) 1991-2013 Altera Corporation
2
// Your use of Altera Corporation's design tools, logic functions 
3
// and other software and tools, and its AMPP partner logic 
4
// functions, and any output files from any of the foregoing 
5
// (including device programming or simulation files), and any 
6
// associated documentation or information are expressly subject 
7
// to the terms and conditions of the Altera Program License 
8
// Subscription Agreement, Altera MegaCore Function License 
9
// Agreement, or other applicable license agreement, including, 
10
// without limitation, that your use is for the sole purpose of 
11
// programming logic devices manufactured by Altera and sold by 
12
// Altera or its authorized distributors.  Please refer to the 
13
// applicable agreement for further details.
14
 
15
// PROGRAM              "Quartus II 64-Bit"
16
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
17 8 gdevic
// CREATED              "Tue Mar 08 06:12:46 2016"
18 3 gdevic
 
19
module reg_file(
20
        reg_sel_sys_lo,
21
        reg_sel_gp_lo,
22
        reg_sel_sys_hi,
23
        reg_sel_gp_hi,
24
        reg_sel_ir,
25
        reg_sel_pc,
26
        ctl_sw_4u,
27
        reg_sel_wz,
28
        reg_sel_sp,
29
        reg_sel_iy,
30
        reg_sel_ix,
31
        reg_sel_hl2,
32
        reg_sel_hl,
33
        reg_sel_de2,
34
        reg_sel_de,
35
        reg_sel_bc2,
36
        reg_sel_bc,
37
        reg_sel_af2,
38
        reg_sel_af,
39
        reg_gp_we,
40
        reg_sys_we_lo,
41
        reg_sys_we_hi,
42
        ctl_reg_in_hi,
43
        ctl_reg_in_lo,
44
        ctl_reg_out_lo,
45
        ctl_reg_out_hi,
46
        clk,
47 8 gdevic
        reg_sw_4d_lo,
48
        reg_sw_4d_hi,
49 3 gdevic
        db_hi_as,
50
        db_hi_ds,
51
        db_lo_as,
52
        db_lo_ds
53
);
54
 
55
 
56
input wire      reg_sel_sys_lo;
57
input wire      reg_sel_gp_lo;
58
input wire      reg_sel_sys_hi;
59
input wire      reg_sel_gp_hi;
60
input wire      reg_sel_ir;
61
input wire      reg_sel_pc;
62
input wire      ctl_sw_4u;
63
input wire      reg_sel_wz;
64
input wire      reg_sel_sp;
65
input wire      reg_sel_iy;
66
input wire      reg_sel_ix;
67
input wire      reg_sel_hl2;
68
input wire      reg_sel_hl;
69
input wire      reg_sel_de2;
70
input wire      reg_sel_de;
71
input wire      reg_sel_bc2;
72
input wire      reg_sel_bc;
73
input wire      reg_sel_af2;
74
input wire      reg_sel_af;
75
input wire      reg_gp_we;
76
input wire      reg_sys_we_lo;
77
input wire      reg_sys_we_hi;
78
input wire      ctl_reg_in_hi;
79
input wire      ctl_reg_in_lo;
80
input wire      ctl_reg_out_lo;
81
input wire      ctl_reg_out_hi;
82
input wire      clk;
83 8 gdevic
input wire      reg_sw_4d_lo;
84
input wire      reg_sw_4d_hi;
85 3 gdevic
inout wire      [7:0] db_hi_as;
86
inout wire      [7:0] db_hi_ds;
87
inout wire      [7:0] db_lo_as;
88
inout wire      [7:0] db_lo_ds;
89
 
90
wire    [7:0] gdfx_temp0;
91
wire    [7:0] gdfx_temp1;
92
wire    SYNTHESIZED_WIRE_84;
93
wire    SYNTHESIZED_WIRE_85;
94
wire    SYNTHESIZED_WIRE_86;
95
wire    SYNTHESIZED_WIRE_28;
96
wire    SYNTHESIZED_WIRE_29;
97
wire    SYNTHESIZED_WIRE_30;
98
wire    SYNTHESIZED_WIRE_31;
99
wire    SYNTHESIZED_WIRE_32;
100
wire    SYNTHESIZED_WIRE_33;
101
wire    SYNTHESIZED_WIRE_34;
102
wire    SYNTHESIZED_WIRE_35;
103
wire    SYNTHESIZED_WIRE_36;
104
wire    SYNTHESIZED_WIRE_37;
105
wire    SYNTHESIZED_WIRE_38;
106
wire    SYNTHESIZED_WIRE_39;
107
wire    SYNTHESIZED_WIRE_40;
108
wire    SYNTHESIZED_WIRE_41;
109
wire    SYNTHESIZED_WIRE_42;
110
wire    SYNTHESIZED_WIRE_43;
111
wire    SYNTHESIZED_WIRE_44;
112
wire    SYNTHESIZED_WIRE_45;
113
wire    SYNTHESIZED_WIRE_46;
114
wire    SYNTHESIZED_WIRE_47;
115
wire    SYNTHESIZED_WIRE_48;
116
wire    SYNTHESIZED_WIRE_49;
117
wire    SYNTHESIZED_WIRE_50;
118
wire    SYNTHESIZED_WIRE_51;
119
wire    SYNTHESIZED_WIRE_52;
120
wire    SYNTHESIZED_WIRE_53;
121
wire    SYNTHESIZED_WIRE_54;
122
wire    SYNTHESIZED_WIRE_55;
123
wire    SYNTHESIZED_WIRE_56;
124
wire    SYNTHESIZED_WIRE_57;
125
wire    SYNTHESIZED_WIRE_58;
126
wire    SYNTHESIZED_WIRE_59;
127
wire    SYNTHESIZED_WIRE_60;
128
wire    SYNTHESIZED_WIRE_61;
129
wire    SYNTHESIZED_WIRE_62;
130
wire    SYNTHESIZED_WIRE_63;
131
wire    SYNTHESIZED_WIRE_64;
132
wire    SYNTHESIZED_WIRE_65;
133
wire    SYNTHESIZED_WIRE_66;
134
wire    SYNTHESIZED_WIRE_67;
135
wire    SYNTHESIZED_WIRE_68;
136
wire    SYNTHESIZED_WIRE_69;
137
wire    SYNTHESIZED_WIRE_70;
138
wire    SYNTHESIZED_WIRE_71;
139
wire    SYNTHESIZED_WIRE_72;
140
wire    SYNTHESIZED_WIRE_73;
141
wire    SYNTHESIZED_WIRE_74;
142
wire    SYNTHESIZED_WIRE_75;
143
wire    SYNTHESIZED_WIRE_76;
144
wire    SYNTHESIZED_WIRE_77;
145
wire    SYNTHESIZED_WIRE_78;
146
wire    SYNTHESIZED_WIRE_79;
147
wire    SYNTHESIZED_WIRE_80;
148
wire    SYNTHESIZED_WIRE_81;
149
wire    SYNTHESIZED_WIRE_82;
150
wire    SYNTHESIZED_WIRE_83;
151
 
152
 
153
 
154
 
155
assign  SYNTHESIZED_WIRE_82 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_wz;
156
 
157
assign  SYNTHESIZED_WIRE_80 = reg_sel_wz & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
158
 
159
assign  SYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_sp;
160
 
161
assign  SYNTHESIZED_WIRE_76 = reg_sel_sp & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
162
 
163
assign  SYNTHESIZED_WIRE_84 =  ~reg_sys_we_lo;
164
 
165
assign  SYNTHESIZED_WIRE_71 = reg_sel_gp_lo & reg_gp_we & reg_sel_iy;
166
 
167
assign  SYNTHESIZED_WIRE_85 =  ~reg_sys_we_hi;
168
 
169
assign  SYNTHESIZED_WIRE_74 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_pc;
170
 
171
assign  SYNTHESIZED_WIRE_67 = reg_sel_gp_lo & reg_gp_we & reg_sel_ix;
172
 
173
assign  SYNTHESIZED_WIRE_55 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl2;
174
 
175
assign  SYNTHESIZED_WIRE_72 = reg_sel_pc & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
176
 
177
assign  SYNTHESIZED_WIRE_59 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl;
178
 
179
assign  SYNTHESIZED_WIRE_47 = reg_sel_gp_lo & reg_gp_we & reg_sel_de2;
180
 
181
assign  SYNTHESIZED_WIRE_51 = reg_sel_gp_lo & reg_gp_we & reg_sel_de;
182
 
183
assign  SYNTHESIZED_WIRE_81 = reg_sel_wz & reg_sys_we_hi & reg_sel_sys_hi;
184
 
185
assign  SYNTHESIZED_WIRE_86 =  ~reg_gp_we;
186
 
187
assign  SYNTHESIZED_WIRE_70 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_iy;
188
 
189
assign  SYNTHESIZED_WIRE_68 = reg_sel_iy & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
190
 
191
assign  SYNTHESIZED_WIRE_39 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc2;
192
 
193
assign  SYNTHESIZED_WIRE_43 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc;
194
 
195
assign  SYNTHESIZED_WIRE_31 = reg_sel_gp_lo & reg_gp_we & reg_sel_af2;
196
 
197
assign  SYNTHESIZED_WIRE_77 = reg_sel_sp & reg_gp_we & reg_sel_gp_hi;
198
 
199
assign  SYNTHESIZED_WIRE_66 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_ix;
200
 
201
assign  SYNTHESIZED_WIRE_64 = reg_sel_ix & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
202
 
203
assign  SYNTHESIZED_WIRE_35 = reg_sel_gp_lo & reg_gp_we & reg_sel_af;
204
 
205
assign  SYNTHESIZED_WIRE_69 = reg_sel_iy & reg_gp_we & reg_sel_gp_hi;
206
 
207
assign  SYNTHESIZED_WIRE_63 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_ir;
208
 
209
assign  SYNTHESIZED_WIRE_65 = reg_sel_ix & reg_gp_we & reg_sel_gp_hi;
210
 
211
assign  SYNTHESIZED_WIRE_53 = reg_sel_hl2 & reg_gp_we & reg_sel_gp_hi;
212
 
213
assign  SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl2;
214
 
215
assign  SYNTHESIZED_WIRE_52 = reg_sel_hl2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
216
 
217
assign  SYNTHESIZED_WIRE_57 = reg_sel_hl & reg_gp_we & reg_sel_gp_hi;
218
 
219
assign  SYNTHESIZED_WIRE_45 = reg_sel_de2 & reg_gp_we & reg_sel_gp_hi;
220
 
221
assign  SYNTHESIZED_WIRE_49 = reg_sel_de & reg_gp_we & reg_sel_gp_hi;
222
 
223
assign  SYNTHESIZED_WIRE_37 = reg_sel_bc2 & reg_gp_we & reg_sel_gp_hi;
224
 
225
assign  SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl;
226
 
227
assign  SYNTHESIZED_WIRE_56 = reg_sel_hl & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
228
 
229
assign  SYNTHESIZED_WIRE_75 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_pc;
230
 
231
assign  SYNTHESIZED_WIRE_41 = reg_sel_bc & reg_gp_we & reg_sel_gp_hi;
232
 
233
assign  SYNTHESIZED_WIRE_29 = reg_sel_af2 & reg_gp_we & reg_sel_gp_hi;
234
 
235
assign  SYNTHESIZED_WIRE_33 = reg_sel_af & reg_gp_we & reg_sel_gp_hi;
236
 
237
assign  SYNTHESIZED_WIRE_61 = reg_sel_ir & reg_sys_we_hi & reg_sel_sys_hi;
238
 
239
assign  SYNTHESIZED_WIRE_46 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de2;
240
 
241
assign  SYNTHESIZED_WIRE_44 = reg_sel_de2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
242
 
243
assign  SYNTHESIZED_WIRE_73 = reg_sel_pc & reg_sys_we_hi & reg_sel_sys_hi;
244
 
245
assign  SYNTHESIZED_WIRE_83 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_wz;
246
 
247
assign  SYNTHESIZED_WIRE_50 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de;
248
 
249
assign  SYNTHESIZED_WIRE_48 = reg_sel_de & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
250
 
251
assign  SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc2;
252
 
253
assign  SYNTHESIZED_WIRE_36 = reg_sel_bc2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
254
 
255
assign  SYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc;
256
 
257
assign  SYNTHESIZED_WIRE_40 = reg_sel_bc & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
258
 
259
assign  SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af2;
260
 
261
assign  SYNTHESIZED_WIRE_28 = reg_sel_af2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
262
 
263
assign  SYNTHESIZED_WIRE_62 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_ir;
264
 
265
assign  SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af;
266
 
267
assign  SYNTHESIZED_WIRE_32 = reg_sel_af & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;
268
 
269
assign  SYNTHESIZED_WIRE_60 = reg_sel_ir & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;
270
 
271
assign  SYNTHESIZED_WIRE_79 = reg_sel_gp_lo & reg_gp_we & reg_sel_sp;
272
 
273
 
274
reg_latch       b2v_latch_af2_hi(
275
        .oe(SYNTHESIZED_WIRE_28),
276
        .we(SYNTHESIZED_WIRE_29),
277
        .clk(clk),
278
        .db(gdfx_temp1)
279
        );
280
 
281
 
282
reg_latch       b2v_latch_af2_lo(
283
        .oe(SYNTHESIZED_WIRE_30),
284
        .we(SYNTHESIZED_WIRE_31),
285
        .clk(clk),
286
        .db(gdfx_temp0)
287
        );
288
 
289
 
290
reg_latch       b2v_latch_af_hi(
291
        .oe(SYNTHESIZED_WIRE_32),
292
        .we(SYNTHESIZED_WIRE_33),
293
        .clk(clk),
294
        .db(gdfx_temp1)
295
        );
296
 
297
 
298
reg_latch       b2v_latch_af_lo(
299
        .oe(SYNTHESIZED_WIRE_34),
300
        .we(SYNTHESIZED_WIRE_35),
301
        .clk(clk),
302
        .db(gdfx_temp0)
303
        );
304
 
305
 
306
reg_latch       b2v_latch_bc2_hi(
307
        .oe(SYNTHESIZED_WIRE_36),
308
        .we(SYNTHESIZED_WIRE_37),
309
        .clk(clk),
310
        .db(gdfx_temp1)
311
        );
312
 
313
 
314
reg_latch       b2v_latch_bc2_lo(
315
        .oe(SYNTHESIZED_WIRE_38),
316
        .we(SYNTHESIZED_WIRE_39),
317
        .clk(clk),
318
        .db(gdfx_temp0)
319
        );
320
 
321
 
322
reg_latch       b2v_latch_bc_hi(
323
        .oe(SYNTHESIZED_WIRE_40),
324
        .we(SYNTHESIZED_WIRE_41),
325
        .clk(clk),
326
        .db(gdfx_temp1)
327
        );
328
 
329
 
330
reg_latch       b2v_latch_bc_lo(
331
        .oe(SYNTHESIZED_WIRE_42),
332
        .we(SYNTHESIZED_WIRE_43),
333
        .clk(clk),
334
        .db(gdfx_temp0)
335
        );
336
 
337
 
338
reg_latch       b2v_latch_de2_hi(
339
        .oe(SYNTHESIZED_WIRE_44),
340
        .we(SYNTHESIZED_WIRE_45),
341
        .clk(clk),
342
        .db(gdfx_temp1)
343
        );
344
 
345
 
346
reg_latch       b2v_latch_de2_lo(
347
        .oe(SYNTHESIZED_WIRE_46),
348
        .we(SYNTHESIZED_WIRE_47),
349
        .clk(clk),
350
        .db(gdfx_temp0)
351
        );
352
 
353
 
354
reg_latch       b2v_latch_de_hi(
355
        .oe(SYNTHESIZED_WIRE_48),
356
        .we(SYNTHESIZED_WIRE_49),
357
        .clk(clk),
358
        .db(gdfx_temp1)
359
        );
360
 
361
 
362
reg_latch       b2v_latch_de_lo(
363
        .oe(SYNTHESIZED_WIRE_50),
364
        .we(SYNTHESIZED_WIRE_51),
365
        .clk(clk),
366
        .db(gdfx_temp0)
367
        );
368
 
369
 
370
reg_latch       b2v_latch_hl2_hi(
371
        .oe(SYNTHESIZED_WIRE_52),
372
        .we(SYNTHESIZED_WIRE_53),
373
        .clk(clk),
374
        .db(gdfx_temp1)
375
        );
376
 
377
 
378
reg_latch       b2v_latch_hl2_lo(
379
        .oe(SYNTHESIZED_WIRE_54),
380
        .we(SYNTHESIZED_WIRE_55),
381
        .clk(clk),
382
        .db(gdfx_temp0)
383
        );
384
 
385
 
386
reg_latch       b2v_latch_hl_hi(
387
        .oe(SYNTHESIZED_WIRE_56),
388
        .we(SYNTHESIZED_WIRE_57),
389
        .clk(clk),
390
        .db(gdfx_temp1)
391
        );
392
 
393
 
394
reg_latch       b2v_latch_hl_lo(
395
        .oe(SYNTHESIZED_WIRE_58),
396
        .we(SYNTHESIZED_WIRE_59),
397
        .clk(clk),
398
        .db(gdfx_temp0)
399
        );
400
 
401
 
402
reg_latch       b2v_latch_ir_hi(
403
        .oe(SYNTHESIZED_WIRE_60),
404
        .we(SYNTHESIZED_WIRE_61),
405
        .clk(clk),
406
        .db(db_hi_as)
407
        );
408
 
409
 
410
reg_latch       b2v_latch_ir_lo(
411
        .oe(SYNTHESIZED_WIRE_62),
412
        .we(SYNTHESIZED_WIRE_63),
413
        .clk(clk),
414
        .db(db_lo_as)
415
        );
416
 
417
 
418
reg_latch       b2v_latch_ix_hi(
419
        .oe(SYNTHESIZED_WIRE_64),
420
        .we(SYNTHESIZED_WIRE_65),
421
        .clk(clk),
422
        .db(gdfx_temp1)
423
        );
424
 
425
 
426
reg_latch       b2v_latch_ix_lo(
427
        .oe(SYNTHESIZED_WIRE_66),
428
        .we(SYNTHESIZED_WIRE_67),
429
        .clk(clk),
430
        .db(gdfx_temp0)
431
        );
432
 
433
 
434
reg_latch       b2v_latch_iy_hi(
435
        .oe(SYNTHESIZED_WIRE_68),
436
        .we(SYNTHESIZED_WIRE_69),
437
        .clk(clk),
438
        .db(gdfx_temp1)
439
        );
440
 
441
 
442
reg_latch       b2v_latch_iy_lo(
443
        .oe(SYNTHESIZED_WIRE_70),
444
        .we(SYNTHESIZED_WIRE_71),
445
        .clk(clk),
446
        .db(gdfx_temp0)
447
        );
448
 
449
 
450
reg_latch       b2v_latch_pc_hi(
451
        .oe(SYNTHESIZED_WIRE_72),
452
        .we(SYNTHESIZED_WIRE_73),
453
        .clk(clk),
454
        .db(db_hi_as)
455
        );
456
 
457
 
458
reg_latch       b2v_latch_pc_lo(
459
        .oe(SYNTHESIZED_WIRE_74),
460
        .we(SYNTHESIZED_WIRE_75),
461
        .clk(clk),
462
        .db(db_lo_as)
463
        );
464
 
465
 
466
reg_latch       b2v_latch_sp_hi(
467
        .oe(SYNTHESIZED_WIRE_76),
468
        .we(SYNTHESIZED_WIRE_77),
469
        .clk(clk),
470
        .db(gdfx_temp1)
471
        );
472
 
473
 
474
reg_latch       b2v_latch_sp_lo(
475
        .oe(SYNTHESIZED_WIRE_78),
476
        .we(SYNTHESIZED_WIRE_79),
477
        .clk(clk),
478
        .db(gdfx_temp0)
479
        );
480
 
481
 
482
reg_latch       b2v_latch_wz_hi(
483
        .oe(SYNTHESIZED_WIRE_80),
484
        .we(SYNTHESIZED_WIRE_81),
485
        .clk(clk),
486
        .db(gdfx_temp1)
487
        );
488
 
489
 
490
reg_latch       b2v_latch_wz_lo(
491
        .oe(SYNTHESIZED_WIRE_82),
492
        .we(SYNTHESIZED_WIRE_83),
493
        .clk(clk),
494
        .db(gdfx_temp0)
495
        );
496
 
497
assign  gdfx_temp0[7] = ctl_sw_4u ? db_lo_as[7] : 1'bz;
498
assign  gdfx_temp0[6] = ctl_sw_4u ? db_lo_as[6] : 1'bz;
499
assign  gdfx_temp0[5] = ctl_sw_4u ? db_lo_as[5] : 1'bz;
500
assign  gdfx_temp0[4] = ctl_sw_4u ? db_lo_as[4] : 1'bz;
501
assign  gdfx_temp0[3] = ctl_sw_4u ? db_lo_as[3] : 1'bz;
502
assign  gdfx_temp0[2] = ctl_sw_4u ? db_lo_as[2] : 1'bz;
503
assign  gdfx_temp0[1] = ctl_sw_4u ? db_lo_as[1] : 1'bz;
504
assign  gdfx_temp0[0] = ctl_sw_4u ? db_lo_as[0] : 1'bz;
505
 
506 8 gdevic
assign  db_lo_as[7] = reg_sw_4d_lo ? gdfx_temp0[7] : 1'bz;
507
assign  db_lo_as[6] = reg_sw_4d_lo ? gdfx_temp0[6] : 1'bz;
508
assign  db_lo_as[5] = reg_sw_4d_lo ? gdfx_temp0[5] : 1'bz;
509
assign  db_lo_as[4] = reg_sw_4d_lo ? gdfx_temp0[4] : 1'bz;
510
assign  db_lo_as[3] = reg_sw_4d_lo ? gdfx_temp0[3] : 1'bz;
511
assign  db_lo_as[2] = reg_sw_4d_lo ? gdfx_temp0[2] : 1'bz;
512
assign  db_lo_as[1] = reg_sw_4d_lo ? gdfx_temp0[1] : 1'bz;
513
assign  db_lo_as[0] = reg_sw_4d_lo ? gdfx_temp0[0] : 1'bz;
514 3 gdevic
 
515
assign  gdfx_temp1[7] = ctl_sw_4u ? db_hi_as[7] : 1'bz;
516
assign  gdfx_temp1[6] = ctl_sw_4u ? db_hi_as[6] : 1'bz;
517
assign  gdfx_temp1[5] = ctl_sw_4u ? db_hi_as[5] : 1'bz;
518
assign  gdfx_temp1[4] = ctl_sw_4u ? db_hi_as[4] : 1'bz;
519
assign  gdfx_temp1[3] = ctl_sw_4u ? db_hi_as[3] : 1'bz;
520
assign  gdfx_temp1[2] = ctl_sw_4u ? db_hi_as[2] : 1'bz;
521
assign  gdfx_temp1[1] = ctl_sw_4u ? db_hi_as[1] : 1'bz;
522
assign  gdfx_temp1[0] = ctl_sw_4u ? db_hi_as[0] : 1'bz;
523
 
524 8 gdevic
assign  db_hi_as[7] = reg_sw_4d_hi ? gdfx_temp1[7] : 1'bz;
525
assign  db_hi_as[6] = reg_sw_4d_hi ? gdfx_temp1[6] : 1'bz;
526
assign  db_hi_as[5] = reg_sw_4d_hi ? gdfx_temp1[5] : 1'bz;
527
assign  db_hi_as[4] = reg_sw_4d_hi ? gdfx_temp1[4] : 1'bz;
528
assign  db_hi_as[3] = reg_sw_4d_hi ? gdfx_temp1[3] : 1'bz;
529
assign  db_hi_as[2] = reg_sw_4d_hi ? gdfx_temp1[2] : 1'bz;
530
assign  db_hi_as[1] = reg_sw_4d_hi ? gdfx_temp1[1] : 1'bz;
531
assign  db_hi_as[0] = reg_sw_4d_hi ? gdfx_temp1[0] : 1'bz;
532 3 gdevic
 
533
assign  db_lo_ds[7] = ctl_reg_out_lo ? gdfx_temp0[7] : 1'bz;
534
assign  db_lo_ds[6] = ctl_reg_out_lo ? gdfx_temp0[6] : 1'bz;
535
assign  db_lo_ds[5] = ctl_reg_out_lo ? gdfx_temp0[5] : 1'bz;
536
assign  db_lo_ds[4] = ctl_reg_out_lo ? gdfx_temp0[4] : 1'bz;
537
assign  db_lo_ds[3] = ctl_reg_out_lo ? gdfx_temp0[3] : 1'bz;
538
assign  db_lo_ds[2] = ctl_reg_out_lo ? gdfx_temp0[2] : 1'bz;
539
assign  db_lo_ds[1] = ctl_reg_out_lo ? gdfx_temp0[1] : 1'bz;
540
assign  db_lo_ds[0] = ctl_reg_out_lo ? gdfx_temp0[0] : 1'bz;
541
 
542
assign  gdfx_temp0[7] = ctl_reg_in_lo ? db_lo_ds[7] : 1'bz;
543
assign  gdfx_temp0[6] = ctl_reg_in_lo ? db_lo_ds[6] : 1'bz;
544
assign  gdfx_temp0[5] = ctl_reg_in_lo ? db_lo_ds[5] : 1'bz;
545
assign  gdfx_temp0[4] = ctl_reg_in_lo ? db_lo_ds[4] : 1'bz;
546
assign  gdfx_temp0[3] = ctl_reg_in_lo ? db_lo_ds[3] : 1'bz;
547
assign  gdfx_temp0[2] = ctl_reg_in_lo ? db_lo_ds[2] : 1'bz;
548
assign  gdfx_temp0[1] = ctl_reg_in_lo ? db_lo_ds[1] : 1'bz;
549
assign  gdfx_temp0[0] = ctl_reg_in_lo ? db_lo_ds[0] : 1'bz;
550
 
551
assign  db_hi_ds[7] = ctl_reg_out_hi ? gdfx_temp1[7] : 1'bz;
552
assign  db_hi_ds[6] = ctl_reg_out_hi ? gdfx_temp1[6] : 1'bz;
553
assign  db_hi_ds[5] = ctl_reg_out_hi ? gdfx_temp1[5] : 1'bz;
554
assign  db_hi_ds[4] = ctl_reg_out_hi ? gdfx_temp1[4] : 1'bz;
555
assign  db_hi_ds[3] = ctl_reg_out_hi ? gdfx_temp1[3] : 1'bz;
556
assign  db_hi_ds[2] = ctl_reg_out_hi ? gdfx_temp1[2] : 1'bz;
557
assign  db_hi_ds[1] = ctl_reg_out_hi ? gdfx_temp1[1] : 1'bz;
558
assign  db_hi_ds[0] = ctl_reg_out_hi ? gdfx_temp1[0] : 1'bz;
559
 
560
assign  gdfx_temp1[7] = ctl_reg_in_hi ? db_hi_ds[7] : 1'bz;
561
assign  gdfx_temp1[6] = ctl_reg_in_hi ? db_hi_ds[6] : 1'bz;
562
assign  gdfx_temp1[5] = ctl_reg_in_hi ? db_hi_ds[5] : 1'bz;
563
assign  gdfx_temp1[4] = ctl_reg_in_hi ? db_hi_ds[4] : 1'bz;
564
assign  gdfx_temp1[3] = ctl_reg_in_hi ? db_hi_ds[3] : 1'bz;
565
assign  gdfx_temp1[2] = ctl_reg_in_hi ? db_hi_ds[2] : 1'bz;
566
assign  gdfx_temp1[1] = ctl_reg_in_hi ? db_hi_ds[1] : 1'bz;
567
assign  gdfx_temp1[0] = ctl_reg_in_hi ? db_hi_ds[0] : 1'bz;
568
 
569
 
570
endmodule

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