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gdevic |
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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*/
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(header "symbol" (version "1.2"))
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(symbol
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(rect 64 64 184 160)
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(text "reg_latch" (rect 5 0 58 14)(font "Arial" (font_size 8)))
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(text "inst" (rect 8 80 25 92)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
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(text "oe" (rect 21 27 35 41)(font "Arial" (font_size 8)))
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(line (pt 0 32)(pt 16 32))
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)
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(port
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(pt 0 48)
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(input)
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(text "we" (rect 0 0 18 14)(font "Arial" (font_size 8)))
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(text "we" (rect 21 43 39 57)(font "Arial" (font_size 8)))
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(line (pt 0 48)(pt 16 48))
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)
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(port
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(pt 120 64)
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(input)
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(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
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(text "clk" (rect 73 56 88 70)(font "Arial" (font_size 8)))
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(line (pt 104 64)(pt 120 64))
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)
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(port
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(pt 120 32)
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(bidir)
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(text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
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(text "db[7..0]" (rect 57 27 99 41)(font "Arial" (font_size 8)))
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(line (pt 120 32)(pt 104 32)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 104 80))
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)
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(fill (color 85 255 127))
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)
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