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[/] [a-z80/] [trunk/] [cpu/] [toplevel/] [test_top.sv] - Blame information for rev 4

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//--------------------------------------------------------------
// Testbench for the top level design
//--------------------------------------------------------------
`include "z80.svh"
 
module test_bench_top(z80_if.tb z);
 
assign clk = z.CLK;
 
initial begin : init
    $display("Test: Start of test at %d", $time);
    z.nWAIT <= `CLR;
    z.nINT <= `CLR;
    z.nNMI <= `CLR;
    z.nBUSRQ <= `CLR;
    force dut.z80_top_ifc_n.fpga_reset=1;
    z.nRESET <= `SET;
#2  force dut.z80_top_ifc_n.fpga_reset=0;
    repeat (3) @(posedge clk);
    z.nRESET <= `CLR;
end : init
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Testbench for interrupt testing
// Enable one or more interrupt generators and run them with the
// 'hello world' code
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
// Infuse a NMI at a certain clock
initial begin : nmi_once
    repeat (500) @(posedge clk);
//    z.nNMI <= `SET;
    repeat (1) @(posedge clk);
    z.nNMI <= `CLR;
end : nmi_once
 
// Test sending a *periodic* NMI
always begin : nmi_rep
    repeat (3000) @(posedge clk);
//    z.nNMI <= `SET;
    repeat (1) @(posedge clk);
    z.nNMI <= `CLR;
end : nmi_rep
 
// Infuse an INT at a certain clock
initial begin : int_once
    repeat (1000) @(posedge clk);
//    z.nINT <= `SET;
    repeat (300) @(posedge clk);
    z.nINT <= `CLR;
end : int_once
 
// Test sending a *periodic* INT
always begin : int_rep
    repeat (5000) @(posedge clk);
//    z.nINT <= `SET;
    repeat (300) @(posedge clk);
    z.nINT <= `CLR;
end : int_rep
 
// Test WAIT.. inject at will
initial begin : wait_once
    repeat (1008) @(posedge clk);
//    z.nWAIT <= `SET;
    repeat (2) @(posedge clk);
    z.nWAIT <= `CLR;
end : wait_once
 
// Test BUSRQ / BUSACK
initial begin : busrq_once
    repeat (10) @(posedge clk);
//    z.nBUSRQ <= `SET;
    repeat (10) @(posedge clk);
    z.nBUSRQ <= `CLR;
end : busrq_once
 
// Test special RESET
initial begin : spc_reset
    repeat (40) @(posedge clk);
//    z.nRESET <= `SET;
    repeat (1) @(posedge clk);
    z.nRESET <= `CLR;
end : spc_reset
 
endmodule
 
module test_top();
 
// Although the clock is going forever, we will stop simulation at some point
bit clk = 1;
initial forever #1 clk = ~clk;
 
// Stop after printing "Hello, World!"
initial begin : stopme
    #70000 $stop();
end : stopme
 
z80_if z80(clk);            // Instantiate the Z80 bus interface
z80_top_ifc_n dut(z80);     // Create an instance of our Z80 design
test_bench_top tb(z80);     // Create an instance of the test bench
 
ram  ram( .Address(z80.A), .Data(z80.D), .CS(z80.nMREQ), .WE(z80.nWR), .OE(z80.nRD) );
io   io( .Address(z80.A), .Data(z80.D), .CS(z80.nIORQ), .WE(z80.nWR), .OE(z80.nRD) );
iorq iorq( .Data(z80.D), .M1(z80.nM1), .IORQ(z80.nIORQ) );
 
endmodule

Line No.	Rev	Author	Line
1	3	gdevic	`//--------------------------------------------------------------`
2			`// Testbench for the top level design`
3			`//--------------------------------------------------------------`
4			`include "z80.svh"
5
6			`module test_bench_top(z80_if.tb z);`
7
8			`assign clk = z.CLK;`
9
10			`initial begin : init`
11			`$display("Test: Start of test at %d", $time);`
12			z.nWAIT <= `CLR;
13			z.nINT <= `CLR;
14			z.nNMI <= `CLR;
15			z.nBUSRQ <= `CLR;
16			`force dut.z80_top_ifc_n.fpga_reset=1;`
17			z.nRESET <= `SET;
18			`#2 force dut.z80_top_ifc_n.fpga_reset=0;`
19			`repeat (3) @(posedge clk);`
20			z.nRESET <= `CLR;
21			`end : init`
22
23			`//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
24			`// Testbench for interrupt testing`
25			`// Enable one or more interrupt generators and run them with the`
26			`// 'hello world' code`
27			`//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
28
29			`// Infuse a NMI at a certain clock`
30			`initial begin : nmi_once`
31			`repeat (500) @(posedge clk);`
32			// z.nNMI <= `SET;
33			`repeat (1) @(posedge clk);`
34			z.nNMI <= `CLR;
35			`end : nmi_once`
36
37			`// Test sending a periodic NMI`
38			`always begin : nmi_rep`
39			`repeat (3000) @(posedge clk);`
40			// z.nNMI <= `SET;
41			`repeat (1) @(posedge clk);`
42			z.nNMI <= `CLR;
43			`end : nmi_rep`
44
45			`// Infuse an INT at a certain clock`
46			`initial begin : int_once`
47			`repeat (1000) @(posedge clk);`
48			// z.nINT <= `SET;
49			`repeat (300) @(posedge clk);`
50			z.nINT <= `CLR;
51			`end : int_once`
52
53			`// Test sending a periodic INT`
54			`always begin : int_rep`
55			`repeat (5000) @(posedge clk);`
56			// z.nINT <= `SET;
57			`repeat (300) @(posedge clk);`
58			z.nINT <= `CLR;
59			`end : int_rep`
60
61			`// Test WAIT.. inject at will`
62			`initial begin : wait_once`
63			`repeat (1008) @(posedge clk);`
64			// z.nWAIT <= `SET;
65			`repeat (2) @(posedge clk);`
66			z.nWAIT <= `CLR;
67			`end : wait_once`
68
69			`// Test BUSRQ / BUSACK`
70			`initial begin : busrq_once`
71			`repeat (10) @(posedge clk);`
72			// z.nBUSRQ <= `SET;
73			`repeat (10) @(posedge clk);`
74			z.nBUSRQ <= `CLR;
75			`end : busrq_once`
76
77			`// Test special RESET`
78			`initial begin : spc_reset`
79			`repeat (40) @(posedge clk);`
80			// z.nRESET <= `SET;
81			`repeat (1) @(posedge clk);`
82			z.nRESET <= `CLR;
83			`end : spc_reset`
84
85			`endmodule`
86
87			`module test_top();`
88
89			`// Although the clock is going forever, we will stop simulation at some point`
90			`bit clk = 1;`
91			`initial forever #1 clk = ~clk;`
92
93			`// Stop after printing "Hello, World!"`
94			`initial begin : stopme`
95			`#70000 $stop();`
96			`end : stopme`
97
98			`z80_if z80(clk); // Instantiate the Z80 bus interface`
99			`z80_top_ifc_n dut(z80); // Create an instance of our Z80 design`
100			`test_bench_top tb(z80); // Create an instance of the test bench`
101
102			`ram ram( .Address(z80.A), .Data(z80.D), .CS(z80.nMREQ), .WE(z80.nWR), .OE(z80.nRD) );`
103			`io io( .Address(z80.A), .Data(z80.D), .CS(z80.nIORQ), .WE(z80.nWR), .OE(z80.nRD) );`
104			`iorq iorq( .Data(z80.D), .M1(z80.nM1), .IORQ(z80.nIORQ) );`
105
106			`endmodule`

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[/] [a-z80/] [trunk/] [cpu/] [toplevel/] [test_top.sv] - Blame information for rev 4