Subversion Repositories a-z80

// file: clock.v

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//----------------------------------------------------------------------------

// User entered comments

//----------------------------------------------------------------------------

// None

//

//----------------------------------------------------------------------------

// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"

// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"

//----------------------------------------------------------------------------

// CLK_OUT1____10.000______0.000______50.0_____1200.000____150.000

// CLK_OUT2____50.000______0.000______50.0______200.000____150.000

//

//----------------------------------------------------------------------------

// "Input Clock   Freq (MHz)    Input Jitter (UI)"

//----------------------------------------------------------------------------

// __primary_________100.000____________0.010

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "clock,clk_wiz_v3_6,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)

module clock

 (// Clock in ports

  input         CLK_IN1,

  // Clock out ports

  output        CLK_OUT1,

  output        CLK_OUT2,

  // Status and control signals

  output        LOCKED

 );

  // Input buffering

  //------------------------------------

  IBUFG clkin1_buf

   (.O (clkin1),

    .I (CLK_IN1));

  // Clocking primitive

  //------------------------------------

  // Instantiation of the DCM primitive

  //    * Unused inputs are tied off

  //    * Unused outputs are labeled unused

  wire        psdone_unused;

  wire        locked_int;

  wire [7:0]  status_int;

  wire clkfb;

  wire clk0;

  wire clkfx;

  DCM_SP

  #(.CLKDV_DIVIDE          (5.000),

    .CLKFX_DIVIDE          (10),

    .CLKFX_MULTIPLY        (2),

    .CLKIN_DIVIDE_BY_2     ("TRUE"),

    .CLKIN_PERIOD          (10.0),

    .CLKOUT_PHASE_SHIFT    ("NONE"),

    .CLK_FEEDBACK          ("1X"),

    .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS"),

    .PHASE_SHIFT           (0),

    .STARTUP_WAIT          ("FALSE"))

  dcm_sp_inst

    // Input clock

   (.CLKIN                 (clkin1),

    .CLKFB                 (clkfb),

    // Output clocks

    .CLK0                  (clk0),

    .CLK90                 (),

    .CLK180                (),

    .CLK270                (),

    .CLK2X                 (),

    .CLK2X180              (),

    .CLKFX                 (clkfx),

    .CLKFX180              (),

    .CLKDV                 (),

    // Ports for dynamic phase shift

    .PSCLK                 (1'b0),

    .PSEN                  (1'b0),

    .PSINCDEC              (1'b0),

    .PSDONE                (),

    // Other control and status signals

    .LOCKED                (locked_int),

    .STATUS                (status_int),

    .RST                   (1'b0),

    // Unused pin- tie low

    .DSSEN                 (1'b0));

    assign LOCKED = locked_int;

  // Output buffering

  //-----------------------------------

  assign clkfb = CLK_OUT2;

  BUFG clkout1_buf

   (.O   (CLK_OUT1),

    .I   (clkfx));

  BUFG clkout2_buf

   (.O   (CLK_OUT2),

    .I   (clk0));

endmodule