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[/] [a-z80/] [trunk/] [host/] [basic_nexys3/] [ram.v] - Blame information for rev 21

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1 8 gdevic
module ram(clk, addr, we, data_in, data_out);
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parameter n = 4;
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input clk, we;
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input [n-1:0] addr;
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input [7:0] data_in;
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output reg [7:0] data_out;
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reg [7:0] reg_array [2**n-1:0];
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initial $readmemb("ram.mif", reg_array);
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always @(posedge clk)
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begin
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    if (we == 1)
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        reg_array[addr] <= data_in;
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    data_out = reg_array[addr];
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end
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endmodule

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