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[/] [ac97/] [trunk/] [bench/] [verilog/] [ac97_codec_sin.v] - Blame information for rev 20

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE AC 97 Codec                                       ////
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////  Serial Input Block                                         ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: ac97_codec_sin.v,v 1.2 2002-09-19 06:36:19 rudi Exp $
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//
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//  $Date: 2002-09-19 06:36:19 $
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//  $Revision: 1.2 $
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//  $Author: rudi $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.1  2002/02/13 08:22:32  rudi
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//
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//               Added test bench for public release
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//
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//
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//
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//
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`include "ac97_defines.v"
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module ac97_codec_sin(clk, rst,
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        sync,
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        slt0, slt1, slt2, slt3, slt4, slt5,
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        slt6, slt7, slt8, slt9, slt10, slt11, slt12,
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        sdata_in
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        );
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input           clk, rst;
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// --------------------------------------
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// Misc Signals
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input           sync;
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output  [15:0]   slt0;
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output  [19:0]   slt1;
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output  [19:0]   slt2;
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output  [19:0]   slt3;
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output  [19:0]   slt4;
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output  [19:0]   slt5;
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output  [19:0]   slt6;
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output  [19:0]   slt7;
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output  [19:0]   slt8;
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output  [19:0]   slt9;
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output  [19:0]   slt10;
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output  [19:0]   slt11;
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output  [19:0]   slt12;
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// --------------------------------------
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// AC97 Codec Interface
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input           sdata_in;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg             sdata_in_r;
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reg     [19:0]   sr;
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reg     [15:0]   slt0;
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reg     [19:0]   slt1;
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reg     [19:0]   slt2;
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reg     [19:0]   slt3;
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reg     [19:0]   slt4;
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reg     [19:0]   slt5;
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reg     [19:0]   slt6;
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reg     [19:0]   slt7;
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reg     [19:0]   slt8;
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reg     [19:0]   slt9;
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reg     [19:0]   slt10;
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reg     [19:0]   slt11;
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reg     [19:0]   slt12;
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wire    [12:0]   le;
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////////////////////////////////////////////////////////////////////
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//
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// Latch Enable logic
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//
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// Sync Edge Detector
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reg             sync_r;
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wire            sync_e;
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always @(posedge clk)
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        sync_r <= #1 sync;
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assign sync_e = sync & !sync_r;
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// Frame Counter
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reg     [7:0]    cnt;
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always @(posedge clk)
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        if(sync_e)      cnt <= #1 0;
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        else            cnt <= #1 cnt + 1;
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assign le[0] = (cnt == 16);
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assign le[1] = (cnt == 36);
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assign le[2] = (cnt == 56);
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assign le[3] = (cnt == 76);
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assign le[4] = (cnt == 96);
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assign le[5] = (cnt == 116);
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assign le[6] = (cnt == 136);
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assign le[7] = (cnt == 156);
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assign le[8] = (cnt == 176);
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assign le[9] = (cnt == 196);
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assign le[10] = (cnt == 216);
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assign le[11] = (cnt == 236);
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assign le[12] = (cnt == 0);
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////////////////////////////////////////////////////////////////////
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//
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// Output registers
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//
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always @(posedge clk)
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        if(le[0])        slt0 <= #1 sr[15:0];
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always @(posedge clk)
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        if(le[1])       slt1 <= #1 sr;
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always @(posedge clk)
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        if(le[2])       slt2 <= #1 sr;
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always @(posedge clk)
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        if(le[3])       slt3 <= #1 sr;
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always @(posedge clk)
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        if(le[4])       slt4 <= #1 sr;
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always @(posedge clk)
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        if(le[5])       slt5 <= #1 sr;
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always @(posedge clk)
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        if(le[6])       slt6 <= #1 sr;
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always @(posedge clk)
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        if(le[7])       slt7 <= #1 sr;
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always @(posedge clk)
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        if(le[8])       slt8 <= #1 sr;
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always @(posedge clk)
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        if(le[9])       slt9 <= #1 sr;
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always @(posedge clk)
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        if(le[10])      slt10 <= #1 sr;
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always @(posedge clk)
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        if(le[11])      slt11 <= #1 sr;
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always @(posedge clk)
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        if(le[12])      slt12 <= #1 sr;
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////////////////////////////////////////////////////////////////////
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//
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// Serial Shift Register
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//
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always @(negedge clk)
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        sdata_in_r <= #1 sdata_in;
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always @(posedge clk)
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        sr <= #1 {sr[18:0], sdata_in_r };
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endmodule
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