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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Codec Top Level                             ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_codec_top.v,v 1.2 2002-09-19 06:36:19 rudi Exp $
//
//  $Date: 2002-09-19 06:36:19 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2002/02/13 08:22:32  rudi
//
//               Added test bench for public release
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_codec_top(clk, rst,
        sync,
        sdata_out,
        sdata_in
        );
 
input           clk, rst;
 
// --------------------------------------
// AC97 Codec Interface
input           sync;
output          sdata_out;
input           sdata_in;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
wire    [15:0]   out_slt0;
wire    [19:0]   out_slt1;
wire    [19:0]   out_slt2;
wire    [19:0]   out_slt3;
wire    [19:0]   out_slt4;
wire    [19:0]   out_slt5;
wire    [19:0]   out_slt6;
wire    [19:0]   out_slt7;
wire    [19:0]   out_slt8;
wire    [19:0]   out_slt9;
wire    [19:0]   out_slt10;
wire    [19:0]   out_slt11;
wire    [19:0]   out_slt12;
 
wire    [15:0]   in_slt0;
wire    [19:0]   in_slt1;
reg     [19:0]   in_slt2;
reg     [19:0]   in_slt3;
reg     [19:0]   in_slt4;
reg     [19:0]   in_slt5;
reg     [19:0]   in_slt6;
reg     [19:0]   in_slt7;
reg     [19:0]   in_slt8;
reg     [19:0]   in_slt9;
reg     [19:0]   in_slt10;
reg     [19:0]   in_slt11;
reg     [19:0]   in_slt12;
 
reg     [19:0]   smem[0:32];
reg     [19:0]   rmem[0:32];
 
reg     [15:0]   s0;
reg     [19:0]   s1;
 
integer         rs1_ptr, rs2_ptr;
integer         rs3_ptr, rs4_ptr, rs5_ptr, rs6_ptr, rs7_ptr;
integer         rs8_ptr, rs9_ptr, rs10_ptr, rs11_ptr, rs12_ptr;
integer         is2_ptr, is3_ptr, is4_ptr, is5_ptr, is6_ptr, is7_ptr;
integer         is8_ptr, is9_ptr, is10_ptr, is11_ptr, is12_ptr;
 
reg     [19:0]   rslt0;
reg     [19:0]   rslt1;
reg     [19:0]   rslt2;
reg     [19:0]   rs1_mem[0:256];
reg     [19:0]   rs2_mem[0:256];
reg     [19:0]   rs3_mem[0:256];
reg     [19:0]   rs4_mem[0:256];
reg     [19:0]   rs5_mem[0:256];
reg     [19:0]   rs6_mem[0:256];
reg     [19:0]   rs7_mem[0:256];
reg     [19:0]   rs8_mem[0:256];
reg     [19:0]   rs9_mem[0:256];
reg     [19:0]   rs10_mem[0:256];
reg     [19:0]   rs11_mem[0:256];
reg     [19:0]   rs12_mem[0:256];
 
reg     [19:0]   is2_mem[0:256];
reg     [19:0]   is3_mem[0:256];
reg     [19:0]   is4_mem[0:256];
reg     [19:0]   is5_mem[0:256];
reg     [19:0]   is6_mem[0:256];
reg     [19:0]   is7_mem[0:256];
reg     [19:0]   is8_mem[0:256];
reg     [19:0]   is9_mem[0:256];
reg     [19:0]   is10_mem[0:256];
reg     [19:0]   is11_mem[0:256];
reg     [19:0]   is12_mem[0:256];
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
task init;
input   mode;
 
integer mode;
begin
 
fill_mem(mode);
clr_ptrs;
 
end
endtask
 
task fill_mem;
input   mode;
 
integer mode;
integer n;
 
begin
 
if(mode==0)
for(n=0;n<256;n=n+1)
   begin
        is2_mem[n] = { 4'h0, n[11:0], 4'h0 };
        is3_mem[n] = { 4'h1, n[11:0], 4'h0 };
        is4_mem[n] = { 4'h2, n[11:0], 4'h0 };
        is5_mem[n] = { 4'h3, n[11:0], 4'h0 };
        is6_mem[n] = { 4'h4, n[11:0], 4'h0 };
        is7_mem[n] = { 4'h5, n[11:0], 4'h0 };
        is8_mem[n] = { 4'h6, n[11:0], 4'h0 };
        is9_mem[n] = { 4'h7, n[11:0], 4'h0 };
        is10_mem[n] = { 4'h8, n[11:0], 4'h0 };
        is11_mem[n] = { 4'h9, n[11:0], 4'h0 };
        is12_mem[n] = { 4'ha, n[11:0], 4'h0 };
   end
else
for(n=0;n<256;n=n+1)
   begin
        is2_mem[n] = $random;
        is3_mem[n] = $random;
        is4_mem[n] = $random;
        is5_mem[n] = $random;
        is6_mem[n] = $random;
        is7_mem[n] = $random;
        is8_mem[n] = $random;
        is9_mem[n] = $random;
        is10_mem[n] = $random;
        is11_mem[n] = $random;
        is12_mem[n] = $random;
   end
 
end
endtask
 
always @(posedge clk)
        if(!rst)        s0 = 0;
 
always @(posedge clk)
        if(!rst)        s1 = 0;
 
assign in_slt0  = s0;
assign in_slt1  = s1;
 
 
//always @(posedge sync)
always @(rslt0 or rslt1 or s0)
        if(s0[13] | (rslt0[14] & rslt1[19]) )
           begin
                in_slt2 = #1 is2_mem[is2_ptr];
                is2_ptr = is2_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[12])
           begin
                in_slt3 = #1 is3_mem[is3_ptr];
                is3_ptr = is3_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[11])
           begin
                in_slt4 = #1 is4_mem[is4_ptr];
                is4_ptr = is4_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[10])
           begin
                in_slt5 = #1 is5_mem[is5_ptr];
                is5_ptr = is5_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[9])
           begin
                in_slt6 = #1 is6_mem[is6_ptr];
                is6_ptr = is6_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[8])
           begin
                in_slt7 = #1 is7_mem[is7_ptr];
                is7_ptr = is7_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[7])
           begin
                in_slt8 = #1 is8_mem[is8_ptr];
                is8_ptr = is8_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[6])
           begin
                in_slt9 = #1 is9_mem[is9_ptr];
                is9_ptr = is9_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[5])
           begin
                in_slt10 = #1 is10_mem[is10_ptr];
                is10_ptr = is10_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[4])
           begin
                in_slt11 = #1 is11_mem[is11_ptr];
                is11_ptr = is11_ptr + 1;
           end
 
always @(posedge sync)
        if(s0[3])
           begin
                in_slt12 = #1 is12_mem[is12_ptr];
                is12_ptr = is12_ptr + 1;
           end
 
always @(posedge sync)
   begin
        rslt0 <= #2 out_slt0;
        rslt1 <= #2 out_slt1;
        rslt2 <= #2 out_slt2;
   end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[14])
           begin
                rs1_mem[rs1_ptr] = #1 out_slt1;
                rs1_ptr = rs1_ptr + 1;
                //$display("INFO: Codec Register Addr: %h (%t)", out_slt1, $time);
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[13])
           begin
                rs2_mem[rs2_ptr] = #1 out_slt2;
                rs2_ptr = rs2_ptr + 1;
                //$display("INFO: Codec Register Data: %h (%t)", out_slt2, $time);
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[12])
           begin
                rs3_mem[rs3_ptr] = #1 out_slt3;
                rs3_ptr = rs3_ptr + 1;
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[11])
           begin
                rs4_mem[rs4_ptr] = #1 out_slt4;
                rs4_ptr = rs4_ptr + 1;
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[10])
           begin
                rs5_mem[rs5_ptr] = #1 out_slt5;
                rs5_ptr = rs5_ptr + 1;
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[9])
           begin
                rs6_mem[rs6_ptr] = #1 out_slt6;
                rs6_ptr = rs6_ptr + 1;
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[8])
           begin
                rs7_mem[rs7_ptr] = #1 out_slt7;
                rs7_ptr = rs7_ptr + 1;
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[7])
           begin
                rs8_mem[rs8_ptr] = #1 out_slt8;
                rs8_ptr = rs8_ptr + 1;
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[6])
           begin
                rs9_mem[rs9_ptr] = #1 out_slt9;
                rs9_ptr = rs9_ptr + 1;
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[5])
           begin
                rs10_mem[rs10_ptr] = #1 out_slt10;
                rs10_ptr = rs10_ptr + 1;
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[4])
           begin
                rs11_mem[rs11_ptr] = #1 out_slt11;
                rs11_ptr = rs11_ptr + 1;
           end
 
always @(posedge sync)
        if(out_slt0[15] & out_slt0[3])
           begin
                rs12_mem[rs12_ptr] = #1 out_slt12;
                rs12_ptr = rs12_ptr + 1;
           end
 
 
task clr_ptrs;
 
begin
 
rs1_ptr = 0;
rs2_ptr = 0;
rs3_ptr = 0;
rs4_ptr = 0;
rs5_ptr = 0;
rs6_ptr = 0;
rs7_ptr = 0;
rs8_ptr = 0;
rs9_ptr = 0;
rs10_ptr = 0;
rs11_ptr = 0;
rs12_ptr = 0;
 
is2_ptr = 0;
is3_ptr = 0;
is4_ptr = 0;
is5_ptr = 0;
is6_ptr = 0;
is7_ptr = 0;
is8_ptr = 0;
is9_ptr = 0;
is10_ptr = 0;
is11_ptr = 0;
is12_ptr = 0;
 
end
endtask
 
 
task set_tag;
input           cr;
input   [11:0]   tag;
 
// s0 - 16 bits
// 15 - Codec Ready
// 14:3 - Slot 1-12 Valid bits
// 2:0 - RESERVED (stuffed with 0)
begin
s0 = {cr, tag, 3'h0};
end
endtask
 
 
task set_req;
input   [9:0]    req;
 
reg     [6:0]    idx;
begin
 
idx = out_slt1[18:12];
s1 = {1'b0, idx, ~req, 2'h0};
 
end
endtask
 
 
task tx1;
input   fcnt_max;       // Total number fo frames
input   rdy_del;        // How many frames before codec is ready
input   ovalid;         // Out Channels valid (Surround Sound)
input   ivalid;         // In Channels Valid (Mic & Line In)
input   oint;           // Output Intervals
input   iint;           // input Intervals
 
integer         fcnt_max, f;
integer         rdy_del;
reg     [9:0]    ovalid, ivalid;
reg     [19:0]   oint, iint;
 
reg             och0_v;
reg     [1:0]    och0_cnt;
reg             och1_v;
reg     [1:0]    och1_cnt;
reg             och2_v;
reg     [1:0]    och2_cnt;
reg             och3_v;
reg     [1:0]    och3_cnt;
reg             och4_v;
reg     [1:0]    och4_cnt;
reg             och5_v;
reg     [1:0]    och5_cnt;
reg             och6_v;
reg     [1:0]    och6_cnt;
reg             och7_v;
reg     [1:0]    och7_cnt;
reg             och8_v;
reg     [1:0]    och8_cnt;
reg             och9_v;
reg     [1:0]    och9_cnt;
reg             ich0_v;
reg     [1:0]    ich0_cnt;
reg             ich1_v;
reg     [1:0]    ich1_cnt;
reg             ich2_v;
reg     [1:0]    ich2_cnt;
reg             ich3_v;
reg     [1:0]    ich3_cnt;
reg             ich4_v;
reg     [1:0]    ich4_cnt;
reg             ich5_v;
reg     [1:0]    ich5_cnt;
reg             ich6_v;
reg     [1:0]    ich6_cnt;
reg             ich7_v;
reg     [1:0]    ich7_cnt;
reg             ich8_v;
reg     [1:0]    ich8_cnt;
reg             ich9_v;
reg     [1:0]    ich9_cnt;
 
begin
 
och0_cnt = 0;
och1_cnt = 0;
och2_cnt = 0;
och3_cnt = 0;
och4_cnt = 0;
och5_cnt = 0;
och6_cnt = 0;
och7_cnt = 0;
och8_cnt = 0;
och9_cnt = 0;
 
ich0_cnt = 0;
ich1_cnt = 0;
ich2_cnt = 0;
ich3_cnt = 0;
ich4_cnt = 0;
ich5_cnt = 0;
ich6_cnt = 0;
ich7_cnt = 0;
ich8_cnt = 0;
ich9_cnt = 0;
 
for(f=0;f<fcnt_max;f=f+1)
   begin
        while(!sync)    @(posedge clk);
        if(f>rdy_del)
           begin
 
                och0_v = ovalid[9] & (och0_cnt == oint[19:18]);
                if(och0_v)      och0_cnt = 0;
                else            och0_cnt = och0_cnt + 1;
                och1_v = ovalid[8] & (och1_cnt == oint[17:16]);
                if(och1_v)      och1_cnt = 0;
                else            och1_cnt = och1_cnt + 1;
                och2_v = ovalid[7] & (och2_cnt == oint[15:14]);
                if(och2_v)      och2_cnt = 0;
                else            och2_cnt = och2_cnt + 1;
                och3_v = ovalid[6] & (och3_cnt == oint[13:12]);
                if(och3_v)      och3_cnt = 0;
                else            och3_cnt = och3_cnt + 1;
                och4_v = ovalid[5] & (och4_cnt == oint[11:10]);
                if(och4_v)      och4_cnt = 0;
                else            och4_cnt = och4_cnt + 1;
                och5_v = ovalid[4] & (och5_cnt == oint[9:8]);
                if(och5_v)      och5_cnt = 0;
                else            och5_cnt = och5_cnt + 1;
                och6_v = ovalid[3] & (och6_cnt == oint[7:6]);
                if(och6_v)      och6_cnt = 0;
                else            och6_cnt = och6_cnt + 1;
                och7_v = ovalid[2] & (och7_cnt == oint[5:4]);
                if(och7_v)      och7_cnt = 0;
                else            och7_cnt = och7_cnt + 1;
                och8_v = ovalid[1] & (och8_cnt == oint[3:2]);
                if(och8_v)      och8_cnt = 0;
                else            och8_cnt = och8_cnt + 1;
                och9_v = ovalid[0] & (och9_cnt == oint[1:0]);
                if(och9_v)      och9_cnt = 0;
                else            och9_cnt = och9_cnt + 1;
 
                ich0_v = ivalid[9] & (ich0_cnt == iint[19:18]);
                if(ich0_v)      ich0_cnt = 0;
                else            ich0_cnt = ich0_cnt + 1;
                ich1_v = ivalid[8] & (ich1_cnt == iint[17:16]);
                if(ich1_v)      ich1_cnt = 0;
                else            ich1_cnt = ich1_cnt + 1;
                ich2_v = ivalid[7] & (ich2_cnt == iint[15:14]);
                if(ich2_v)      ich2_cnt = 0;
                else            ich2_cnt = ich2_cnt + 1;
                ich3_v = ivalid[6] & (ich3_cnt == iint[13:12]);
                if(ich3_v)      ich3_cnt = 0;
                else            ich3_cnt = ich3_cnt + 1;
                ich4_v = ivalid[5] & (ich4_cnt == iint[11:10]);
                if(ich4_v)      ich4_cnt = 0;
                else            ich4_cnt = ich4_cnt + 1;
                ich5_v = ivalid[4] & (ich5_cnt == iint[9:8]);
                if(ich5_v)      ich5_cnt = 0;
                else            ich5_cnt = ich5_cnt + 1;
                ich6_v = ivalid[3] & (ich6_cnt == iint[7:6]);
                if(ich6_v)      ich6_cnt = 0;
                else            ich6_cnt = ich6_cnt + 1;
                ich7_v = ivalid[2] & (ich7_cnt == iint[5:4]);
                if(ich7_v)      ich7_cnt = 0;
                else            ich7_cnt = ich7_cnt + 1;
                ich8_v = ivalid[1] & (ich8_cnt == iint[3:2]);
                if(ich8_v)      ich8_cnt = 0;
                else            ich8_cnt = ich8_cnt + 1;
                ich9_v = ivalid[0] & (ich9_cnt == iint[1:0]);
                if(ich9_v)      ich9_cnt = 0;
                else            ich9_cnt = ich9_cnt + 1;
 
                set_tag(1'b1, { 1'b0,           // Slot 1
                                1'b0,           // Slot 2
                                ich0_v, ich1_v, ich2_v, ich3_v, ich4_v,
                                ich5_v, ich6_v, ich7_v, ich8_v, ich9_v} );
 
                set_req( {      och0_v, och1_v, och2_v, och3_v, och4_v,
                                och5_v, och6_v, och7_v, och8_v, och9_v} );
 
           end
        while(sync)     @(posedge clk);
   end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Modules
//
 
ac97_codec_sin  u0(
                .clk(           clk             ),
                .rst(           rst             ),
                .sync(          sync            ),
                .slt0(          out_slt0        ),
                .slt1(          out_slt1        ),
                .slt2(          out_slt2        ),
                .slt3(          out_slt3        ),
                .slt4(          out_slt4        ),
                .slt5(          out_slt5        ),
                .slt6(          out_slt6        ),
                .slt7(          out_slt7        ),
                .slt8(          out_slt8        ),
                .slt9(          out_slt9        ),
                .slt10(         out_slt10       ),
                .slt11(         out_slt11       ),
                .slt12(         out_slt12       ),
                .sdata_in(      sdata_in        )
                );
 
ac97_codec_sout u1(
                .clk(           clk             ),
                .rst(           rst             ),
                .sync(          sync            ),
                .slt0(          in_slt0         ),
                .slt1(          in_slt1         ),
                .slt2(          in_slt2         ),
                .slt3(          in_slt3         ),
                .slt4(          in_slt4         ),
                .slt5(          in_slt5         ),
                .slt6(          in_slt6         ),
                .slt7(          in_slt7         ),
                .slt8(          in_slt8         ),
                .slt9(          in_slt9         ),
                .slt10(         in_slt10        ),
                .slt11(         in_slt11        ),
                .slt12(         in_slt12        ),
                .sdata_out(     sdata_out       )
                );
 
endmodule
 
 

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[/] [ac97/] [trunk/] [bench/] [verilog/] [ac97_codec_top.v] - Blame information for rev 20

Line No.	Rev	Author	Line
1	7	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Codec Top Level ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	15	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17	7	rudi	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	15	rudi	`// $Id: ac97_codec_top.v,v 1.2 2002-09-19 06:36:19 rudi Exp $`
42	7	rudi	`//`
43	15	rudi	`// $Date: 2002-09-19 06:36:19 $`
44			`// $Revision: 1.2 $`
45	7	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	15	rudi	`// Revision 1.1 2002/02/13 08:22:32 rudi`
52	7	rudi	`//`
53	15	rudi	`// Added test bench for public release`
54	7	rudi	`//`
55			`//`
56	15	rudi	`//`
57			`//`
58	7	rudi
59			`include "ac97_defines.v"
60
61			`module ac97_codec_top(clk, rst,`
62			`sync,`
63			`sdata_out,`
64			`sdata_in`
65			`);`
66
67			`input clk, rst;`
68
69			`// --------------------------------------`
70			`// AC97 Codec Interface`
71			`input sync;`
72			`output sdata_out;`
73			`input sdata_in;`
74
75			`////////////////////////////////////////////////////////////////////`
76			`//`
77			`// Local Wires`
78			`//`
79
80			`wire [15:0] out_slt0;`
81			`wire [19:0] out_slt1;`
82			`wire [19:0] out_slt2;`
83			`wire [19:0] out_slt3;`
84			`wire [19:0] out_slt4;`
85			`wire [19:0] out_slt5;`
86			`wire [19:0] out_slt6;`
87			`wire [19:0] out_slt7;`
88			`wire [19:0] out_slt8;`
89			`wire [19:0] out_slt9;`
90			`wire [19:0] out_slt10;`
91			`wire [19:0] out_slt11;`
92			`wire [19:0] out_slt12;`
93
94			`wire [15:0] in_slt0;`
95			`wire [19:0] in_slt1;`
96			`reg [19:0] in_slt2;`
97			`reg [19:0] in_slt3;`
98			`reg [19:0] in_slt4;`
99			`reg [19:0] in_slt5;`
100			`reg [19:0] in_slt6;`
101			`reg [19:0] in_slt7;`
102			`reg [19:0] in_slt8;`
103			`reg [19:0] in_slt9;`
104			`reg [19:0] in_slt10;`
105			`reg [19:0] in_slt11;`
106			`reg [19:0] in_slt12;`
107
108			`reg [19:0] smem[0:32];`
109			`reg [19:0] rmem[0:32];`
110
111			`reg [15:0] s0;`
112			`reg [19:0] s1;`
113
114			`integer rs1_ptr, rs2_ptr;`
115			`integer rs3_ptr, rs4_ptr, rs5_ptr, rs6_ptr, rs7_ptr;`
116			`integer rs8_ptr, rs9_ptr, rs10_ptr, rs11_ptr, rs12_ptr;`
117			`integer is2_ptr, is3_ptr, is4_ptr, is5_ptr, is6_ptr, is7_ptr;`
118			`integer is8_ptr, is9_ptr, is10_ptr, is11_ptr, is12_ptr;`
119
120			`reg [19:0] rslt0;`
121			`reg [19:0] rslt1;`
122			`reg [19:0] rslt2;`
123			`reg [19:0] rs1_mem[0:256];`
124			`reg [19:0] rs2_mem[0:256];`
125			`reg [19:0] rs3_mem[0:256];`
126			`reg [19:0] rs4_mem[0:256];`
127			`reg [19:0] rs5_mem[0:256];`
128			`reg [19:0] rs6_mem[0:256];`
129			`reg [19:0] rs7_mem[0:256];`
130			`reg [19:0] rs8_mem[0:256];`
131			`reg [19:0] rs9_mem[0:256];`
132			`reg [19:0] rs10_mem[0:256];`
133			`reg [19:0] rs11_mem[0:256];`
134			`reg [19:0] rs12_mem[0:256];`
135
136			`reg [19:0] is2_mem[0:256];`
137			`reg [19:0] is3_mem[0:256];`
138			`reg [19:0] is4_mem[0:256];`
139			`reg [19:0] is5_mem[0:256];`
140			`reg [19:0] is6_mem[0:256];`
141			`reg [19:0] is7_mem[0:256];`
142			`reg [19:0] is8_mem[0:256];`
143			`reg [19:0] is9_mem[0:256];`
144			`reg [19:0] is10_mem[0:256];`
145			`reg [19:0] is11_mem[0:256];`
146			`reg [19:0] is12_mem[0:256];`
147
148			`////////////////////////////////////////////////////////////////////`
149			`//`
150			`// Misc Logic`
151			`//`
152
153			`task init;`
154			`input mode;`
155
156			`integer mode;`
157			`begin`
158
159			`fill_mem(mode);`
160			`clr_ptrs;`
161
162			`end`
163			`endtask`
164
165			`task fill_mem;`
166			`input mode;`
167
168			`integer mode;`
169			`integer n;`
170
171			`begin`
172
173			`if(mode==0)`
174			`for(n=0;n<256;n=n+1)`
175			`begin`
176			`is2_mem[n] = { 4'h0, n[11:0], 4'h0 };`
177			`is3_mem[n] = { 4'h1, n[11:0], 4'h0 };`
178			`is4_mem[n] = { 4'h2, n[11:0], 4'h0 };`
179			`is5_mem[n] = { 4'h3, n[11:0], 4'h0 };`
180			`is6_mem[n] = { 4'h4, n[11:0], 4'h0 };`
181			`is7_mem[n] = { 4'h5, n[11:0], 4'h0 };`
182			`is8_mem[n] = { 4'h6, n[11:0], 4'h0 };`
183			`is9_mem[n] = { 4'h7, n[11:0], 4'h0 };`
184			`is10_mem[n] = { 4'h8, n[11:0], 4'h0 };`
185			`is11_mem[n] = { 4'h9, n[11:0], 4'h0 };`
186			`is12_mem[n] = { 4'ha, n[11:0], 4'h0 };`
187			`end`
188			`else`
189			`for(n=0;n<256;n=n+1)`
190			`begin`
191			`is2_mem[n] = $random;`
192			`is3_mem[n] = $random;`
193			`is4_mem[n] = $random;`
194			`is5_mem[n] = $random;`
195			`is6_mem[n] = $random;`
196			`is7_mem[n] = $random;`
197			`is8_mem[n] = $random;`
198			`is9_mem[n] = $random;`
199			`is10_mem[n] = $random;`
200			`is11_mem[n] = $random;`
201			`is12_mem[n] = $random;`
202			`end`
203
204			`end`
205			`endtask`
206
207			`always @(posedge clk)`
208			`if(!rst) s0 = 0;`
209
210			`always @(posedge clk)`
211			`if(!rst) s1 = 0;`
212
213			`assign in_slt0 = s0;`
214			`assign in_slt1 = s1;`
215
216
217			`//always @(posedge sync)`
218			`always @(rslt0 or rslt1 or s0)`
219			`if(s0[13] \| (rslt0[14] & rslt1[19]) )`
220			`begin`
221			`in_slt2 = #1 is2_mem[is2_ptr];`
222			`is2_ptr = is2_ptr + 1;`
223			`end`
224
225			`always @(posedge sync)`
226			`if(s0[12])`
227			`begin`
228			`in_slt3 = #1 is3_mem[is3_ptr];`
229			`is3_ptr = is3_ptr + 1;`
230			`end`
231
232			`always @(posedge sync)`
233			`if(s0[11])`
234			`begin`
235			`in_slt4 = #1 is4_mem[is4_ptr];`
236			`is4_ptr = is4_ptr + 1;`
237			`end`
238
239			`always @(posedge sync)`
240			`if(s0[10])`
241			`begin`
242			`in_slt5 = #1 is5_mem[is5_ptr];`
243			`is5_ptr = is5_ptr + 1;`
244			`end`
245
246			`always @(posedge sync)`
247			`if(s0[9])`
248			`begin`
249			`in_slt6 = #1 is6_mem[is6_ptr];`
250			`is6_ptr = is6_ptr + 1;`
251			`end`
252
253			`always @(posedge sync)`
254			`if(s0[8])`
255			`begin`
256			`in_slt7 = #1 is7_mem[is7_ptr];`
257			`is7_ptr = is7_ptr + 1;`
258			`end`
259
260			`always @(posedge sync)`
261			`if(s0[7])`
262			`begin`
263			`in_slt8 = #1 is8_mem[is8_ptr];`
264			`is8_ptr = is8_ptr + 1;`
265			`end`
266
267			`always @(posedge sync)`
268			`if(s0[6])`
269			`begin`
270			`in_slt9 = #1 is9_mem[is9_ptr];`
271			`is9_ptr = is9_ptr + 1;`
272			`end`
273
274			`always @(posedge sync)`
275			`if(s0[5])`
276			`begin`
277			`in_slt10 = #1 is10_mem[is10_ptr];`
278			`is10_ptr = is10_ptr + 1;`
279			`end`
280
281			`always @(posedge sync)`
282			`if(s0[4])`
283			`begin`
284			`in_slt11 = #1 is11_mem[is11_ptr];`
285			`is11_ptr = is11_ptr + 1;`
286			`end`
287
288			`always @(posedge sync)`
289			`if(s0[3])`
290			`begin`
291			`in_slt12 = #1 is12_mem[is12_ptr];`
292			`is12_ptr = is12_ptr + 1;`
293			`end`
294
295			`always @(posedge sync)`
296			`begin`
297			`rslt0 <= #2 out_slt0;`
298			`rslt1 <= #2 out_slt1;`
299			`rslt2 <= #2 out_slt2;`
300			`end`
301
302			`always @(posedge sync)`
303			`if(out_slt0[15] & out_slt0[14])`
304			`begin`
305			`rs1_mem[rs1_ptr] = #1 out_slt1;`
306			`rs1_ptr = rs1_ptr + 1;`
307			`//$display("INFO: Codec Register Addr: %h (%t)", out_slt1, $time);`
308			`end`
309
310			`always @(posedge sync)`
311			`if(out_slt0[15] & out_slt0[13])`
312			`begin`
313			`rs2_mem[rs2_ptr] = #1 out_slt2;`
314			`rs2_ptr = rs2_ptr + 1;`
315			`//$display("INFO: Codec Register Data: %h (%t)", out_slt2, $time);`
316			`end`
317
318			`always @(posedge sync)`
319			`if(out_slt0[15] & out_slt0[12])`
320			`begin`
321			`rs3_mem[rs3_ptr] = #1 out_slt3;`
322			`rs3_ptr = rs3_ptr + 1;`
323			`end`
324
325			`always @(posedge sync)`
326			`if(out_slt0[15] & out_slt0[11])`
327			`begin`
328			`rs4_mem[rs4_ptr] = #1 out_slt4;`
329			`rs4_ptr = rs4_ptr + 1;`
330			`end`
331
332			`always @(posedge sync)`
333			`if(out_slt0[15] & out_slt0[10])`
334			`begin`
335			`rs5_mem[rs5_ptr] = #1 out_slt5;`
336			`rs5_ptr = rs5_ptr + 1;`
337			`end`
338
339			`always @(posedge sync)`
340			`if(out_slt0[15] & out_slt0[9])`
341			`begin`
342			`rs6_mem[rs6_ptr] = #1 out_slt6;`
343			`rs6_ptr = rs6_ptr + 1;`
344			`end`
345
346			`always @(posedge sync)`
347			`if(out_slt0[15] & out_slt0[8])`
348			`begin`
349			`rs7_mem[rs7_ptr] = #1 out_slt7;`
350			`rs7_ptr = rs7_ptr + 1;`
351			`end`
352
353			`always @(posedge sync)`
354			`if(out_slt0[15] & out_slt0[7])`
355			`begin`
356			`rs8_mem[rs8_ptr] = #1 out_slt8;`
357			`rs8_ptr = rs8_ptr + 1;`
358			`end`
359
360			`always @(posedge sync)`
361			`if(out_slt0[15] & out_slt0[6])`
362			`begin`
363			`rs9_mem[rs9_ptr] = #1 out_slt9;`
364			`rs9_ptr = rs9_ptr + 1;`
365			`end`
366
367			`always @(posedge sync)`
368			`if(out_slt0[15] & out_slt0[5])`
369			`begin`
370			`rs10_mem[rs10_ptr] = #1 out_slt10;`
371			`rs10_ptr = rs10_ptr + 1;`
372			`end`
373
374			`always @(posedge sync)`
375			`if(out_slt0[15] & out_slt0[4])`
376			`begin`
377			`rs11_mem[rs11_ptr] = #1 out_slt11;`
378			`rs11_ptr = rs11_ptr + 1;`
379			`end`
380
381			`always @(posedge sync)`
382			`if(out_slt0[15] & out_slt0[3])`
383			`begin`
384			`rs12_mem[rs12_ptr] = #1 out_slt12;`
385			`rs12_ptr = rs12_ptr + 1;`
386			`end`
387
388
389			`task clr_ptrs;`
390
391			`begin`
392
393			`rs1_ptr = 0;`
394			`rs2_ptr = 0;`
395			`rs3_ptr = 0;`
396			`rs4_ptr = 0;`
397			`rs5_ptr = 0;`
398			`rs6_ptr = 0;`
399			`rs7_ptr = 0;`
400			`rs8_ptr = 0;`
401			`rs9_ptr = 0;`
402			`rs10_ptr = 0;`
403			`rs11_ptr = 0;`
404			`rs12_ptr = 0;`
405
406			`is2_ptr = 0;`
407			`is3_ptr = 0;`
408			`is4_ptr = 0;`
409			`is5_ptr = 0;`
410			`is6_ptr = 0;`
411			`is7_ptr = 0;`
412			`is8_ptr = 0;`
413			`is9_ptr = 0;`
414			`is10_ptr = 0;`
415			`is11_ptr = 0;`
416			`is12_ptr = 0;`
417
418			`end`
419			`endtask`
420
421
422			`task set_tag;`
423			`input cr;`
424			`input [11:0] tag;`
425
426			`// s0 - 16 bits`
427			`// 15 - Codec Ready`
428			`// 14:3 - Slot 1-12 Valid bits`
429			`// 2:0 - RESERVED (stuffed with 0)`
430			`begin`
431			`s0 = {cr, tag, 3'h0};`
432			`end`
433			`endtask`
434
435
436			`task set_req;`
437			`input [9:0] req;`
438
439			`reg [6:0] idx;`
440			`begin`
441
442			`idx = out_slt1[18:12];`
443			`s1 = {1'b0, idx, ~req, 2'h0};`
444
445			`end`
446			`endtask`
447
448
449			`task tx1;`
450			`input fcnt_max; // Total number fo frames`
451			`input rdy_del; // How many frames before codec is ready`
452			`input ovalid; // Out Channels valid (Surround Sound)`
453			`input ivalid; // In Channels Valid (Mic & Line In)`
454			`input oint; // Output Intervals`
455			`input iint; // input Intervals`
456
457			`integer fcnt_max, f;`
458			`integer rdy_del;`
459			`reg [9:0] ovalid, ivalid;`
460			`reg [19:0] oint, iint;`
461
462			`reg och0_v;`
463			`reg [1:0] och0_cnt;`
464			`reg och1_v;`
465			`reg [1:0] och1_cnt;`
466			`reg och2_v;`
467			`reg [1:0] och2_cnt;`
468			`reg och3_v;`
469			`reg [1:0] och3_cnt;`
470			`reg och4_v;`
471			`reg [1:0] och4_cnt;`
472			`reg och5_v;`
473			`reg [1:0] och5_cnt;`
474			`reg och6_v;`
475			`reg [1:0] och6_cnt;`
476			`reg och7_v;`
477			`reg [1:0] och7_cnt;`
478			`reg och8_v;`
479			`reg [1:0] och8_cnt;`
480			`reg och9_v;`
481			`reg [1:0] och9_cnt;`
482			`reg ich0_v;`
483			`reg [1:0] ich0_cnt;`
484			`reg ich1_v;`
485			`reg [1:0] ich1_cnt;`
486			`reg ich2_v;`
487			`reg [1:0] ich2_cnt;`
488			`reg ich3_v;`
489			`reg [1:0] ich3_cnt;`
490			`reg ich4_v;`
491			`reg [1:0] ich4_cnt;`
492			`reg ich5_v;`
493			`reg [1:0] ich5_cnt;`
494			`reg ich6_v;`
495			`reg [1:0] ich6_cnt;`
496			`reg ich7_v;`
497			`reg [1:0] ich7_cnt;`
498			`reg ich8_v;`
499			`reg [1:0] ich8_cnt;`
500			`reg ich9_v;`
501			`reg [1:0] ich9_cnt;`
502
503			`begin`
504
505			`och0_cnt = 0;`
506			`och1_cnt = 0;`
507			`och2_cnt = 0;`
508			`och3_cnt = 0;`
509			`och4_cnt = 0;`
510			`och5_cnt = 0;`
511			`och6_cnt = 0;`
512			`och7_cnt = 0;`
513			`och8_cnt = 0;`
514			`och9_cnt = 0;`
515
516			`ich0_cnt = 0;`
517			`ich1_cnt = 0;`
518			`ich2_cnt = 0;`
519			`ich3_cnt = 0;`
520			`ich4_cnt = 0;`
521			`ich5_cnt = 0;`
522			`ich6_cnt = 0;`
523			`ich7_cnt = 0;`
524			`ich8_cnt = 0;`
525			`ich9_cnt = 0;`
526
527			`for(f=0;f<fcnt_max;f=f+1)`
528			`begin`
529			`while(!sync) @(posedge clk);`
530			`if(f>rdy_del)`
531			`begin`
532
533			`och0_v = ovalid[9] & (och0_cnt == oint[19:18]);`
534			`if(och0_v) och0_cnt = 0;`
535			`else och0_cnt = och0_cnt + 1;`
536			`och1_v = ovalid[8] & (och1_cnt == oint[17:16]);`
537			`if(och1_v) och1_cnt = 0;`
538			`else och1_cnt = och1_cnt + 1;`
539			`och2_v = ovalid[7] & (och2_cnt == oint[15:14]);`
540			`if(och2_v) och2_cnt = 0;`
541			`else och2_cnt = och2_cnt + 1;`
542			`och3_v = ovalid[6] & (och3_cnt == oint[13:12]);`
543			`if(och3_v) och3_cnt = 0;`
544			`else och3_cnt = och3_cnt + 1;`
545			`och4_v = ovalid[5] & (och4_cnt == oint[11:10]);`
546			`if(och4_v) och4_cnt = 0;`
547			`else och4_cnt = och4_cnt + 1;`
548			`och5_v = ovalid[4] & (och5_cnt == oint[9:8]);`
549			`if(och5_v) och5_cnt = 0;`
550			`else och5_cnt = och5_cnt + 1;`
551			`och6_v = ovalid[3] & (och6_cnt == oint[7:6]);`
552			`if(och6_v) och6_cnt = 0;`
553			`else och6_cnt = och6_cnt + 1;`
554			`och7_v = ovalid[2] & (och7_cnt == oint[5:4]);`
555			`if(och7_v) och7_cnt = 0;`
556			`else och7_cnt = och7_cnt + 1;`
557			`och8_v = ovalid[1] & (och8_cnt == oint[3:2]);`
558			`if(och8_v) och8_cnt = 0;`
559			`else och8_cnt = och8_cnt + 1;`
560			`och9_v = ovalid[0] & (och9_cnt == oint[1:0]);`
561			`if(och9_v) och9_cnt = 0;`
562			`else och9_cnt = och9_cnt + 1;`
563
564			`ich0_v = ivalid[9] & (ich0_cnt == iint[19:18]);`
565			`if(ich0_v) ich0_cnt = 0;`
566			`else ich0_cnt = ich0_cnt + 1;`
567			`ich1_v = ivalid[8] & (ich1_cnt == iint[17:16]);`
568			`if(ich1_v) ich1_cnt = 0;`
569			`else ich1_cnt = ich1_cnt + 1;`
570			`ich2_v = ivalid[7] & (ich2_cnt == iint[15:14]);`
571			`if(ich2_v) ich2_cnt = 0;`
572			`else ich2_cnt = ich2_cnt + 1;`
573			`ich3_v = ivalid[6] & (ich3_cnt == iint[13:12]);`
574			`if(ich3_v) ich3_cnt = 0;`
575			`else ich3_cnt = ich3_cnt + 1;`
576			`ich4_v = ivalid[5] & (ich4_cnt == iint[11:10]);`
577			`if(ich4_v) ich4_cnt = 0;`
578			`else ich4_cnt = ich4_cnt + 1;`
579			`ich5_v = ivalid[4] & (ich5_cnt == iint[9:8]);`
580			`if(ich5_v) ich5_cnt = 0;`
581			`else ich5_cnt = ich5_cnt + 1;`
582			`ich6_v = ivalid[3] & (ich6_cnt == iint[7:6]);`
583			`if(ich6_v) ich6_cnt = 0;`
584			`else ich6_cnt = ich6_cnt + 1;`
585			`ich7_v = ivalid[2] & (ich7_cnt == iint[5:4]);`
586			`if(ich7_v) ich7_cnt = 0;`
587			`else ich7_cnt = ich7_cnt + 1;`
588			`ich8_v = ivalid[1] & (ich8_cnt == iint[3:2]);`
589			`if(ich8_v) ich8_cnt = 0;`
590			`else ich8_cnt = ich8_cnt + 1;`
591			`ich9_v = ivalid[0] & (ich9_cnt == iint[1:0]);`
592			`if(ich9_v) ich9_cnt = 0;`
593			`else ich9_cnt = ich9_cnt + 1;`
594
595			`set_tag(1'b1, { 1'b0, // Slot 1`
596			`1'b0, // Slot 2`
597			`ich0_v, ich1_v, ich2_v, ich3_v, ich4_v,`
598			`ich5_v, ich6_v, ich7_v, ich8_v, ich9_v} );`
599
600			`set_req( { och0_v, och1_v, och2_v, och3_v, och4_v,`
601			`och5_v, och6_v, och7_v, och8_v, och9_v} );`
602
603			`end`
604			`while(sync) @(posedge clk);`
605			`end`
606			`end`
607			`endtask`
608
609			`////////////////////////////////////////////////////////////////////`
610			`//`
611			`// Modules`
612			`//`
613
614			`ac97_codec_sin u0(`
615			`.clk( clk ),`
616			`.rst( rst ),`
617			`.sync( sync ),`
618			`.slt0( out_slt0 ),`
619			`.slt1( out_slt1 ),`
620			`.slt2( out_slt2 ),`
621			`.slt3( out_slt3 ),`
622			`.slt4( out_slt4 ),`
623			`.slt5( out_slt5 ),`
624			`.slt6( out_slt6 ),`
625			`.slt7( out_slt7 ),`
626			`.slt8( out_slt8 ),`
627			`.slt9( out_slt9 ),`
628			`.slt10( out_slt10 ),`
629			`.slt11( out_slt11 ),`
630			`.slt12( out_slt12 ),`
631			`.sdata_in( sdata_in )`
632			`);`
633
634			`ac97_codec_sout u1(`
635			`.clk( clk ),`
636			`.rst( rst ),`
637			`.sync( sync ),`
638			`.slt0( in_slt0 ),`
639			`.slt1( in_slt1 ),`
640			`.slt2( in_slt2 ),`
641			`.slt3( in_slt3 ),`
642			`.slt4( in_slt4 ),`
643			`.slt5( in_slt5 ),`
644			`.slt6( in_slt6 ),`
645			`.slt7( in_slt7 ),`
646			`.slt8( in_slt8 ),`
647			`.slt9( in_slt9 ),`
648			`.slt10( in_slt10 ),`
649			`.slt11( in_slt11 ),`
650			`.slt12( in_slt12 ),`
651			`.sdata_out( sdata_out )`
652			`);`
653
654			`endmodule`
655
656