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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Top Level Test Bench                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: test_bench_top.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
//
//  $Date: 2002-02-13 08:22:32 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//                        
 
`include "ac97_defines.v"
 
module test;
 
reg             clk;
reg             rst;
wire    [31:0]   wb_data_i;
wire    [31:0]   wb_data_o;
wire    [31:0]   wb_addr_i;
wire    [3:0]    wb_sel_i;
wire            wb_we_i;
wire            wb_cyc_i;
wire            wb_stb_i;
wire            wb_ack_o;
wire            wb_err_o;
wire            int;
wire    [8:0]    dma_req;
reg     [8:0]    dma_ack;
reg             susp_req;
reg             resume_req;
wire            suspended;
reg             bit_clk;
wire            sync;
wire            sdata_out;
wire            sdata_in;
wire            ac97_reset_;
 
// Test Bench Variables
reg             verbose;
integer         error_cnt;
 
// DMA model
reg             wb_busy;
reg             oc0_dma_en;
reg             oc1_dma_en;
reg             oc2_dma_en;
reg             oc3_dma_en;
reg             oc4_dma_en;
reg             oc5_dma_en;
reg             ic0_dma_en;
reg             ic1_dma_en;
reg             ic2_dma_en;
reg     [31:0]   oc0_mem[0:256];
reg     [31:0]   oc1_mem[0:256];
reg     [31:0]   oc2_mem[0:256];
reg     [31:0]   oc3_mem[0:256];
reg     [31:0]   oc4_mem[0:256];
reg     [31:0]   oc5_mem[0:256];
reg     [31:0]   ic0_mem[0:256];
reg     [31:0]   ic1_mem[0:256];
reg     [31:0]   ic2_mem[0:256];
reg     [31:0]   reg_mem[0:256];
integer         oc0_ptr;
integer         oc1_ptr;
integer         oc2_ptr;
integer         oc3_ptr;
integer         oc4_ptr;
integer         oc5_ptr;
integer         ic0_ptr;
integer         ic1_ptr;
integer         ic2_ptr;
 
reg     [31:0]   ints_r;
reg             int_chk_en;
integer         int_cnt;
 
integer         n;
 
// Misc Variables
reg     [31:0]   data;
reg     [31:0]   data1;
reg     [31:0]   data2;
reg     [31:0]   tmp;
integer         size, frames, m;
 
/////////////////////////////////////////////////////////////////////
//
// Defines 
//
 
`define CSR             8'h00
`define OCC0            8'h04
`define OCC1            8'h08
`define ICC             8'h0c
`define CRAC            8'h10
`define INTM            8'h14
`define INTS            8'h18
 
`define OC0             8'h20
`define OC1             8'h24
`define OC2             8'h28
`define OC3             8'h2c
`define OC4             8'h30
`define OC5             8'h34
`define IC0             8'h38
`define IC1             8'h3c
`define IC2             8'h40
 
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
 
task do_rst;
 
begin
        wb_busy = 0;
        oc0_dma_en = 0;
        oc1_dma_en = 0;
        oc2_dma_en = 0;
        oc3_dma_en = 0;
        oc4_dma_en = 0;
        oc5_dma_en = 0;
        ic0_dma_en = 0;
        ic1_dma_en = 0;
        ic2_dma_en = 0;
 
        oc0_ptr = 0;
        oc1_ptr = 0;
        oc2_ptr = 0;
        oc3_ptr = 0;
        oc4_ptr = 0;
        oc5_ptr = 0;
        ic0_ptr = 0;
        ic1_ptr = 0;
        ic2_ptr = 0;
 
        rst = 0;
        repeat(48)      @(posedge clk);
        rst = 1;
        repeat(48)      @(posedge clk);
 
end
 
endtask
 
initial
   begin
        $display("\n\n");
        $display("*****************************************************");
        $display("* WISHBONE Memory Controller Simulation started ... *");
        $display("*****************************************************");
        $display("\n");
`ifdef WAVES
        $shm_open("waves");
        $shm_probe("AS",test,"AS");
        $display("INFO: Signal dump enabled ...\n\n");
`endif
        //wd_cnt = 0;
        int_chk_en = 1;
        int_cnt = 0;
        error_cnt = 0;
        clk = 1;
        bit_clk = 0;
        rst = 0;
        susp_req = 0;
        resume_req = 0;
        verbose = 1;
        dma_ack = 0;
 
        wb_busy = 0;
        oc0_dma_en = 0;
        oc1_dma_en = 0;
        oc2_dma_en = 0;
        oc3_dma_en = 0;
        oc4_dma_en = 0;
        oc5_dma_en = 0;
        ic0_dma_en = 0;
        ic1_dma_en = 0;
        ic2_dma_en = 0;
 
        oc0_ptr = 0;
        oc1_ptr = 0;
        oc2_ptr = 0;
        oc3_ptr = 0;
        oc4_ptr = 0;
        oc5_ptr = 0;
        ic0_ptr = 0;
        ic1_ptr = 0;
        ic2_ptr = 0;
 
        repeat(48)      @(posedge clk);
        rst = 1;
        repeat(48)      @(posedge clk);
 
        // HERE IS WHERE THE TEST CASES GO ...
 
if(0)    // Full Regression Run
   begin
$display(" ......................................................");
$display(" :                                                    :");
$display(" :    Regression Run ...                              :");
$display(" :....................................................:");
 
        basic1;
 
        do_rst;
 
        basic2;
 
        do_rst;
 
        vsr1;
 
   end
else
if(1)   // Debug Tests
   begin
$display(" ......................................................");
$display(" :                                                    :");
$display(" :    Test Debug Testing ...                          :");
$display(" :....................................................:");
 
        basic1;
 
        do_rst;
 
        basic2;
 
        do_rst;
 
        vsr1;
 
        repeat(100)     @(posedge clk);
        $finish;
   end
else
   begin
 
        //
        // TEST DEVELOPMENT AREA
        //
 
$display("\n\n");
$display("*****************************************************");
$display("*** XXX AC97 I/O Test ...                         ***");
$display("*****************************************************\n");
 
 
        wb_busy = 1;
        m0.wb_wr1(`INTM,4'hf, 32'h0000_0003);
        m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
        m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
        m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
        m0.wb_wr1(`OCC0,4'hf, 32'h7272_7272);
        m0.wb_wr1(`OCC1,4'hf, 32'h0000_7272);
 
        wb_busy = 0;
        oc0_dma_en = 1;
        oc1_dma_en = 1;
        oc2_dma_en = 1;
        oc3_dma_en = 1;
        oc4_dma_en = 1;
        oc5_dma_en = 1;
        ic0_dma_en = 1;
        ic1_dma_en = 1;
        ic2_dma_en = 1;
 
        for(n=0;n<256;n=n+1)
           begin
                oc0_mem[n] = $random;
                oc1_mem[n] = $random;
                oc2_mem[n] = $random;
                oc3_mem[n] = $random;
                oc4_mem[n] = $random;
                oc5_mem[n] = $random;
                ic0_mem[n] = $random;
                ic1_mem[n] = $random;
                ic2_mem[n] = $random;
           end
 
        u1.init(0);
        frames = 139;
 
fork
        u1.tx1( frames,                                 // Number of frames to process
                0,                                       // How many frames before codec is ready
                10'b1111_1111_11,                        // Output slots valid bits
                10'b1111_1111_11,                        // Input slots valid bits
                20'b00_00_00_00_00_00_00_00_00_00,       // Output Slots intervals
                20'b00_00_00_00_00_00_00_00_00_00        // Input Slots intervals
                );
 
        begin   // Do a register Write
                repeat(2)       @(posedge sync);
 
                for(n=0;n<75;n=n+1)
                   begin
                        @(negedge sync);
                        repeat(230)     @(posedge bit_clk);
 
                        repeat(n)       @(posedge bit_clk);
 
                        while(wb_busy)  @(posedge clk);
                        wb_busy = 1;
                        m0.wb_wr1(`CRAC,4'hf, {1'b1, 8'h0, n[6:0], 16'h1234 + n[7:0]} );
                        wb_busy = 0;
 
                        while(!int)     @(posedge clk);
 
                        while(wb_busy)  @(posedge clk);
                        wb_busy = 1;
                        m0.wb_rd1(`CRAC,4'hf, reg_mem[n] );
                        m0.wb_wr1(`CSR, 4'hf, 32'h0000_0001);
 
                        repeat(10)      @(posedge clk);
                        force bit_clk = 0;
                        repeat(80)      @(posedge clk);
 
                        m0.wb_wr1(`CSR, 4'hf, 32'h0000_0002);
 
                        repeat(300)     @(posedge clk);
 
                        release bit_clk;
 
                        wb_busy = 0;
 
                   end
        end
join
 
repeat(300)     @(posedge bit_clk);
 
        for(n=0;n<75;n=n+1)
           begin
 
                        tmp = u1.is2_mem[n];
                        data2 = {16'h0, tmp[19:4]};
                        tmp = reg_mem[n];
                        data1 = {16'h0, tmp[15:0]};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: Register Read Data %0d Mismatch Expected: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
 
           end
 
        size = frames - 4;
 
        for(n=0;n<size;n=n+1)
           begin
                data1 = u1.rs3_mem[n];
                data = oc0_mem[n[8:1]];
 
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
                else            data2 = {12'h0, data[31:16], 4'h0};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<size;n=n+1)
           begin
                data1 = u1.rs4_mem[n];
                data = oc1_mem[n[8:1]];
 
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
                else            data2 = {12'h0, data[31:16], 4'h0};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<size;n=n+1)
           begin
                data1 = u1.rs6_mem[n];
                data = oc2_mem[n[8:1]];
 
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
                else            data2 = {12'h0, data[31:16], 4'h0};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<size;n=n+1)
           begin
                data1 = u1.rs7_mem[n];
                data = oc3_mem[n[8:1]];
 
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
                else            data2 = {12'h0, data[31:16], 4'h0};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<size;n=n+1)
           begin
                data1 = u1.rs8_mem[n];
                data = oc4_mem[n[8:1]];
 
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
                else            data2 = {12'h0, data[31:16], 4'h0};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<size;n=n+1)
           begin
                data1 = u1.rs9_mem[n];
                data = oc5_mem[n[8:1]];
 
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
                else            data2 = {12'h0, data[31:16], 4'h0};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<size;n=n+1)
           begin
                data1 = u1.is3_mem[n];
                data = ic0_mem[n[8:1]];
 
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
                else            data2 = {12'h0, data[31:16], 4'h0};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<size;n=n+1)
           begin
                data1 = u1.is4_mem[n];
                data = ic1_mem[n[8:1]];
 
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
                else            data2 = {12'h0, data[31:16], 4'h0};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<size;n=n+1)
           begin
                data1 = u1.is6_mem[n];
                data = ic2_mem[n[8:1]];
 
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
                else            data2 = {12'h0, data[31:16], 4'h0};
 
                if(     (data1 !== data2) |
                        (^data1 === 1'hx) |
                        (^data2 === 1'hx)
                        )
                   begin
                        $display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
                        n, data2, data1);
                        error_cnt = error_cnt + 1;
                   end
           end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
 
repeat(6000)    @(posedge clk);
$finish;
 
   end
 
        repeat(100)     @(posedge clk);
        $finish;
   end
 
 
task wait_sync;
 
begin
 
while(!sync)    @(posedge bit_clk);
repeat(2)       @(posedge bit_clk);
end
endtask
 
/////////////////////////////////////////////////////////////////////
//
// Simple Interrupt Handler
//
 
always @(posedge clk)
if(int & int_chk_en)
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_rd1(`INTS,4'hf, ints_r);
        //$display("INFO: Got Interrupt (%0d). INTS: %h (%t)", int_cnt, ints_r, $time);
        wb_busy = 0;
        int_cnt = int_cnt + 1;
   end
 
/////////////////////////////////////////////////////////////////////
//
// Simple DMA Engine
//
 
always @(posedge clk)
if(oc0_dma_en & dma_req[0])
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_wr4(`OC0, 4'hf, 0, oc0_mem[oc0_ptr+0],
                                        oc0_mem[oc0_ptr+1],
                                        oc0_mem[oc0_ptr+2],
                                        oc0_mem[oc0_ptr+3]);
        oc0_ptr = oc0_ptr + 4;
        wb_busy = 0;
        dma_ack[0] = 1;
        @(posedge clk);
        #1 dma_ack[0] = 0;
   end
 
 
always @(posedge clk)
if(oc1_dma_en & dma_req[1])
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_wr4(`OC1, 4'hf, 0, oc1_mem[oc1_ptr+0],
                                        oc1_mem[oc1_ptr+1],
                                        oc1_mem[oc1_ptr+2],
                                        oc1_mem[oc1_ptr+3]);
        oc1_ptr = oc1_ptr + 4;
        wb_busy = 0;
        dma_ack[1] = 1;
        @(posedge clk);
        #1 dma_ack[1] = 0;
   end
 
always @(posedge clk)
if(oc2_dma_en & dma_req[2])
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_wr4(`OC2, 4'hf, 0, oc2_mem[oc2_ptr+0],
                                        oc2_mem[oc2_ptr+1],
                                        oc2_mem[oc2_ptr+2],
                                        oc2_mem[oc2_ptr+3]);
        oc2_ptr = oc2_ptr + 4;
        wb_busy = 0;
        dma_ack[2] = 1;
        @(posedge clk);
        #1 dma_ack[2] = 0;
   end
 
always @(posedge clk)
if(oc3_dma_en & dma_req[3])
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_wr4(`OC3, 4'hf, 0, oc3_mem[oc3_ptr+0],
                                        oc3_mem[oc3_ptr+1],
                                        oc3_mem[oc3_ptr+2],
                                        oc3_mem[oc3_ptr+3]);
        oc3_ptr = oc3_ptr + 4;
        wb_busy = 0;
        dma_ack[3] = 1;
        @(posedge clk);
        #1 dma_ack[3] = 0;
   end
 
always @(posedge clk)
if(oc4_dma_en & dma_req[4])
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_wr4(`OC4, 4'hf, 0, oc4_mem[oc4_ptr+0],
                                        oc4_mem[oc4_ptr+1],
                                        oc4_mem[oc4_ptr+2],
                                        oc4_mem[oc4_ptr+3]);
        oc4_ptr = oc4_ptr + 4;
        wb_busy = 0;
        dma_ack[4] = 1;
        @(posedge clk);
        #1 dma_ack[4] = 0;
   end
 
always @(posedge clk)
if(oc5_dma_en & dma_req[5])
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_wr4(`OC5, 4'hf, 0, oc5_mem[oc5_ptr+0],
                                        oc5_mem[oc5_ptr+1],
                                        oc5_mem[oc5_ptr+2],
                                        oc5_mem[oc5_ptr+3]);
        oc5_ptr = oc5_ptr + 4;
        wb_busy = 0;
        dma_ack[5] = 1;
        @(posedge clk);
        #1 dma_ack[5] = 0;
   end
 
always @(posedge clk)
if(ic0_dma_en & dma_req[6])
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_rd4(`IC0, 4'hf, 0, ic0_mem[ic0_ptr+0],
                                        ic0_mem[ic0_ptr+1],
                                        ic0_mem[ic0_ptr+2],
                                        ic0_mem[ic0_ptr+3]);
        ic0_ptr = ic0_ptr + 4;
        wb_busy = 0;
        dma_ack[6] = 1;
        @(posedge clk);
        #1 dma_ack[6] = 0;
   end
 
always @(posedge clk)
if(ic1_dma_en & dma_req[7])
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_rd4(`IC1, 4'hf, 0, ic1_mem[ic1_ptr+0],
                                        ic1_mem[ic1_ptr+1],
                                        ic1_mem[ic1_ptr+2],
                                        ic1_mem[ic1_ptr+3]);
        ic1_ptr = ic1_ptr + 4;
        wb_busy = 0;
        dma_ack[7] = 1;
        @(posedge clk);
        #1 dma_ack[7] = 0;
   end
 
always @(posedge clk)
if(ic2_dma_en & dma_req[8])
   begin
        while(wb_busy)  @(posedge clk);
        wb_busy = 1;
        m0.wb_rd4(`IC2, 4'hf, 0, ic2_mem[ic2_ptr+0],
                                        ic2_mem[ic2_ptr+1],
                                        ic2_mem[ic2_ptr+2],
                                        ic2_mem[ic2_ptr+3]);
        ic2_ptr = ic2_ptr + 4;
        wb_busy = 0;
        dma_ack[8] = 1;
        @(posedge clk);
        #1 dma_ack[8] = 0;
   end
 
 
 
 
/////////////////////////////////////////////////////////////////////
//
// Clock Generation
//
 
always #2.5     clk = ~clk;
 
always #40.69   bit_clk <= ~bit_clk;
 
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE AC 97 Controller IP Core
//
 
ac97_top        u0(
                .clk_i(         clk             ),
                .rst_i(         rst             ),
                .wb_data_i(     wb_data_i       ),
                .wb_data_o(     wb_data_o       ),
                .wb_addr_i(     wb_addr_i       ),
                .wb_sel_i(      wb_sel_i        ),
                .wb_we_i(       wb_we_i         ),
                .wb_cyc_i(      wb_cyc_i        ),
                .wb_stb_i(      wb_stb_i        ),
                .wb_ack_o(      wb_ack_o        ),
                .wb_err_o(      wb_err_o        ),
                .int_o(         int             ),
                .dma_req_o(     dma_req         ),
                .dma_ack_i(     dma_ack         ),
                .suspended_o(   suspended       ),
                .bit_clk_pad_i( bit_clk         ),
                .sync_pad_o(    sync            ),
                .sdata_pad_o(   sdata_out       ),
                .sdata_pad_i(   sdata_in        ),
                .ac97_reset_pad_o_(     ac97_reset_     )
                );
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE Master Model
//
 
wb_mast m0(     .clk(           clk             ),
                .rst(           rst             ),
                .adr(           wb_addr_i       ),
                .din(           wb_data_o       ),
                .dout(          wb_data_i       ),
                .cyc(           wb_cyc_i        ),
                .stb(           wb_stb_i        ),
                .sel(           wb_sel_i        ),
                .we(            wb_we_i         ),
                .ack(           wb_ack_o        ),
                .err(           wb_err_o        ),
                .rty(                           )
                );
 
/////////////////////////////////////////////////////////////////////
//
// AC 97 Codec Model
//
 
 
ac97_codec_top  u1(
                .clk(           bit_clk         ),
                .rst(           rst             ),
                .sync(          sync            ),
                .sdata_out(     sdata_in        ),
                .sdata_in(      sdata_out       )
                );
 
 
 
/////////////////////////////////////////////////////////////////////
//
// Tests and libraries
//
 
 
`include "tests.v"
 
endmodule
 
 

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[/] [ac97/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Top Level Test Bench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: test_bench_top.v,v 1.1 2002-02-13 08:22:32 rudi Exp $`
41			`//`
42			`// $Date: 2002-02-13 08:22:32 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`//`
52			`//`
53
54			`include "ac97_defines.v"
55
56			`module test;`
57
58			`reg clk;`
59			`reg rst;`
60			`wire [31:0] wb_data_i;`
61			`wire [31:0] wb_data_o;`
62			`wire [31:0] wb_addr_i;`
63			`wire [3:0] wb_sel_i;`
64			`wire wb_we_i;`
65			`wire wb_cyc_i;`
66			`wire wb_stb_i;`
67			`wire wb_ack_o;`
68			`wire wb_err_o;`
69			`wire int;`
70			`wire [8:0] dma_req;`
71			`reg [8:0] dma_ack;`
72			`reg susp_req;`
73			`reg resume_req;`
74			`wire suspended;`
75			`reg bit_clk;`
76			`wire sync;`
77			`wire sdata_out;`
78			`wire sdata_in;`
79			`wire ac97_reset_;`
80
81			`// Test Bench Variables`
82			`reg verbose;`
83			`integer error_cnt;`
84
85			`// DMA model`
86			`reg wb_busy;`
87			`reg oc0_dma_en;`
88			`reg oc1_dma_en;`
89			`reg oc2_dma_en;`
90			`reg oc3_dma_en;`
91			`reg oc4_dma_en;`
92			`reg oc5_dma_en;`
93			`reg ic0_dma_en;`
94			`reg ic1_dma_en;`
95			`reg ic2_dma_en;`
96			`reg [31:0] oc0_mem[0:256];`
97			`reg [31:0] oc1_mem[0:256];`
98			`reg [31:0] oc2_mem[0:256];`
99			`reg [31:0] oc3_mem[0:256];`
100			`reg [31:0] oc4_mem[0:256];`
101			`reg [31:0] oc5_mem[0:256];`
102			`reg [31:0] ic0_mem[0:256];`
103			`reg [31:0] ic1_mem[0:256];`
104			`reg [31:0] ic2_mem[0:256];`
105			`reg [31:0] reg_mem[0:256];`
106			`integer oc0_ptr;`
107			`integer oc1_ptr;`
108			`integer oc2_ptr;`
109			`integer oc3_ptr;`
110			`integer oc4_ptr;`
111			`integer oc5_ptr;`
112			`integer ic0_ptr;`
113			`integer ic1_ptr;`
114			`integer ic2_ptr;`
115
116			`reg [31:0] ints_r;`
117			`reg int_chk_en;`
118			`integer int_cnt;`
119
120			`integer n;`
121
122			`// Misc Variables`
123			`reg [31:0] data;`
124			`reg [31:0] data1;`
125			`reg [31:0] data2;`
126			`reg [31:0] tmp;`
127			`integer size, frames, m;`
128
129			`/////////////////////////////////////////////////////////////////////`
130			`//`
131			`// Defines`
132			`//`
133
134			`define CSR 8'h00
135			`define OCC0 8'h04
136			`define OCC1 8'h08
137			`define ICC 8'h0c
138			`define CRAC 8'h10
139			`define INTM 8'h14
140			`define INTS 8'h18
141
142			`define OC0 8'h20
143			`define OC1 8'h24
144			`define OC2 8'h28
145			`define OC3 8'h2c
146			`define OC4 8'h30
147			`define OC5 8'h34
148			`define IC0 8'h38
149			`define IC1 8'h3c
150			`define IC2 8'h40
151
152			`/////////////////////////////////////////////////////////////////////`
153			`//`
154			`// Simulation Initialization and Start up Section`
155			`//`
156
157			`task do_rst;`
158
159			`begin`
160			`wb_busy = 0;`
161			`oc0_dma_en = 0;`
162			`oc1_dma_en = 0;`
163			`oc2_dma_en = 0;`
164			`oc3_dma_en = 0;`
165			`oc4_dma_en = 0;`
166			`oc5_dma_en = 0;`
167			`ic0_dma_en = 0;`
168			`ic1_dma_en = 0;`
169			`ic2_dma_en = 0;`
170
171			`oc0_ptr = 0;`
172			`oc1_ptr = 0;`
173			`oc2_ptr = 0;`
174			`oc3_ptr = 0;`
175			`oc4_ptr = 0;`
176			`oc5_ptr = 0;`
177			`ic0_ptr = 0;`
178			`ic1_ptr = 0;`
179			`ic2_ptr = 0;`
180
181			`rst = 0;`
182			`repeat(48) @(posedge clk);`
183			`rst = 1;`
184			`repeat(48) @(posedge clk);`
185
186			`end`
187
188			`endtask`
189
190			`initial`
191			`begin`
192			`$display("\n\n");`
193			`$display("*****************************************************");`
194			`$display("* WISHBONE Memory Controller Simulation started ... *");`
195			`$display("*****************************************************");`
196			`$display("\n");`
197			`ifdef WAVES
198			`$shm_open("waves");`
199			`$shm_probe("AS",test,"AS");`
200			`$display("INFO: Signal dump enabled ...\n\n");`
201			`endif
202			`//wd_cnt = 0;`
203			`int_chk_en = 1;`
204			`int_cnt = 0;`
205			`error_cnt = 0;`
206			`clk = 1;`
207			`bit_clk = 0;`
208			`rst = 0;`
209			`susp_req = 0;`
210			`resume_req = 0;`
211			`verbose = 1;`
212			`dma_ack = 0;`
213
214			`wb_busy = 0;`
215			`oc0_dma_en = 0;`
216			`oc1_dma_en = 0;`
217			`oc2_dma_en = 0;`
218			`oc3_dma_en = 0;`
219			`oc4_dma_en = 0;`
220			`oc5_dma_en = 0;`
221			`ic0_dma_en = 0;`
222			`ic1_dma_en = 0;`
223			`ic2_dma_en = 0;`
224
225			`oc0_ptr = 0;`
226			`oc1_ptr = 0;`
227			`oc2_ptr = 0;`
228			`oc3_ptr = 0;`
229			`oc4_ptr = 0;`
230			`oc5_ptr = 0;`
231			`ic0_ptr = 0;`
232			`ic1_ptr = 0;`
233			`ic2_ptr = 0;`
234
235			`repeat(48) @(posedge clk);`
236			`rst = 1;`
237			`repeat(48) @(posedge clk);`
238
239			`// HERE IS WHERE THE TEST CASES GO ...`
240
241			`if(0) // Full Regression Run`
242			`begin`
243			`$display(" ......................................................");`
244			`$display(" : :");`
245			`$display(" : Regression Run ... :");`
246			`$display(" :....................................................:");`
247
248			`basic1;`
249
250			`do_rst;`
251
252			`basic2;`
253
254			`do_rst;`
255
256			`vsr1;`
257
258			`end`
259			`else`
260			`if(1) // Debug Tests`
261			`begin`
262			`$display(" ......................................................");`
263			`$display(" : :");`
264			`$display(" : Test Debug Testing ... :");`
265			`$display(" :....................................................:");`
266
267			`basic1;`
268
269			`do_rst;`
270
271			`basic2;`
272
273			`do_rst;`
274
275			`vsr1;`
276
277			`repeat(100) @(posedge clk);`
278			`$finish;`
279			`end`
280			`else`
281			`begin`
282
283			`//`
284			`// TEST DEVELOPMENT AREA`
285			`//`
286
287			`$display("\n\n");`
288			`$display("*****************************************************");`
289			`$display("* XXX AC97 I/O Test ... *");`
290			`$display("*****************************************************\n");`
291
292
293			`wb_busy = 1;`
294			m0.wb_wr1(`INTM,4'hf, 32'h0000_0003);
295			m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
296			m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
297			m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
298			m0.wb_wr1(`OCC0,4'hf, 32'h7272_7272);
299			m0.wb_wr1(`OCC1,4'hf, 32'h0000_7272);
300
301			`wb_busy = 0;`
302			`oc0_dma_en = 1;`
303			`oc1_dma_en = 1;`
304			`oc2_dma_en = 1;`
305			`oc3_dma_en = 1;`
306			`oc4_dma_en = 1;`
307			`oc5_dma_en = 1;`
308			`ic0_dma_en = 1;`
309			`ic1_dma_en = 1;`
310			`ic2_dma_en = 1;`
311
312			`for(n=0;n<256;n=n+1)`
313			`begin`
314			`oc0_mem[n] = $random;`
315			`oc1_mem[n] = $random;`
316			`oc2_mem[n] = $random;`
317			`oc3_mem[n] = $random;`
318			`oc4_mem[n] = $random;`
319			`oc5_mem[n] = $random;`
320			`ic0_mem[n] = $random;`
321			`ic1_mem[n] = $random;`
322			`ic2_mem[n] = $random;`
323			`end`
324
325			`u1.init(0);`
326			`frames = 139;`
327
328			`fork`
329			`u1.tx1( frames, // Number of frames to process`
330			`0, // How many frames before codec is ready`
331			`10'b1111_1111_11, // Output slots valid bits`
332			`10'b1111_1111_11, // Input slots valid bits`
333			`20'b00_00_00_00_00_00_00_00_00_00, // Output Slots intervals`
334			`20'b00_00_00_00_00_00_00_00_00_00 // Input Slots intervals`
335			`);`
336
337			`begin // Do a register Write`
338			`repeat(2) @(posedge sync);`
339
340			`for(n=0;n<75;n=n+1)`
341			`begin`
342			`@(negedge sync);`
343			`repeat(230) @(posedge bit_clk);`
344
345			`repeat(n) @(posedge bit_clk);`
346
347			`while(wb_busy) @(posedge clk);`
348			`wb_busy = 1;`
349			m0.wb_wr1(`CRAC,4'hf, {1'b1, 8'h0, n[6:0], 16'h1234 + n[7:0]} );
350			`wb_busy = 0;`
351
352			`while(!int) @(posedge clk);`
353
354			`while(wb_busy) @(posedge clk);`
355			`wb_busy = 1;`
356			m0.wb_rd1(`CRAC,4'hf, reg_mem[n] );
357			m0.wb_wr1(`CSR, 4'hf, 32'h0000_0001);
358
359			`repeat(10) @(posedge clk);`
360			`force bit_clk = 0;`
361			`repeat(80) @(posedge clk);`
362
363			m0.wb_wr1(`CSR, 4'hf, 32'h0000_0002);
364
365			`repeat(300) @(posedge clk);`
366
367			`release bit_clk;`
368
369			`wb_busy = 0;`
370
371			`end`
372			`end`
373			`join`
374
375			`repeat(300) @(posedge bit_clk);`
376
377			`for(n=0;n<75;n=n+1)`
378			`begin`
379
380			`tmp = u1.is2_mem[n];`
381			`data2 = {16'h0, tmp[19:4]};`
382			`tmp = reg_mem[n];`
383			`data1 = {16'h0, tmp[15:0]};`
384
385			`if( (data1 !== data2) \|`
386			`(^data1 === 1'hx) \|`
387			`(^data2 === 1'hx)`
388			`)`
389			`begin`
390			`$display("ERROR: Register Read Data %0d Mismatch Expected: %h Got: %h",`
391			`n, data2, data1);`
392			`error_cnt = error_cnt + 1;`
393			`end`
394
395			`end`
396
397			`size = frames - 4;`
398
399			`for(n=0;n<size;n=n+1)`
400			`begin`
401			`data1 = u1.rs3_mem[n];`
402			`data = oc0_mem[n[8:1]];`
403
404			`if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};`
405			`else data2 = {12'h0, data[31:16], 4'h0};`
406
407			`if( (data1 !== data2) \|`
408			`(^data1 === 1'hx) \|`
409			`(^data2 === 1'hx)`
410			`)`
411			`begin`
412			`$display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",`
413			`n, data2, data1);`
414			`error_cnt = error_cnt + 1;`
415			`end`
416			`end`
417
418			`for(n=0;n<size;n=n+1)`
419			`begin`
420			`data1 = u1.rs4_mem[n];`
421			`data = oc1_mem[n[8:1]];`
422
423			`if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};`
424			`else data2 = {12'h0, data[31:16], 4'h0};`
425
426			`if( (data1 !== data2) \|`
427			`(^data1 === 1'hx) \|`
428			`(^data2 === 1'hx)`
429			`)`
430			`begin`
431			`$display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",`
432			`n, data2, data1);`
433			`error_cnt = error_cnt + 1;`
434			`end`
435			`end`
436
437			`for(n=0;n<size;n=n+1)`
438			`begin`
439			`data1 = u1.rs6_mem[n];`
440			`data = oc2_mem[n[8:1]];`
441
442			`if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};`
443			`else data2 = {12'h0, data[31:16], 4'h0};`
444
445			`if( (data1 !== data2) \|`
446			`(^data1 === 1'hx) \|`
447			`(^data2 === 1'hx)`
448			`)`
449			`begin`
450			`$display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",`
451			`n, data2, data1);`
452			`error_cnt = error_cnt + 1;`
453			`end`
454			`end`
455
456			`for(n=0;n<size;n=n+1)`
457			`begin`
458			`data1 = u1.rs7_mem[n];`
459			`data = oc3_mem[n[8:1]];`
460
461			`if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};`
462			`else data2 = {12'h0, data[31:16], 4'h0};`
463
464			`if( (data1 !== data2) \|`
465			`(^data1 === 1'hx) \|`
466			`(^data2 === 1'hx)`
467			`)`
468			`begin`
469			`$display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",`
470			`n, data2, data1);`
471			`error_cnt = error_cnt + 1;`
472			`end`
473			`end`
474
475			`for(n=0;n<size;n=n+1)`
476			`begin`
477			`data1 = u1.rs8_mem[n];`
478			`data = oc4_mem[n[8:1]];`
479
480			`if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};`
481			`else data2 = {12'h0, data[31:16], 4'h0};`
482
483			`if( (data1 !== data2) \|`
484			`(^data1 === 1'hx) \|`
485			`(^data2 === 1'hx)`
486			`)`
487			`begin`
488			`$display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",`
489			`n, data2, data1);`
490			`error_cnt = error_cnt + 1;`
491			`end`
492			`end`
493
494			`for(n=0;n<size;n=n+1)`
495			`begin`
496			`data1 = u1.rs9_mem[n];`
497			`data = oc5_mem[n[8:1]];`
498
499			`if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};`
500			`else data2 = {12'h0, data[31:16], 4'h0};`
501
502			`if( (data1 !== data2) \|`
503			`(^data1 === 1'hx) \|`
504			`(^data2 === 1'hx)`
505			`)`
506			`begin`
507			`$display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",`
508			`n, data2, data1);`
509			`error_cnt = error_cnt + 1;`
510			`end`
511			`end`
512
513			`for(n=0;n<size;n=n+1)`
514			`begin`
515			`data1 = u1.is3_mem[n];`
516			`data = ic0_mem[n[8:1]];`
517
518			`if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};`
519			`else data2 = {12'h0, data[31:16], 4'h0};`
520
521			`if( (data1 !== data2) \|`
522			`(^data1 === 1'hx) \|`
523			`(^data2 === 1'hx)`
524			`)`
525			`begin`
526			`$display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",`
527			`n, data2, data1);`
528			`error_cnt = error_cnt + 1;`
529			`end`
530			`end`
531
532			`for(n=0;n<size;n=n+1)`
533			`begin`
534			`data1 = u1.is4_mem[n];`
535			`data = ic1_mem[n[8:1]];`
536
537			`if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};`
538			`else data2 = {12'h0, data[31:16], 4'h0};`
539
540			`if( (data1 !== data2) \|`
541			`(^data1 === 1'hx) \|`
542			`(^data2 === 1'hx)`
543			`)`
544			`begin`
545			`$display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",`
546			`n, data2, data1);`
547			`error_cnt = error_cnt + 1;`
548			`end`
549			`end`
550
551			`for(n=0;n<size;n=n+1)`
552			`begin`
553			`data1 = u1.is6_mem[n];`
554			`data = ic2_mem[n[8:1]];`
555
556			`if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};`
557			`else data2 = {12'h0, data[31:16], 4'h0};`
558
559			`if( (data1 !== data2) \|`
560			`(^data1 === 1'hx) \|`
561			`(^data2 === 1'hx)`
562			`)`
563			`begin`
564			`$display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",`
565			`n, data2, data1);`
566			`error_cnt = error_cnt + 1;`
567			`end`
568			`end`
569
570			`show_errors;`
571			`$display("*****************************************************");`
572			`$display("* Test DONE ... *");`
573			`$display("*****************************************************\n\n");`
574
575
576			`repeat(6000) @(posedge clk);`
577			`$finish;`
578
579			`end`
580
581			`repeat(100) @(posedge clk);`
582			`$finish;`
583			`end`
584
585
586			`task wait_sync;`
587
588			`begin`
589
590			`while(!sync) @(posedge bit_clk);`
591			`repeat(2) @(posedge bit_clk);`
592			`end`
593			`endtask`
594
595			`/////////////////////////////////////////////////////////////////////`
596			`//`
597			`// Simple Interrupt Handler`
598			`//`
599
600			`always @(posedge clk)`
601			`if(int & int_chk_en)`
602			`begin`
603			`while(wb_busy) @(posedge clk);`
604			`wb_busy = 1;`
605			m0.wb_rd1(`INTS,4'hf, ints_r);
606			`//$display("INFO: Got Interrupt (%0d). INTS: %h (%t)", int_cnt, ints_r, $time);`
607			`wb_busy = 0;`
608			`int_cnt = int_cnt + 1;`
609			`end`
610
611			`/////////////////////////////////////////////////////////////////////`
612			`//`
613			`// Simple DMA Engine`
614			`//`
615
616			`always @(posedge clk)`
617			`if(oc0_dma_en & dma_req[0])`
618			`begin`
619			`while(wb_busy) @(posedge clk);`
620			`wb_busy = 1;`
621			m0.wb_wr4(`OC0, 4'hf, 0, oc0_mem[oc0_ptr+0],
622			`oc0_mem[oc0_ptr+1],`
623			`oc0_mem[oc0_ptr+2],`
624			`oc0_mem[oc0_ptr+3]);`
625			`oc0_ptr = oc0_ptr + 4;`
626			`wb_busy = 0;`
627			`dma_ack[0] = 1;`
628			`@(posedge clk);`
629			`#1 dma_ack[0] = 0;`
630			`end`
631
632
633			`always @(posedge clk)`
634			`if(oc1_dma_en & dma_req[1])`
635			`begin`
636			`while(wb_busy) @(posedge clk);`
637			`wb_busy = 1;`
638			m0.wb_wr4(`OC1, 4'hf, 0, oc1_mem[oc1_ptr+0],
639			`oc1_mem[oc1_ptr+1],`
640			`oc1_mem[oc1_ptr+2],`
641			`oc1_mem[oc1_ptr+3]);`
642			`oc1_ptr = oc1_ptr + 4;`
643			`wb_busy = 0;`
644			`dma_ack[1] = 1;`
645			`@(posedge clk);`
646			`#1 dma_ack[1] = 0;`
647			`end`
648
649			`always @(posedge clk)`
650			`if(oc2_dma_en & dma_req[2])`
651			`begin`
652			`while(wb_busy) @(posedge clk);`
653			`wb_busy = 1;`
654			m0.wb_wr4(`OC2, 4'hf, 0, oc2_mem[oc2_ptr+0],
655			`oc2_mem[oc2_ptr+1],`
656			`oc2_mem[oc2_ptr+2],`
657			`oc2_mem[oc2_ptr+3]);`
658			`oc2_ptr = oc2_ptr + 4;`
659			`wb_busy = 0;`
660			`dma_ack[2] = 1;`
661			`@(posedge clk);`
662			`#1 dma_ack[2] = 0;`
663			`end`
664
665			`always @(posedge clk)`
666			`if(oc3_dma_en & dma_req[3])`
667			`begin`
668			`while(wb_busy) @(posedge clk);`
669			`wb_busy = 1;`
670			m0.wb_wr4(`OC3, 4'hf, 0, oc3_mem[oc3_ptr+0],
671			`oc3_mem[oc3_ptr+1],`
672			`oc3_mem[oc3_ptr+2],`
673			`oc3_mem[oc3_ptr+3]);`
674			`oc3_ptr = oc3_ptr + 4;`
675			`wb_busy = 0;`
676			`dma_ack[3] = 1;`
677			`@(posedge clk);`
678			`#1 dma_ack[3] = 0;`
679			`end`
680
681			`always @(posedge clk)`
682			`if(oc4_dma_en & dma_req[4])`
683			`begin`
684			`while(wb_busy) @(posedge clk);`
685			`wb_busy = 1;`
686			m0.wb_wr4(`OC4, 4'hf, 0, oc4_mem[oc4_ptr+0],
687			`oc4_mem[oc4_ptr+1],`
688			`oc4_mem[oc4_ptr+2],`
689			`oc4_mem[oc4_ptr+3]);`
690			`oc4_ptr = oc4_ptr + 4;`
691			`wb_busy = 0;`
692			`dma_ack[4] = 1;`
693			`@(posedge clk);`
694			`#1 dma_ack[4] = 0;`
695			`end`
696
697			`always @(posedge clk)`
698			`if(oc5_dma_en & dma_req[5])`
699			`begin`
700			`while(wb_busy) @(posedge clk);`
701			`wb_busy = 1;`
702			m0.wb_wr4(`OC5, 4'hf, 0, oc5_mem[oc5_ptr+0],
703			`oc5_mem[oc5_ptr+1],`
704			`oc5_mem[oc5_ptr+2],`
705			`oc5_mem[oc5_ptr+3]);`
706			`oc5_ptr = oc5_ptr + 4;`
707			`wb_busy = 0;`
708			`dma_ack[5] = 1;`
709			`@(posedge clk);`
710			`#1 dma_ack[5] = 0;`
711			`end`
712
713			`always @(posedge clk)`
714			`if(ic0_dma_en & dma_req[6])`
715			`begin`
716			`while(wb_busy) @(posedge clk);`
717			`wb_busy = 1;`
718			m0.wb_rd4(`IC0, 4'hf, 0, ic0_mem[ic0_ptr+0],
719			`ic0_mem[ic0_ptr+1],`
720			`ic0_mem[ic0_ptr+2],`
721			`ic0_mem[ic0_ptr+3]);`
722			`ic0_ptr = ic0_ptr + 4;`
723			`wb_busy = 0;`
724			`dma_ack[6] = 1;`
725			`@(posedge clk);`
726			`#1 dma_ack[6] = 0;`
727			`end`
728
729			`always @(posedge clk)`
730			`if(ic1_dma_en & dma_req[7])`
731			`begin`
732			`while(wb_busy) @(posedge clk);`
733			`wb_busy = 1;`
734			m0.wb_rd4(`IC1, 4'hf, 0, ic1_mem[ic1_ptr+0],
735			`ic1_mem[ic1_ptr+1],`
736			`ic1_mem[ic1_ptr+2],`
737			`ic1_mem[ic1_ptr+3]);`
738			`ic1_ptr = ic1_ptr + 4;`
739			`wb_busy = 0;`
740			`dma_ack[7] = 1;`
741			`@(posedge clk);`
742			`#1 dma_ack[7] = 0;`
743			`end`
744
745			`always @(posedge clk)`
746			`if(ic2_dma_en & dma_req[8])`
747			`begin`
748			`while(wb_busy) @(posedge clk);`
749			`wb_busy = 1;`
750			m0.wb_rd4(`IC2, 4'hf, 0, ic2_mem[ic2_ptr+0],
751			`ic2_mem[ic2_ptr+1],`
752			`ic2_mem[ic2_ptr+2],`
753			`ic2_mem[ic2_ptr+3]);`
754			`ic2_ptr = ic2_ptr + 4;`
755			`wb_busy = 0;`
756			`dma_ack[8] = 1;`
757			`@(posedge clk);`
758			`#1 dma_ack[8] = 0;`
759			`end`
760
761
762
763
764			`/////////////////////////////////////////////////////////////////////`
765			`//`
766			`// Clock Generation`
767			`//`
768
769			`always #2.5 clk = ~clk;`
770
771			`always #40.69 bit_clk <= ~bit_clk;`
772
773
774			`/////////////////////////////////////////////////////////////////////`
775			`//`
776			`// WISHBONE AC 97 Controller IP Core`
777			`//`
778
779			`ac97_top u0(`
780			`.clk_i( clk ),`
781			`.rst_i( rst ),`
782			`.wb_data_i( wb_data_i ),`
783			`.wb_data_o( wb_data_o ),`
784			`.wb_addr_i( wb_addr_i ),`
785			`.wb_sel_i( wb_sel_i ),`
786			`.wb_we_i( wb_we_i ),`
787			`.wb_cyc_i( wb_cyc_i ),`
788			`.wb_stb_i( wb_stb_i ),`
789			`.wb_ack_o( wb_ack_o ),`
790			`.wb_err_o( wb_err_o ),`
791			`.int_o( int ),`
792			`.dma_req_o( dma_req ),`
793			`.dma_ack_i( dma_ack ),`
794			`.suspended_o( suspended ),`
795			`.bit_clk_pad_i( bit_clk ),`
796			`.sync_pad_o( sync ),`
797			`.sdata_pad_o( sdata_out ),`
798			`.sdata_pad_i( sdata_in ),`
799			`.ac97_reset_pad_o_( ac97_reset_ )`
800			`);`
801
802			`/////////////////////////////////////////////////////////////////////`
803			`//`
804			`// WISHBONE Master Model`
805			`//`
806
807			`wb_mast m0( .clk( clk ),`
808			`.rst( rst ),`
809			`.adr( wb_addr_i ),`
810			`.din( wb_data_o ),`
811			`.dout( wb_data_i ),`
812			`.cyc( wb_cyc_i ),`
813			`.stb( wb_stb_i ),`
814			`.sel( wb_sel_i ),`
815			`.we( wb_we_i ),`
816			`.ack( wb_ack_o ),`
817			`.err( wb_err_o ),`
818			`.rty( )`
819			`);`
820
821			`/////////////////////////////////////////////////////////////////////`
822			`//`
823			`// AC 97 Codec Model`
824			`//`
825
826
827			`ac97_codec_top u1(`
828			`.clk( bit_clk ),`
829			`.rst( rst ),`
830			`.sync( sync ),`
831			`.sdata_out( sdata_in ),`
832			`.sdata_in( sdata_out )`
833			`);`
834
835
836
837			`/////////////////////////////////////////////////////////////////////`
838			`//`
839			`// Tests and libraries`
840			`//`
841
842
843			`include "tests.v"
844
845			`endmodule`
846
847