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1 7 rudi
/////////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  Tests                                                      ////
4
////                                                             ////
5
////                                                             ////
6
////  Author: Rudolf Usselmann                                   ////
7
////          rudi@asics.ws                                      ////
8
////                                                             ////
9
////                                                             ////
10
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
11
////                                                             ////
12
/////////////////////////////////////////////////////////////////////
13
////                                                             ////
14 15 rudi
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
15
////                         www.asics.ws                        ////
16
////                         rudi@asics.ws                       ////
17 7 rudi
////                                                             ////
18
//// This source file may be used and distributed without        ////
19
//// restriction provided that this copyright statement is not   ////
20
//// removed from the file and that any derivative work contains ////
21
//// the original copyright notice and the associated disclaimer.////
22
////                                                             ////
23
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
24
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
25
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
26
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
27
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
28
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
29
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
30
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
31
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
32
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
33
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
34
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
35
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
36
////                                                             ////
37
/////////////////////////////////////////////////////////////////////
38
 
39
//  CVS Log
40
//
41 15 rudi
//  $Id: tests.v,v 1.5 2002-09-19 06:36:19 rudi Exp $
42 7 rudi
//
43 15 rudi
//  $Date: 2002-09-19 06:36:19 $
44
//  $Revision: 1.5 $
45 7 rudi
//  $Author: rudi $
46
//  $Locker:  $
47
//  $State: Exp $
48
//
49
// Change History:
50
//               $Log: not supported by cvs2svn $
51 15 rudi
//               Revision 1.4  2002/03/11 03:21:12  rudi
52
//
53
//               - Added defines to select fifo depth between 4, 8 and 16 entries.
54
//
55 12 rudi
//               Revision 1.3  2002/03/05 04:54:08  rudi
56
//
57
//               - fixed spelling
58
//
59 11 rudi
//               Revision 1.2  2002/03/05 04:44:04  rudi
60
//
61
//               - Fixed the order of the thrash hold bits to match the spec.
62
//               - Many minor synthesis cleanup items ...
63
//
64 10 rudi
//               Revision 1.1  2002/02/13 08:22:32  rudi
65 7 rudi
//
66 10 rudi
//               Added test bench for public release
67 7 rudi
//
68 10 rudi
//
69
//
70 7 rudi
//                        
71
 
72
 
73
task show_errors;
74
 
75
begin
76
 
77
$display("\n");
78
$display("     +--------------------+");
79
$display("     |  Total ERRORS: %0d   |", error_cnt);
80
$display("     +--------------------+");
81
 
82
end
83
endtask
84
 
85
 
86
task basic1;
87
 
88
reg     [31:0]   data;
89
reg     [31:0]   data1;
90
reg     [31:0]   data2;
91
integer         size, frames, m;
92
 
93
begin
94
$display("\n\n");
95
$display("*****************************************************");
96
$display("*** Basic AC97 I/O Test & Reg Wr ...              ***");
97
$display("*****************************************************\n");
98
 
99
 
100
        wb_busy = 1;
101
        m0.wb_wr1(`INTM,4'hf, 32'h0000_0003);
102
        m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
103
        m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
104
        m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
105
 
106
        wb_busy = 0;
107
        oc0_dma_en = 1;
108
        oc1_dma_en = 1;
109
        oc2_dma_en = 1;
110
        oc3_dma_en = 1;
111
        oc4_dma_en = 1;
112
        oc5_dma_en = 1;
113
        ic0_dma_en = 1;
114
        ic1_dma_en = 1;
115
        ic2_dma_en = 1;
116
 
117
        for(n=0;n<256;n=n+1)
118
           begin
119
                oc0_mem[n] = $random;
120
                oc1_mem[n] = $random;
121
                oc2_mem[n] = $random;
122
                oc3_mem[n] = $random;
123
                oc4_mem[n] = $random;
124
                oc5_mem[n] = $random;
125
                ic0_mem[n] = $random;
126
                ic1_mem[n] = $random;
127
                ic2_mem[n] = $random;
128
           end
129
 
130
        u1.init(0);
131
        frames = 139;
132
 
133
fork
134
        u1.tx1( frames,                                 // Number of frames to process
135
                0,                                       // How many frames before codec is ready
136
                10'b1111_1111_11,                        // Output slots valid bits
137
                10'b1111_1111_11,                        // Input slots valid bits
138
                20'b00_00_00_00_00_00_00_00_00_00,       // Output Slots intervals
139
                20'b00_00_00_00_00_00_00_00_00_00        // Input Slots intervals
140
                );
141
 
142
        begin   // Do a register Write
143
                repeat(2)       @(posedge sync);
144
 
145
                for(n=0;n<75;n=n+1)
146
                   begin
147
                        @(negedge sync);
148 10 rudi
                        //repeat(230)   @(posedge bit_clk);
149
                        repeat(130)     @(posedge bit_clk);
150 7 rudi
 
151
                        repeat(n)       @(posedge bit_clk);
152
 
153
                        while(wb_busy)  @(posedge clk);
154
                        wb_busy = 1;
155
                        m0.wb_wr1(`CRAC,4'hf, {9'h0, n[6:0], 16'h1234 + n[7:0]} );
156
                        wb_busy = 0;
157
 
158
                        while(!int)     @(posedge clk);
159
                   end
160
        end
161
join
162
 
163
repeat(300)     @(posedge bit_clk);
164
 
165
        for(n=0;n<75;n=n+1)
166
           begin
167
                        data2 = {9'h0, n[6:0], 16'h1234 + n[7:0]};
168
                        tmp = u1.rs2_mem[n];
169
                        data1[15:0] = tmp[19:4];
170
 
171
                        tmp = u1.rs1_mem[n];
172
                        data1[31:16] = {9'h0, tmp[18:12]};
173
 
174
                if(     (data1 !== data2) |
175
                        (^data1 === 1'hx) |
176
                        (^data2 === 1'hx)
177
                        )
178
                   begin
179
                        $display("ERROR: Register Write Data %0d Mismatch Sent: %h Got: %h",
180
                        n, data2, data1);
181
                        error_cnt = error_cnt + 1;
182
                   end
183
 
184
           end
185
 
186 12 rudi
        size = frames - 12;
187 7 rudi
 
188
        for(n=0;n<size;n=n+1)
189
           begin
190
                data1 = u1.rs3_mem[n];
191
                data = oc0_mem[n[8:1]];
192
 
193
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
194
                else            data2 = {12'h0, data[31:16], 4'h0};
195
 
196
                if(     (data1 !== data2) |
197
                        (^data1 === 1'hx) |
198
                        (^data2 === 1'hx)
199
                        )
200
                   begin
201
                        $display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
202
                        n, data2, data1);
203
                        error_cnt = error_cnt + 1;
204
                   end
205
           end
206
 
207
        for(n=0;n<size;n=n+1)
208
           begin
209
                data1 = u1.rs4_mem[n];
210
                data = oc1_mem[n[8:1]];
211
 
212
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
213
                else            data2 = {12'h0, data[31:16], 4'h0};
214
 
215
                if(     (data1 !== data2) |
216
                        (^data1 === 1'hx) |
217
                        (^data2 === 1'hx)
218
                        )
219
                   begin
220
                        $display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
221
                        n, data2, data1);
222
                        error_cnt = error_cnt + 1;
223
                   end
224
           end
225
 
226
        for(n=0;n<size;n=n+1)
227
           begin
228
                data1 = u1.rs6_mem[n];
229
                data = oc2_mem[n[8:1]];
230
 
231
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
232
                else            data2 = {12'h0, data[31:16], 4'h0};
233
 
234
                if(     (data1 !== data2) |
235
                        (^data1 === 1'hx) |
236
                        (^data2 === 1'hx)
237
                        )
238
                   begin
239
                        $display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
240
                        n, data2, data1);
241
                        error_cnt = error_cnt + 1;
242
                   end
243
           end
244
 
245
        for(n=0;n<size;n=n+1)
246
           begin
247
                data1 = u1.rs7_mem[n];
248
                data = oc3_mem[n[8:1]];
249
 
250
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
251
                else            data2 = {12'h0, data[31:16], 4'h0};
252
 
253
                if(     (data1 !== data2) |
254
                        (^data1 === 1'hx) |
255
                        (^data2 === 1'hx)
256
                        )
257
                   begin
258
                        $display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
259
                        n, data2, data1);
260
                        error_cnt = error_cnt + 1;
261
                   end
262
           end
263
 
264
        for(n=0;n<size;n=n+1)
265
           begin
266
                data1 = u1.rs8_mem[n];
267
                data = oc4_mem[n[8:1]];
268
 
269
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
270
                else            data2 = {12'h0, data[31:16], 4'h0};
271
 
272
                if(     (data1 !== data2) |
273
                        (^data1 === 1'hx) |
274
                        (^data2 === 1'hx)
275
                        )
276
                   begin
277
                        $display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
278
                        n, data2, data1);
279
                        error_cnt = error_cnt + 1;
280
                   end
281
           end
282
 
283
        for(n=0;n<size;n=n+1)
284
           begin
285
                data1 = u1.rs9_mem[n];
286
                data = oc5_mem[n[8:1]];
287
 
288
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
289
                else            data2 = {12'h0, data[31:16], 4'h0};
290
 
291
                if(     (data1 !== data2) |
292
                        (^data1 === 1'hx) |
293
                        (^data2 === 1'hx)
294
                        )
295
                   begin
296
                        $display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
297
                        n, data2, data1);
298
                        error_cnt = error_cnt + 1;
299
                   end
300
           end
301
 
302
        for(n=0;n<size;n=n+1)
303
           begin
304
                data1 = u1.is3_mem[n];
305
                data = ic0_mem[n[8:1]];
306
 
307
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
308
                else            data2 = {12'h0, data[31:16], 4'h0};
309
 
310
                if(     (data1 !== data2) |
311
                        (^data1 === 1'hx) |
312
                        (^data2 === 1'hx)
313
                        )
314
                   begin
315
                        $display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
316
                        n, data2, data1);
317
                        error_cnt = error_cnt + 1;
318
                   end
319
           end
320
 
321
        for(n=0;n<size;n=n+1)
322
           begin
323
                data1 = u1.is4_mem[n];
324
                data = ic1_mem[n[8:1]];
325
 
326
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
327
                else            data2 = {12'h0, data[31:16], 4'h0};
328
 
329
                if(     (data1 !== data2) |
330
                        (^data1 === 1'hx) |
331
                        (^data2 === 1'hx)
332
                        )
333
                   begin
334
                        $display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
335
                        n, data2, data1);
336
                        error_cnt = error_cnt + 1;
337
                   end
338
           end
339
 
340
        for(n=0;n<size;n=n+1)
341
           begin
342
                data1 = u1.is6_mem[n];
343
                data = ic2_mem[n[8:1]];
344
 
345
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
346
                else            data2 = {12'h0, data[31:16], 4'h0};
347
 
348
                if(     (data1 !== data2) |
349
                        (^data1 === 1'hx) |
350
                        (^data2 === 1'hx)
351
                        )
352
                   begin
353
                        $display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
354
                        n, data2, data1);
355
                        error_cnt = error_cnt + 1;
356
                   end
357
           end
358
 
359
repeat(10)      @(posedge clk);
360
 
361
show_errors;
362
$display("*****************************************************");
363
$display("*** Test DONE ...                                 ***");
364
$display("*****************************************************\n\n");
365
 
366
end
367
endtask
368
 
369
 
370
 
371
task basic2;
372
 
373
reg     [31:0]   data;
374
reg     [31:0]   data1;
375
reg     [31:0]   data2;
376
integer         size, frames, m;
377
 
378
begin
379
$display("\n\n");
380
$display("*****************************************************");
381
$display("*** Basic AC97 I/O Test & Reg Rd ...              ***");
382
$display("*****************************************************\n");
383
 
384
        wb_busy = 1;
385
        m0.wb_wr1(`INTM,4'hf, 32'h0000_0003);
386
        m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
387
        m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
388
        m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
389
 
390
        wb_busy = 0;
391
        oc0_dma_en = 1;
392
        oc1_dma_en = 1;
393
        oc2_dma_en = 1;
394
        oc3_dma_en = 1;
395
        oc4_dma_en = 1;
396
        oc5_dma_en = 1;
397
        ic0_dma_en = 1;
398
        ic1_dma_en = 1;
399
        ic2_dma_en = 1;
400
 
401
        for(n=0;n<256;n=n+1)
402
           begin
403
                oc0_mem[n] = $random;
404
                oc1_mem[n] = $random;
405
                oc2_mem[n] = $random;
406
                oc3_mem[n] = $random;
407
                oc4_mem[n] = $random;
408
                oc5_mem[n] = $random;
409
                ic0_mem[n] = $random;
410
                ic1_mem[n] = $random;
411
                ic2_mem[n] = $random;
412
           end
413
 
414
        u1.init(0);
415
        frames = 139;
416
 
417
fork
418
        u1.tx1( frames,                                 // Number of frames to process
419
                0,                                       // How many frames before codec is ready
420
                10'b1111_1111_11,                        // Output slots valid bits
421
                10'b1111_1111_11,                        // Input slots valid bits
422
                20'b00_00_00_00_00_00_00_00_00_00,       // Output Slots intervals
423
                20'b00_00_00_00_00_00_00_00_00_00        // Input Slots intervals
424
                );
425
 
426
        begin   // Do a register Write
427
                repeat(2)       @(posedge sync);
428
 
429
                for(n=0;n<75;n=n+1)
430
                   begin
431
                        @(negedge sync);
432 10 rudi
                        //repeat(230)   @(posedge bit_clk);
433
                        repeat(130)     @(posedge bit_clk);
434 7 rudi
 
435
                        repeat(n)       @(posedge bit_clk);
436
 
437
                        while(wb_busy)  @(posedge clk);
438
                        wb_busy = 1;
439
                        m0.wb_wr1(`CRAC,4'hf, {1'b1, 8'h0, n[6:0], 16'h1234 + n[7:0]} );
440
                        wb_busy = 0;
441
 
442
                        while(!int)     @(posedge clk);
443
 
444
                        while(wb_busy)  @(posedge clk);
445
                        wb_busy = 1;
446
                        m0.wb_rd1(`CRAC,4'hf, reg_mem[n] );
447
                        wb_busy = 0;
448
 
449
                   end
450
        end
451
join
452
 
453
repeat(300)     @(posedge bit_clk);
454
 
455
        for(n=0;n<75;n=n+1)
456
           begin
457
 
458
                        tmp = u1.is2_mem[n];
459
                        data2 = {16'h0, tmp[19:4]};
460
                        tmp = reg_mem[n];
461
                        data1 = {16'h0, tmp[15:0]};
462
 
463
                if(     (data1 !== data2) |
464
                        (^data1 === 1'hx) |
465
                        (^data2 === 1'hx)
466
                        )
467
                   begin
468
                        $display("ERROR: Register Read Data %0d Mismatch Expected: %h Got: %h",
469
                        n, data2, data1);
470
                        error_cnt = error_cnt + 1;
471
                   end
472
 
473
           end
474
 
475
        size = frames - 4;
476
 
477
        for(n=0;n<size;n=n+1)
478
           begin
479
                data1 = u1.rs3_mem[n];
480
                data = oc0_mem[n[8:1]];
481
 
482
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
483
                else            data2 = {12'h0, data[31:16], 4'h0};
484
 
485
                if(     (data1 !== data2) |
486
                        (^data1 === 1'hx) |
487
                        (^data2 === 1'hx)
488
                        )
489
                   begin
490
                        $display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
491
                        n, data2, data1);
492
                        error_cnt = error_cnt + 1;
493
                   end
494
           end
495
 
496
        for(n=0;n<size;n=n+1)
497
           begin
498
                data1 = u1.rs4_mem[n];
499
                data = oc1_mem[n[8:1]];
500
 
501
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
502
                else            data2 = {12'h0, data[31:16], 4'h0};
503
 
504
                if(     (data1 !== data2) |
505
                        (^data1 === 1'hx) |
506
                        (^data2 === 1'hx)
507
                        )
508
                   begin
509
                        $display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
510
                        n, data2, data1);
511
                        error_cnt = error_cnt + 1;
512
                   end
513
           end
514
 
515
        for(n=0;n<size;n=n+1)
516
           begin
517
                data1 = u1.rs6_mem[n];
518
                data = oc2_mem[n[8:1]];
519
 
520
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
521
                else            data2 = {12'h0, data[31:16], 4'h0};
522
 
523
                if(     (data1 !== data2) |
524
                        (^data1 === 1'hx) |
525
                        (^data2 === 1'hx)
526
                        )
527
                   begin
528
                        $display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
529
                        n, data2, data1);
530
                        error_cnt = error_cnt + 1;
531
                   end
532
           end
533
 
534
        for(n=0;n<size;n=n+1)
535
           begin
536
                data1 = u1.rs7_mem[n];
537
                data = oc3_mem[n[8:1]];
538
 
539
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
540
                else            data2 = {12'h0, data[31:16], 4'h0};
541
 
542
                if(     (data1 !== data2) |
543
                        (^data1 === 1'hx) |
544
                        (^data2 === 1'hx)
545
                        )
546
                   begin
547
                        $display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
548
                        n, data2, data1);
549
                        error_cnt = error_cnt + 1;
550
                   end
551
           end
552
 
553
        for(n=0;n<size;n=n+1)
554
           begin
555
                data1 = u1.rs8_mem[n];
556
                data = oc4_mem[n[8:1]];
557
 
558
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
559
                else            data2 = {12'h0, data[31:16], 4'h0};
560
 
561
                if(     (data1 !== data2) |
562
                        (^data1 === 1'hx) |
563
                        (^data2 === 1'hx)
564
                        )
565
                   begin
566
                        $display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
567
                        n, data2, data1);
568
                        error_cnt = error_cnt + 1;
569
                   end
570
           end
571
 
572
        for(n=0;n<size;n=n+1)
573
           begin
574
                data1 = u1.rs9_mem[n];
575
                data = oc5_mem[n[8:1]];
576
 
577
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
578
                else            data2 = {12'h0, data[31:16], 4'h0};
579
 
580
                if(     (data1 !== data2) |
581
                        (^data1 === 1'hx) |
582
                        (^data2 === 1'hx)
583
                        )
584
                   begin
585
                        $display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
586
                        n, data2, data1);
587
                        error_cnt = error_cnt + 1;
588
                   end
589
           end
590
 
591
        for(n=0;n<size;n=n+1)
592
           begin
593
                data1 = u1.is3_mem[n];
594
                data = ic0_mem[n[8:1]];
595
 
596
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
597
                else            data2 = {12'h0, data[31:16], 4'h0};
598
 
599
                if(     (data1 !== data2) |
600
                        (^data1 === 1'hx) |
601
                        (^data2 === 1'hx)
602
                        )
603
                   begin
604
                        $display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
605
                        n, data2, data1);
606
                        error_cnt = error_cnt + 1;
607
                   end
608
           end
609
 
610
        for(n=0;n<size;n=n+1)
611
           begin
612
                data1 = u1.is4_mem[n];
613
                data = ic1_mem[n[8:1]];
614
 
615
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
616
                else            data2 = {12'h0, data[31:16], 4'h0};
617
 
618
                if(     (data1 !== data2) |
619
                        (^data1 === 1'hx) |
620
                        (^data2 === 1'hx)
621
                        )
622
                   begin
623
                        $display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
624
                        n, data2, data1);
625
                        error_cnt = error_cnt + 1;
626
                   end
627
           end
628
 
629
        for(n=0;n<size;n=n+1)
630
           begin
631
                data1 = u1.is6_mem[n];
632
                data = ic2_mem[n[8:1]];
633
 
634
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
635
                else            data2 = {12'h0, data[31:16], 4'h0};
636
 
637
                if(     (data1 !== data2) |
638
                        (^data1 === 1'hx) |
639
                        (^data2 === 1'hx)
640
                        )
641
                   begin
642
                        $display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
643
                        n, data2, data1);
644
                        error_cnt = error_cnt + 1;
645
                   end
646
           end
647
 
648
show_errors;
649
$display("*****************************************************");
650
$display("*** Test DONE ...                                 ***");
651
$display("*****************************************************\n\n");
652
 
653
end
654
endtask
655
 
656
 
657
 
658
task vsr1;
659
 
660
reg     [31:0]   data;
661
reg     [31:0]   data1;
662
reg     [31:0]   data2;
663
integer         size, frames, m;
664
 
665
begin
666
$display("\n\n");
667
$display("*****************************************************");
668
$display("*** VSR AC97 I/O Test ...                       ***");
669
$display("*****************************************************\n");
670
 
671
        wb_busy = 1;
672 10 rudi
        m0.wb_wr1(`INTM,4'hf, 32'h0492_4924);
673
 
674 7 rudi
        m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
675
        m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
676
        m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
677
 
678
        wb_busy = 0;
679 10 rudi
 
680 7 rudi
        oc0_dma_en = 1;
681
        oc1_dma_en = 1;
682
        oc2_dma_en = 1;
683
        oc3_dma_en = 1;
684
        oc4_dma_en = 1;
685
        oc5_dma_en = 1;
686
        ic0_dma_en = 1;
687
        ic1_dma_en = 1;
688
        ic2_dma_en = 1;
689
 
690
        for(n=0;n<256;n=n+1)
691
           begin
692
                oc0_mem[n] = $random;
693
                oc1_mem[n] = $random;
694
                oc2_mem[n] = $random;
695
                oc3_mem[n] = $random;
696
                oc4_mem[n] = $random;
697
                oc5_mem[n] = $random;
698
                ic0_mem[n] = $random;
699
                ic1_mem[n] = $random;
700
                ic2_mem[n] = $random;
701
           end
702
 
703
        u1.init(0);
704
 
705
        frames = 132;
706
 
707
        u1.tx1( frames,                                 // Number of frames to process
708
                0,                                       // How many frames before codec is ready
709
                10'b1101_1110_00,                        // Output slots valid bits
710
                10'b1101_0000_00,                        // Input slots valid bits
711
                20'b01_01_00_01_01_01_01_00_00_00,       // Output Slots intervals
712
                20'b01_01_00_01_00_00_00_00_00_00        // Input Slots intervals
713
                );
714
 
715
        size = (frames - 4)/2;
716
 
717
        for(n=0;n<size;n=n+1)
718
           begin
719
                data1 = u1.rs3_mem[n];
720
                data = oc0_mem[n[8:1]];
721
 
722
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
723
                else            data2 = {12'h0, data[31:16], 4'h0};
724
 
725
                if(     (data1 !== data2) |
726
                        (^data1 === 1'hx) |
727
                        (^data2 === 1'hx)
728
                        )
729
                   begin
730
                        $display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
731
                        n, data2, data1);
732
                        error_cnt = error_cnt + 1;
733
                   end
734
           end
735
 
736
        for(n=0;n<size;n=n+1)
737
           begin
738
                data1 = u1.rs4_mem[n];
739
                data = oc1_mem[n[8:1]];
740
 
741
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
742
                else            data2 = {12'h0, data[31:16], 4'h0};
743
 
744
                if(     (data1 !== data2) |
745
                        (^data1 === 1'hx) |
746
                        (^data2 === 1'hx)
747
                        )
748
                   begin
749
                        $display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
750
                        n, data2, data1);
751
                        error_cnt = error_cnt + 1;
752
                   end
753
           end
754
 
755
        for(n=0;n<size;n=n+1)
756
           begin
757
                data1 = u1.rs6_mem[n];
758
                data = oc2_mem[n[8:1]];
759
 
760
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
761
                else            data2 = {12'h0, data[31:16], 4'h0};
762
 
763
                if(     (data1 !== data2) |
764
                        (^data1 === 1'hx) |
765
                        (^data2 === 1'hx)
766
                        )
767
                   begin
768
                        $display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
769
                        n, data2, data1);
770
                        error_cnt = error_cnt + 1;
771
                   end
772
           end
773
 
774
        for(n=0;n<size;n=n+1)
775
           begin
776
                data1 = u1.rs7_mem[n];
777
                data = oc3_mem[n[8:1]];
778
 
779
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
780
                else            data2 = {12'h0, data[31:16], 4'h0};
781
 
782
                if(     (data1 !== data2) |
783
                        (^data1 === 1'hx) |
784
                        (^data2 === 1'hx)
785
                        )
786
                   begin
787
                        $display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
788
                        n, data2, data1);
789
                        error_cnt = error_cnt + 1;
790
                   end
791
           end
792
 
793
        for(n=0;n<size;n=n+1)
794
           begin
795
                data1 = u1.rs8_mem[n];
796
                data = oc4_mem[n[8:1]];
797
 
798
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
799
                else            data2 = {12'h0, data[31:16], 4'h0};
800
 
801
                if(     (data1 !== data2) |
802
                        (^data1 === 1'hx) |
803
                        (^data2 === 1'hx)
804
                        )
805
                   begin
806
                        $display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
807
                        n, data2, data1);
808
                        error_cnt = error_cnt + 1;
809
                   end
810
           end
811
 
812
        for(n=0;n<size;n=n+1)
813
           begin
814
                data1 = u1.rs9_mem[n];
815
                data = oc5_mem[n[8:1]];
816
 
817
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
818
                else            data2 = {12'h0, data[31:16], 4'h0};
819
 
820
                if(     (data1 !== data2) |
821
                        (^data1 === 1'hx) |
822
                        (^data2 === 1'hx)
823
                        )
824
                   begin
825
                        $display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
826
                        n, data2, data1);
827
                        error_cnt = error_cnt + 1;
828
                   end
829
           end
830
 
831
        for(n=0;n<size;n=n+1)
832
           begin
833
                data1 = u1.is3_mem[n];
834
                data = ic0_mem[n[8:1]];
835
 
836
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
837
                else            data2 = {12'h0, data[31:16], 4'h0};
838
 
839
                if(     (data1 !== data2) |
840
                        (^data1 === 1'hx) |
841
                        (^data2 === 1'hx)
842
                        )
843
                   begin
844
                        $display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
845
                        n, data2, data1);
846
                        error_cnt = error_cnt + 1;
847
                   end
848
           end
849
 
850
        for(n=0;n<size;n=n+1)
851
           begin
852
                data1 = u1.is4_mem[n];
853
                data = ic1_mem[n[8:1]];
854
 
855
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
856
                else            data2 = {12'h0, data[31:16], 4'h0};
857
 
858
                if(     (data1 !== data2) |
859
                        (^data1 === 1'hx) |
860
                        (^data2 === 1'hx)
861
                        )
862
                   begin
863
                        $display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
864
                        n, data2, data1);
865
                        error_cnt = error_cnt + 1;
866
                   end
867
           end
868
 
869
        for(n=0;n<size;n=n+1)
870
           begin
871
                data1 = u1.is6_mem[n];
872
                data = ic2_mem[n[8:1]];
873
 
874
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
875
                else            data2 = {12'h0, data[31:16], 4'h0};
876
 
877
                if(     (data1 !== data2) |
878
                        (^data1 === 1'hx) |
879
                        (^data2 === 1'hx)
880
                        )
881
                   begin
882
                        $display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
883
                        n, data2, data1);
884
                        error_cnt = error_cnt + 1;
885
                   end
886
           end
887
 
888
repeat(10)      @(posedge clk);
889
 
890
show_errors;
891
$display("*****************************************************");
892
$display("*** Test DONE ...                                 ***");
893
$display("*****************************************************\n\n");
894
 
895
end
896
endtask
897
 
898
 
899 10 rudi
 
900
task vsr_int;
901
 
902
reg     [31:0]   data;
903
reg     [31:0]   data1;
904
reg     [31:0]   data2;
905
integer         size, frames, m, th, smpl;
906
 
907
begin
908
$display("\n\n");
909
$display("*****************************************************");
910
$display("*** VSR AC97 I/O Test (INT ctrl) ...              ***");
911
$display("*****************************************************\n");
912
 
913
for(smpl=0;smpl<4;smpl=smpl+1)
914
begin
915
$display("Sampling selection: %0d",smpl);
916
for(th=0;th<4;th=th+1)
917
   begin
918
        do_rst;
919
 
920
        while(wb_busy)  @(posedge clk);
921
 
922
        wb_busy = 1;
923
 
924
        m0.wb_wr1(`INTM,4'hf, 32'hffff_fffc);
925
 
926
        case(th)
927
        0:
928
        begin
929 11 rudi
        $display("Interrupt threshold: 100%");
930 10 rudi
        oc0_th = 4;     // 100% (4/4) Full Empty
931
        oc1_th = 4;
932
        oc2_th = 4;
933
        oc3_th = 4;
934
        oc4_th = 4;
935
        oc5_th = 4;
936
        ic0_th = 4;
937
        ic1_th = 4;
938
        ic2_th = 4;
939
 
940
        m0.wb_wr1(`OCC0,4'hf, 32'h3333_3333);
941
        m0.wb_wr1(`OCC1,4'hf, 32'h0000_3333);
942
        m0.wb_wr1(`ICC,4'hf, 32'h0033_3333);
943
        end
944
 
945
        1:
946
        begin
947 11 rudi
        $display("Interrupt threshold: 75%");
948 10 rudi
        oc0_th = 3;     // 75% (3/4) Full Empty
949
        oc1_th = 3;
950
        oc2_th = 3;
951
        oc3_th = 3;
952
        oc4_th = 3;
953
        oc5_th = 3;
954
        ic0_th = 3;
955
        ic1_th = 3;
956
        ic2_th = 3;
957
 
958
        m0.wb_wr1(`OCC0,4'hf, 32'h2323_2323);
959
        m0.wb_wr1(`OCC1,4'hf, 32'h0000_2323);
960
        m0.wb_wr1(`ICC,4'hf, 32'h0023_2323);
961
        end
962
 
963
        2:
964
        begin
965 11 rudi
        $display("Interrupt threshold: 50%");
966 10 rudi
        oc0_th = 2;     // 50% (1/2) Full/Empty
967
        oc1_th = 2;
968
        oc2_th = 2;
969
        oc3_th = 2;
970
        oc4_th = 2;
971
        oc5_th = 2;
972
        ic0_th = 2;
973
        ic1_th = 2;
974
        ic2_th = 2;
975
 
976
        m0.wb_wr1(`OCC0,4'hf, 32'h1313_1313);
977
        m0.wb_wr1(`OCC1,4'hf, 32'h0000_1313);
978
        m0.wb_wr1(`ICC,4'hf, 32'h0013_1313);
979
        end
980
 
981
        3:
982
        begin
983 11 rudi
        $display("Interrupt threshold: 25%");
984 10 rudi
        oc0_th = 1;     // 25% (1/4) Full/Empty
985
        oc1_th = 1;
986
        oc2_th = 1;
987
        oc3_th = 1;
988
        oc4_th = 1;
989
        oc5_th = 1;
990
        ic0_th = 1;
991
        ic1_th = 1;
992
        ic2_th = 1;
993
 
994
        m0.wb_wr1(`OCC0,4'hf, 32'h0303_0303);
995
        m0.wb_wr1(`OCC1,4'hf, 32'h0000_0303);
996
        m0.wb_wr1(`ICC,4'hf, 32'h0003_0303);
997
        end
998
        endcase
999
 
1000 12 rudi
 
1001
`ifdef AC97_OUT_FIFO_DEPTH_8
1002
        oc0_th = oc0_th * 2;
1003
        oc1_th = oc1_th * 2;
1004
        oc2_th = oc2_th * 2;
1005
        oc3_th = oc3_th * 2;
1006
        oc4_th = oc4_th * 2;
1007
        oc5_th = oc5_th * 2;
1008
`endif
1009
 
1010
`ifdef AC97_OUT_FIFO_DEPTH_16
1011
        oc0_th = oc0_th * 4;
1012
        oc1_th = oc1_th * 4;
1013
        oc2_th = oc2_th * 4;
1014
        oc3_th = oc3_th * 4;
1015
        oc4_th = oc4_th * 4;
1016
        oc5_th = oc5_th * 4;
1017
`endif
1018
 
1019
 
1020
 
1021
`ifdef AC97_IN_FIFO_DEPTH_8
1022
        ic0_th = ic0_th * 2;
1023
        ic1_th = ic1_th * 2;
1024
        ic2_th = ic2_th * 2;
1025
`endif
1026
 
1027
`ifdef AC97_IN_FIFO_DEPTH_16
1028
        ic0_th = ic0_th * 4;
1029
        ic1_th = ic1_th * 4;
1030
        ic2_th = ic2_th * 4;
1031
`endif
1032
 
1033 10 rudi
        wb_busy = 0;
1034
 
1035
        oc0_dma_en = 0;
1036
        oc1_dma_en = 0;
1037
        oc2_dma_en = 0;
1038
        oc3_dma_en = 0;
1039
        oc4_dma_en = 0;
1040
        oc5_dma_en = 0;
1041
        ic0_dma_en = 0;
1042
        ic1_dma_en = 0;
1043
        ic2_dma_en = 0;
1044
        int_chk_en = 0;
1045
        int_ctrl_en = 1;
1046
 
1047
        for(n=0;n<256;n=n+1)
1048
           begin
1049
                oc0_mem[n] = $random;
1050
                oc1_mem[n] = $random;
1051
                oc2_mem[n] = $random;
1052
                oc3_mem[n] = $random;
1053
                oc4_mem[n] = $random;
1054
                oc5_mem[n] = $random;
1055
                ic0_mem[n] = $random;
1056
                ic1_mem[n] = $random;
1057
                ic2_mem[n] = $random;
1058
           end
1059
 
1060
        u1.init(0);
1061
        frames = 132;
1062
        frames = 132 + 132 + 132;
1063
 
1064
 
1065
        case(smpl)
1066
           0:    // All FULL Speed (48 Khz per channel)
1067
                u1.tx1( frames,                 // Number of frames to process
1068
                        0,                       // How many frames before codec is ready
1069
                        10'b1101_1110_00,        // Output slots valid bits
1070
                        10'b1101_0000_00,        // Input slots valid bits
1071
                        20'b00_00_00_00_00_00_00_00_00_00,  // Output Slots intervals
1072
                        20'b00_00_00_00_00_00_00_00_00_00  // Input Slots intervals
1073
                        );
1074
           1:   // All 1/4 Speed (12 Khz per channel)
1075
                u1.tx1( frames,                 // Number of frames to process
1076
                        0,                       // How many frames before codec is ready
1077
                        10'b1101_1110_00,        // Output slots valid bits
1078
                        10'b1101_0000_00,        // Input slots valid bits
1079
                        20'b11_11_00_11_11_11_11_00_00_00,  // Output Slots intervals
1080
                        20'b11_11_00_11_00_00_00_00_00_00  // Input Slots intervals
1081
                        );
1082
           2:   // Mix 1
1083
                u1.tx1( frames,                 // Number of frames to process
1084
                        0,                       // How many frames before codec is ready
1085
                        10'b1101_1110_00,        // Output slots valid bits
1086
                        10'b1101_0000_00,        // Input slots valid bits
1087
                        20'b00_01_00_10_11_01_10_00_00_00,  // Output Slots intervals
1088
                        20'b11_10_00_01_00_00_00_00_00_00  // Input Slots intervals
1089
                        );
1090
           3:   // Mix 2
1091
                u1.tx1( frames,                 // Number of frames to process
1092
                        0,                       // How many frames before codec is ready
1093
                        10'b1101_1110_00,        // Output slots valid bits
1094
                        10'b1101_0000_00,        // Input slots valid bits
1095
                        20'b00_00_00_01_01_10_10_00_00_00,  // Output Slots intervals
1096
                        20'b00_00_00_10_00_00_00_00_00_00  // Input Slots intervals
1097
                        );
1098
        endcase
1099
 
1100
 
1101
        size = (frames - 4)/2;
1102
        size = (frames - 4)/3;
1103
        size = size - 36;
1104
 
1105
        repeat(100)     @(posedge clk);
1106
 
1107
        for(n=0;n<size;n=n+1)
1108
           begin
1109
                data1 = u1.rs3_mem[n];
1110
                data = oc0_mem[n[8:1]];
1111
 
1112
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
1113
                else            data2 = {12'h0, data[31:16], 4'h0};
1114
 
1115
                if(     (data1 !== data2) |
1116
                        (^data1 === 1'hx) |
1117
                        (^data2 === 1'hx)
1118
                        )
1119
                   begin
1120
                        $display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
1121
                        n, data2, data1);
1122
                        error_cnt = error_cnt + 1;
1123
                   end
1124
           end
1125
 
1126
 
1127
        for(n=0;n<size;n=n+1)
1128
           begin
1129
                data1 = u1.rs4_mem[n];
1130
                data = oc1_mem[n[8:1]];
1131
 
1132
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
1133
                else            data2 = {12'h0, data[31:16], 4'h0};
1134
 
1135
                if(     (data1 !== data2) |
1136
                        (^data1 === 1'hx) |
1137
                        (^data2 === 1'hx)
1138
                        )
1139
                   begin
1140
                        $display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
1141
                        n, data2, data1);
1142
                        error_cnt = error_cnt + 1;
1143
                   end
1144
           end
1145
 
1146
        for(n=0;n<size;n=n+1)
1147
           begin
1148
                data1 = u1.rs6_mem[n];
1149
                data = oc2_mem[n[8:1]];
1150
 
1151
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
1152
                else            data2 = {12'h0, data[31:16], 4'h0};
1153
 
1154
                if(     (data1 !== data2) |
1155
                        (^data1 === 1'hx) |
1156
                        (^data2 === 1'hx)
1157
                        )
1158
                   begin
1159
                        $display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
1160
                        n, data2, data1);
1161
                        error_cnt = error_cnt + 1;
1162
                   end
1163
           end
1164
 
1165
        for(n=0;n<size;n=n+1)
1166
           begin
1167
                data1 = u1.rs7_mem[n];
1168
                data = oc3_mem[n[8:1]];
1169
 
1170
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
1171
                else            data2 = {12'h0, data[31:16], 4'h0};
1172
 
1173
                if(     (data1 !== data2) |
1174
                        (^data1 === 1'hx) |
1175
                        (^data2 === 1'hx)
1176
                        )
1177
                   begin
1178
                        $display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
1179
                        n, data2, data1);
1180
                        error_cnt = error_cnt + 1;
1181
                   end
1182
           end
1183
 
1184
        for(n=0;n<size;n=n+1)
1185
           begin
1186
                data1 = u1.rs8_mem[n];
1187
                data = oc4_mem[n[8:1]];
1188
 
1189
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
1190
                else            data2 = {12'h0, data[31:16], 4'h0};
1191
 
1192
                if(     (data1 !== data2) |
1193
                        (^data1 === 1'hx) |
1194
                        (^data2 === 1'hx)
1195
                        )
1196
                   begin
1197
                        $display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
1198
                        n, data2, data1);
1199
                        error_cnt = error_cnt + 1;
1200
                   end
1201
           end
1202
 
1203
        for(n=0;n<size;n=n+1)
1204
           begin
1205
                data1 = u1.rs9_mem[n];
1206
                data = oc5_mem[n[8:1]];
1207
 
1208
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
1209
                else            data2 = {12'h0, data[31:16], 4'h0};
1210
 
1211
                if(     (data1 !== data2) |
1212
                        (^data1 === 1'hx) |
1213
                        (^data2 === 1'hx)
1214
                        )
1215
                   begin
1216
                        $display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
1217
                        n, data2, data1);
1218
                        error_cnt = error_cnt + 1;
1219
                   end
1220
           end
1221
 
1222
        for(n=0;n<size;n=n+1)
1223
           begin
1224
                data1 = u1.is3_mem[n];
1225
                data = ic0_mem[n[8:1]];
1226
 
1227
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
1228
                else            data2 = {12'h0, data[31:16], 4'h0};
1229
 
1230
                if(     (data1 !== data2) |
1231
                        (^data1 === 1'hx) |
1232
                        (^data2 === 1'hx)
1233
                        )
1234
                   begin
1235
                        $display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
1236
                        n, data2, data1);
1237
                        error_cnt = error_cnt + 1;
1238
                   end
1239
           end
1240
 
1241
        for(n=0;n<size;n=n+1)
1242
           begin
1243
                data1 = u1.is4_mem[n];
1244
                data = ic1_mem[n[8:1]];
1245
 
1246
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
1247
                else            data2 = {12'h0, data[31:16], 4'h0};
1248
 
1249
                if(     (data1 !== data2) |
1250
                        (^data1 === 1'hx) |
1251
                        (^data2 === 1'hx)
1252
                        )
1253
                   begin
1254
                        $display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
1255
                        n, data2, data1);
1256
                        error_cnt = error_cnt + 1;
1257
                   end
1258
           end
1259
 
1260
        for(n=0;n<size;n=n+1)
1261
           begin
1262
                data1 = u1.is6_mem[n];
1263
                data = ic2_mem[n[8:1]];
1264
 
1265
                if(~n[0])        data2 = {12'h0, data[15:0], 4'h0};
1266
                else            data2 = {12'h0, data[31:16], 4'h0};
1267
 
1268
                if(     (data1 !== data2) |
1269
                        (^data1 === 1'hx) |
1270
                        (^data2 === 1'hx)
1271
                        )
1272
                   begin
1273
                        $display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
1274
                        n, data2, data1);
1275
                        error_cnt = error_cnt + 1;
1276
                   end
1277
           end
1278
 
1279
repeat(10)      @(posedge clk);
1280
end
1281
end
1282
 
1283
$display("Processed %0d samples per channel for each test",size);
1284
 
1285
show_errors;
1286
$display("*****************************************************");
1287
$display("*** Test DONE ...                                 ***");
1288
$display("*****************************************************\n\n");
1289
 
1290
end
1291
endtask
1292
 
1293
 
1294
 

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