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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
//
//  $Date: 2002-02-13 08:22:32 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//                        
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
reg     [31:0]   rd_mem[mem_size:0];
reg     [31:0]   wr_mem[mem_size:0];
integer         rd_cnt;
integer         wr_cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        //adr = 32'hxxxx_xxxx;
        //adr = 0;
        adr = 32'hffff_ffff;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        rd_cnt = 0;
        wr_cnt = 0;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
 
 
task mem_fill;
 
integer n;
begin
rd_cnt = 0;
wr_cnt = 0;
for(n=0;n<mem_size;n=n+1)
   begin
        rd_mem[n] = $random;
        wr_mem[n] = $random;
   end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
//adr = 0;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
//adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
//adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
//adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
 
for(n=0;n<count;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
        if(n!=0) @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + count;
end
endtask
 
 
task wb_rmw;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + rcount;
 
//@(posedge clk);
 
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
//      if(n!=0)
                @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + wcount;
end
endtask
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
//@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err)      @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
//adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
//adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
//adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
end
endtask
 
 
 
task wb_rd_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + count;
end
endtask
 
endmodule

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[/] [ac97/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 21

Line No.	Rev	Author	Line
1	7	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_mast_model.v,v 1.1 2002-02-13 08:22:32 rudi Exp $`
41			`//`
42			`// $Date: 2002-02-13 08:22:32 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`//`
52			`//`
53			`//`
54
55			`include "wb_model_defines.v"
56
57			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
58
59			`input clk, rst;`
60			`output [31:0] adr;`
61			`input [31:0] din;`
62			`output [31:0] dout;`
63			`output cyc, stb;`
64			`output [3:0] sel;`
65			`output we;`
66			`input ack, err, rty;`
67
68			`////////////////////////////////////////////////////////////////////`
69			`//`
70			`// Local Wires`
71			`//`
72
73			`parameter mem_size = 4096;`
74
75			`reg [31:0] adr;`
76			`reg [31:0] dout;`
77			`reg cyc, stb;`
78			`reg [3:0] sel;`
79			`reg we;`
80
81			`reg [31:0] rd_mem[mem_size:0];`
82			`reg [31:0] wr_mem[mem_size:0];`
83			`integer rd_cnt;`
84			`integer wr_cnt;`
85
86			`////////////////////////////////////////////////////////////////////`
87			`//`
88			`// Memory Logic`
89			`//`
90
91			`initial`
92			`begin`
93			`//adr = 32'hxxxx_xxxx;`
94			`//adr = 0;`
95			`adr = 32'hffff_ffff;`
96			`dout = 32'hxxxx_xxxx;`
97			`cyc = 0;`
98			`stb = 0;`
99			`sel = 4'hx;`
100			`we = 1'hx;`
101			`rd_cnt = 0;`
102			`wr_cnt = 0;`
103			`#1;`
104			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
105			`end`
106
107
108
109			`task mem_fill;`
110
111			`integer n;`
112			`begin`
113			`rd_cnt = 0;`
114			`wr_cnt = 0;`
115			`for(n=0;n<mem_size;n=n+1)`
116			`begin`
117			`rd_mem[n] = $random;`
118			`wr_mem[n] = $random;`
119			`end`
120			`end`
121			`endtask`
122
123			`////////////////////////////////////////////////////////////////////`
124			`//`
125			`// Write 1 Word Task`
126			`//`
127
128			`task wb_wr1;`
129			`input [31:0] a;`
130			`input [3:0] s;`
131			`input [31:0] d;`
132
133			`begin`
134
135			`@(posedge clk);`
136			`#1;`
137			`adr = a;`
138			`dout = d;`
139			`cyc = 1;`
140			`stb = 1;`
141			`we=1;`
142			`sel = s;`
143
144			`@(posedge clk);`
145			`while(~ack & ~err) @(posedge clk);`
146			`#1;`
147			`cyc=0;`
148			`stb=0;`
149			`adr = 32'hxxxx_xxxx;`
150			`//adr = 32'hffff_ffff;`
151			`//adr = 0;`
152			`dout = 32'hxxxx_xxxx;`
153			`we = 1'hx;`
154			`sel = 4'hx;`
155
156			`end`
157			`endtask`
158
159			`////////////////////////////////////////////////////////////////////`
160			`//`
161			`// Write 4 Words Task`
162			`//`
163
164			`task wb_wr4;`
165			`input [31:0] a;`
166			`input [3:0] s;`
167			`input delay;`
168			`input [31:0] d1;`
169			`input [31:0] d2;`
170			`input [31:0] d3;`
171			`input [31:0] d4;`
172
173			`integer delay;`
174
175			`begin`
176
177			`@(posedge clk);`
178			`#1;`
179			`cyc = 1;`
180			`sel = s;`
181
182			`repeat(delay)`
183			`begin`
184			`@(posedge clk);`
185			`#1;`
186			`end`
187			`adr = a;`
188			`dout = d1;`
189			`stb = 1;`
190			`we=1;`
191			`while(~ack & ~err) @(posedge clk);`
192			`#2;`
193			`stb=0;`
194			`we=1'bx;`
195			`dout = 32'hxxxx_xxxx;`
196
197
198			`repeat(delay)`
199			`begin`
200			`@(posedge clk);`
201			`#1;`
202			`end`
203			`stb=1;`
204			`//adr = a+4;`
205			`dout = d2;`
206			`we=1;`
207			`@(posedge clk);`
208			`while(~ack & ~err) @(posedge clk);`
209			`#2;`
210			`stb=0;`
211			`we=1'bx;`
212			`dout = 32'hxxxx_xxxx;`
213
214			`repeat(delay)`
215			`begin`
216			`@(posedge clk);`
217			`#1;`
218			`end`
219			`stb=1;`
220			`//adr = a+8;`
221			`dout = d3;`
222			`we=1;`
223			`@(posedge clk);`
224			`while(~ack & ~err) @(posedge clk);`
225			`#2;`
226			`stb=0;`
227			`we=1'bx;`
228			`dout = 32'hxxxx_xxxx;`
229
230			`repeat(delay)`
231			`begin`
232			`@(posedge clk);`
233			`#1;`
234			`end`
235			`stb=1;`
236			`//adr = a+12;`
237			`dout = d4;`
238			`we=1;`
239			`@(posedge clk);`
240			`while(~ack & ~err) @(posedge clk);`
241			`#1;`
242			`stb=0;`
243			`cyc=0;`
244
245			`adr = 32'hxxxx_xxxx;`
246			`//adr = 0;`
247			`//adr = 32'hffff_ffff;`
248			`dout = 32'hxxxx_xxxx;`
249			`we = 1'hx;`
250			`sel = 4'hx;`
251
252			`end`
253			`endtask`
254
255
256			`task wb_wr_mult;`
257			`input [31:0] a;`
258			`input [3:0] s;`
259			`input delay;`
260			`input count;`
261
262			`integer delay;`
263			`integer count;`
264			`integer n;`
265
266			`begin`
267
268			`@(posedge clk);`
269			`#1;`
270			`cyc = 1;`
271
272			`for(n=0;n<count;n=n+1)`
273			`begin`
274			`repeat(delay)`
275			`begin`
276			`@(posedge clk);`
277			`#1;`
278			`end`
279			`adr = a + (n*4);`
280			`dout = wr_mem[n + wr_cnt];`
281			`stb = 1;`
282			`we=1;`
283			`sel = s;`
284			`if(n!=0) @(posedge clk);`
285			`while(~ack & ~err) @(posedge clk);`
286			`#2;`
287			`stb=0;`
288			`we=1'bx;`
289			`sel = 4'hx;`
290			`dout = 32'hxxxx_xxxx;`
291			`adr = 32'hxxxx_xxxx;`
292			`end`
293
294			`cyc=0;`
295
296			`adr = 32'hxxxx_xxxx;`
297			`//adr = 32'hffff_ffff;`
298
299			`wr_cnt = wr_cnt + count;`
300			`end`
301			`endtask`
302
303
304			`task wb_rmw;`
305			`input [31:0] a;`
306			`input [3:0] s;`
307			`input delay;`
308			`input rcount;`
309			`input wcount;`
310
311			`integer delay;`
312			`integer rcount;`
313			`integer wcount;`
314			`integer n;`
315
316			`begin`
317
318			`@(posedge clk);`
319			`#1;`
320			`cyc = 1;`
321			`we = 0;`
322			`sel = s;`
323			`repeat(delay) @(posedge clk);`
324
325			`for(n=0;n<rcount-1;n=n+1)`
326			`begin`
327			`adr = a + (n*4);`
328			`stb = 1;`
329			`while(~ack & ~err) @(posedge clk);`
330			`rd_mem[n + rd_cnt] = din;`
331			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
332			`#2;`
333			`stb=0;`
334			`we = 1'hx;`
335			`sel = 4'hx;`
336			`adr = 32'hxxxx_xxxx;`
337			`repeat(delay)`
338			`begin`
339			`@(posedge clk);`
340			`#1;`
341			`end`
342			`we = 0;`
343			`sel = s;`
344			`end`
345
346			`adr = a+(n*4);`
347			`stb = 1;`
348			`@(posedge clk);`
349			`while(~ack & ~err) @(posedge clk);`
350			`rd_mem[n + rd_cnt] = din;`
351			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
352			`#1;`
353			`stb=0;`
354			`we = 1'hx;`
355			`sel = 4'hx;`
356			`adr = 32'hxxxx_xxxx;`
357
358			`rd_cnt = rd_cnt + rcount;`
359
360			`//@(posedge clk);`
361
362
363			`for(n=0;n<wcount;n=n+1)`
364			`begin`
365			`repeat(delay)`
366			`begin`
367			`@(posedge clk);`
368			`#1;`
369			`end`
370			`adr = a + (n*4);`
371			`dout = wr_mem[n + wr_cnt];`
372			`stb = 1;`
373			`we=1;`
374			`sel = s;`
375			`// if(n!=0)`
376			`@(posedge clk);`
377			`while(~ack & ~err) @(posedge clk);`
378			`#2;`
379			`stb=0;`
380			`we=1'bx;`
381			`sel = 4'hx;`
382			`dout = 32'hxxxx_xxxx;`
383			`adr = 32'hxxxx_xxxx;`
384			`end`
385
386			`cyc=0;`
387
388			`adr = 32'hxxxx_xxxx;`
389			`//adr = 32'hffff_ffff;`
390
391			`wr_cnt = wr_cnt + wcount;`
392			`end`
393			`endtask`
394
395
396
397			`////////////////////////////////////////////////////////////////////`
398			`//`
399			`// Read 1 Word Task`
400			`//`
401
402			`task wb_rd1;`
403			`input [31:0] a;`
404			`input [3:0] s;`
405			`output [31:0] d;`
406
407			`begin`
408
409			`@(posedge clk);`
410			`#1;`
411			`adr = a;`
412			`cyc = 1;`
413			`stb = 1;`
414			`we = 0;`
415			`sel = s;`
416
417			`//@(posedge clk);`
418			`while(~ack & ~err) @(posedge clk);`
419			`d = din;`
420			`#1;`
421			`cyc=0;`
422			`stb=0;`
423			`//adr = 32'hxxxx_xxxx;`
424			`//adr = 0;`
425			`adr = 32'hffff_ffff;`
426			`dout = 32'hxxxx_xxxx;`
427			`we = 1'hx;`
428			`sel = 4'hx;`
429
430			`end`
431			`endtask`
432
433
434			`////////////////////////////////////////////////////////////////////`
435			`//`
436			`// Read 4 Words Task`
437			`//`
438
439
440			`task wb_rd4;`
441			`input [31:0] a;`
442			`input [3:0] s;`
443			`input delay;`
444			`output [31:0] d1;`
445			`output [31:0] d2;`
446			`output [31:0] d3;`
447			`output [31:0] d4;`
448
449			`integer delay;`
450			`begin`
451
452			`@(posedge clk);`
453			`#1;`
454			`cyc = 1;`
455			`we = 0;`
456			`sel = s;`
457			`repeat(delay) @(posedge clk);`
458
459			`adr = a;`
460			`stb = 1;`
461			`while(~ack & ~err) @(posedge clk);`
462			`d1 = din;`
463			`#2;`
464			`stb=0;`
465			`we = 1'hx;`
466			`sel = 4'hx;`
467			`repeat(delay)`
468			`begin`
469			`@(posedge clk);`
470			`#1;`
471			`end`
472			`we = 0;`
473			`sel = s;`
474
475			`//adr = a+4;`
476			`stb = 1;`
477			`@(posedge clk);`
478			`while(~ack & ~err) @(posedge clk);`
479			`d2 = din;`
480			`#2;`
481			`stb=0;`
482			`we = 1'hx;`
483			`sel = 4'hx;`
484			`repeat(delay)`
485			`begin`
486			`@(posedge clk);`
487			`#1;`
488			`end`
489			`we = 0;`
490			`sel = s;`
491
492
493			`//adr = a+8;`
494			`stb = 1;`
495			`@(posedge clk);`
496			`while(~ack & ~err) @(posedge clk);`
497			`d3 = din;`
498			`#2;`
499			`stb=0;`
500			`we = 1'hx;`
501			`sel = 4'hx;`
502			`repeat(delay)`
503			`begin`
504			`@(posedge clk);`
505			`#1;`
506			`end`
507			`we = 0;`
508			`sel = s;`
509
510			`//adr = a+12;`
511			`stb = 1;`
512			`@(posedge clk);`
513			`while(~ack & ~err) @(posedge clk);`
514			`d4 = din;`
515			`#1;`
516			`stb=0;`
517			`cyc=0;`
518			`we = 1'hx;`
519			`sel = 4'hx;`
520			`adr = 32'hffff_ffff;`
521			`end`
522			`endtask`
523
524
525
526			`task wb_rd_mult;`
527			`input [31:0] a;`
528			`input [3:0] s;`
529			`input delay;`
530			`input count;`
531
532			`integer delay;`
533			`integer count;`
534			`integer n;`
535
536			`begin`
537
538			`@(posedge clk);`
539			`#1;`
540			`cyc = 1;`
541			`we = 0;`
542			`sel = s;`
543			`repeat(delay) @(posedge clk);`
544
545			`for(n=0;n<count-1;n=n+1)`
546			`begin`
547			`adr = a + (n*4);`
548			`stb = 1;`
549			`while(~ack & ~err) @(posedge clk);`
550			`rd_mem[n + rd_cnt] = din;`
551			`#2;`
552			`stb=0;`
553			`we = 1'hx;`
554			`sel = 4'hx;`
555			`adr = 32'hxxxx_xxxx;`
556			`repeat(delay)`
557			`begin`
558			`@(posedge clk);`
559			`#1;`
560			`end`
561			`we = 0;`
562			`sel = s;`
563			`end`
564
565			`adr = a+(n*4);`
566			`stb = 1;`
567			`@(posedge clk);`
568			`while(~ack & ~err) @(posedge clk);`
569			`rd_mem[n + rd_cnt] = din;`
570			`#1;`
571			`stb=0;`
572			`cyc=0;`
573			`we = 1'hx;`
574			`sel = 4'hx;`
575			`adr = 32'hffff_ffff;`
576			`adr = 32'hxxxx_xxxx;`
577
578			`rd_cnt = rd_cnt + count;`
579			`end`
580			`endtask`
581
582			`endmodule`