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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_cra.v] - Blame information for rev 20

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE AC 97 Controller                                  ////
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////  Codec Register Access Module                               ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: ac97_cra.v,v 1.3 2002-09-19 06:30:56 rudi Exp $
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//
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//  $Date: 2002-09-19 06:30:56 $
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//  $Revision: 1.3 $
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//  $Author: rudi $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.2  2002/03/05 04:44:05  rudi
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//
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//               - Fixed the order of the thrash hold bits to match the spec.
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//               - Many minor synthesis cleanup items ...
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//
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//               Revision 1.1  2001/08/03 06:54:49  rudi
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//
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//
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//               - Changed to new directory structure
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//
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//               Revision 1.1.1.1  2001/05/19 02:29:18  rudi
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//               Initial Checkin
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//
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//
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//
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//
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`include "ac97_defines.v"
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module ac97_cra(clk, rst,
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                crac_we, crac_din, crac_out,
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                crac_wr_done, crac_rd_done,
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                valid, out_slt1, out_slt2,
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                in_slt2,
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                crac_valid, crac_wr
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                );
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input           clk, rst;
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input           crac_we;
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output  [15:0]   crac_din;
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input   [31:0]   crac_out;
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output          crac_wr_done, crac_rd_done;
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input           valid;
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output  [19:0]   out_slt1;
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output  [19:0]   out_slt2;
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input   [19:0]   in_slt2;
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output          crac_valid;
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output          crac_wr;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg             crac_wr;
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reg             crac_rd;
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reg             crac_rd_done;
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reg     [15:0]   crac_din;
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reg             crac_we_r;
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reg             valid_r;
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wire            valid_ne;
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wire            valid_pe;
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reg             rdd1, rdd2, rdd3;
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////////////////////////////////////////////////////////////////////
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//
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// Codec Register Data Path
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//
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// Control
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assign out_slt1[19]    = crac_out[31];
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assign out_slt1[18:12] = crac_out[22:16];
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assign out_slt1[11:0]  = 12'h0;
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// Write Data
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assign out_slt2[19:4] = crac_out[15:0];
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assign out_slt2[3:0] = 4'h0;
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// Read Data
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always @(posedge clk or negedge rst)
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   begin
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        if(!rst)                crac_din <= #1 16'h0;
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        else
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        if(crac_rd_done)        crac_din <= #1 in_slt2[19:4];
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   end
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////////////////////////////////////////////////////////////////////
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//
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// Codec Register Access Tracking
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//
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assign crac_valid = crac_wr | crac_rd;
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always @(posedge clk)
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        crac_we_r <= #1 crac_we;
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always @(posedge clk or negedge rst)
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        if(!rst)                        crac_wr <= #1 1'b0;
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        else
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        if(crac_we_r & !crac_out[31])   crac_wr <= #1 1'b1;
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        else
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        if(valid_ne)                    crac_wr <= #1 1'b0;
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assign crac_wr_done = crac_wr & valid_ne;
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always @(posedge clk or negedge rst)
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        if(!rst)                        crac_rd <= #1 1'b0;
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        else
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        if(crac_we_r & crac_out[31])    crac_rd <= #1 1'b1;
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        else
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        if(rdd1 & valid_pe)             crac_rd <= #1 1'b0;
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always @(posedge clk or negedge rst)
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        if(!rst)                        rdd1 <= #1 1'b0;
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        else
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        if(crac_rd & valid_ne)          rdd1 <= #1 1'b1;
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        else
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        if(!crac_rd)                    rdd1 <= #1 1'b0;
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always @(posedge clk or negedge rst)
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        if(!rst)                                        rdd2 <= #1 1'b0;
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        else
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        if( (crac_rd & valid_ne) | (!rdd3 & rdd2) )     rdd2 <= #1 1'b1;
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        else
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        if(crac_rd_done)                                rdd2 <= #1 1'b0;
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always @(posedge clk or negedge rst)
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        if(!rst)                        rdd3 <= #1 1'b0;
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        else
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        if(rdd2 & valid_pe)             rdd3 <= #1 1'b1;
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        else
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        if(crac_rd_done)                rdd3 <= #1 1'b0;
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always @(posedge clk)
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        crac_rd_done <= #1 rdd3 & valid_pe;
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always @(posedge clk)
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        valid_r <= #1 valid;
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assign valid_ne = !valid & valid_r;
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assign valid_pe = valid & !valid_r;
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endmodule

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