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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_dma_req.v] - Blame information for rev 14

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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE AC 97 Controller                                  ////
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////  DMA Request Module                                         ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws                       ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: ac97_dma_req.v,v 1.3 2002-09-19 06:30:56 rudi Exp $
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//
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//  $Date: 2002-09-19 06:30:56 $
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//  $Revision: 1.3 $
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//  $Author: rudi $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.2  2002/03/05 04:44:05  rudi
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//
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//               - Fixed the order of the thrash hold bits to match the spec.
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//               - Many minor synthesis cleanup items ...
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//
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//               Revision 1.1  2001/08/03 06:54:49  rudi
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//
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//
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//               - Changed to new directory structure
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//
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//               Revision 1.1.1.1  2001/05/19 02:29:16  rudi
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//               Initial Checkin
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//
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//
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//
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//
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`include "ac97_defines.v"
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module ac97_dma_req(clk, rst, cfg, status, full_empty, dma_req, dma_ack);
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input           clk, rst;
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input   [7:0]    cfg;
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input   [1:0]    status;
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input           full_empty;
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output          dma_req;
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input           dma_ack;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg     dma_req_d;
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reg     dma_req_r1;
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reg     dma_req;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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always @(cfg or status or full_empty)
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        case(cfg[5:4])  // synopsys parallel_case full_case
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                        // REQ = Ch_EN & DMA_EN & Status
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                        // 1/4 full/empty
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           2'h2: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status == 2'h0));
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                        // 1/2 full/empty
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           2'h1: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status[1] == 1'h0));
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                        // 3/4 full/empty
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           2'h0: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status < 2'h3));
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           2'h3: dma_req_d = cfg[0] & cfg[6] & full_empty;
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        endcase
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always @(posedge clk)
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        dma_req_r1 <= #1 dma_req_d & !dma_ack;
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always @(posedge clk or negedge rst)
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        if(!rst)                                dma_req <= #1 1'b0;
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        else
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        if(dma_req_r1 & dma_req_d & !dma_ack)   dma_req <= #1 1'b1;
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        else
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        if(dma_ack)                             dma_req <= #1 1'b0;
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endmodule
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