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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_fifo_ctrl.v] - Blame information for rev 10

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  FIFO Control Module                                        ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_fifo_ctrl.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
//  $Date: 2002-03-05 04:44:05 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2001/08/03 06:54:49  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:18  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_fifo_ctrl(  clk,
                        valid, ch_en, srs, full_empty, req, crdy,
                        en_out, en_out_l
                        );
input           clk;
input           valid;
input           ch_en;          // Channel Enable
input           srs;            // Sample Rate Select
input           full_empty;     // Fifo Status
input           req;            // Codec Request
input           crdy;           // Codec Ready
output          en_out;         // Output read/write pulse
output          en_out_l;       // Latched Output
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     en_out_l, en_out_l2;
reg     full_empty_r;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk)
        if(!valid)      full_empty_r <= #1 full_empty;
 
always @(posedge clk)
        if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) )
                en_out_l <= #1 1'b1;
        else
        if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) )
                en_out_l <= #1 1'b0;
 
always @(posedge clk)
        en_out_l2 <= #1 en_out_l & valid;
 
assign en_out = en_out_l & !en_out_l2 & valid;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// FIFO Control Module ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	10	rudi	`// $Id: ac97_fifo_ctrl.v,v 1.2 2002-03-05 04:44:05 rudi Exp $`
42	4	rudi	`//`
43	10	rudi	`// $Date: 2002-03-05 04:44:05 $`
44			`// $Revision: 1.2 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	10	rudi	`// Revision 1.1 2001/08/03 06:54:49 rudi`
52			`//`
53			`//`
54			`// - Changed to new directory structure`
55			`//`
56	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:18 rudi`
57			`// Initial Checkin`
58			`//`
59			`//`
60			`//`
61			`//`
62
63			`include "ac97_defines.v"
64
65			`module ac97_fifo_ctrl( clk,`
66			`valid, ch_en, srs, full_empty, req, crdy,`
67			`en_out, en_out_l`
68			`);`
69			`input clk;`
70			`input valid;`
71			`input ch_en; // Channel Enable`
72			`input srs; // Sample Rate Select`
73			`input full_empty; // Fifo Status`
74			`input req; // Codec Request`
75			`input crdy; // Codec Ready`
76			`output en_out; // Output read/write pulse`
77			`output en_out_l; // Latched Output`
78
79			`////////////////////////////////////////////////////////////////////`
80			`//`
81			`// Local Wires`
82			`//`
83
84			`reg en_out_l, en_out_l2;`
85			`reg full_empty_r;`
86
87			`////////////////////////////////////////////////////////////////////`
88			`//`
89			`// Misc Logic`
90			`//`
91
92			`always @(posedge clk)`
93			`if(!valid) full_empty_r <= #1 full_empty;`
94
95			`always @(posedge clk)`
96			`if(valid & ch_en & !full_empty_r & crdy & (!srs \| (srs & req) ) )`
97	10	rudi	`en_out_l <= #1 1'b1;`
98	4	rudi	`else`
99			`if(!valid & !(ch_en & !full_empty_r & crdy & (!srs \| (srs & req) )) )`
100	10	rudi	`en_out_l <= #1 1'b0;`
101	4	rudi
102			`always @(posedge clk)`
103			`en_out_l2 <= #1 en_out_l & valid;`
104
105			`assign en_out = en_out_l & !en_out_l2 & valid;`
106
107			`endmodule`

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_fifo_ctrl.v] - Blame information for rev 10