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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_fifo_ctrl.v] - Blame information for rev 17

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  FIFO Control Module                                        ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_fifo_ctrl.v,v 1.3 2002-09-19 06:30:56 rudi Exp $
//
//  $Date: 2002-09-19 06:30:56 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2002/03/05 04:44:05  rudi
//
//               - Fixed the order of the thrash hold bits to match the spec.
//               - Many minor synthesis cleanup items ...
//
//               Revision 1.1  2001/08/03 06:54:49  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:18  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_fifo_ctrl(  clk,
                        valid, ch_en, srs, full_empty, req, crdy,
                        en_out, en_out_l
                        );
input           clk;
input           valid;
input           ch_en;          // Channel Enable
input           srs;            // Sample Rate Select
input           full_empty;     // Fifo Status
input           req;            // Codec Request
input           crdy;           // Codec Ready
output          en_out;         // Output read/write pulse
output          en_out_l;       // Latched Output
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     en_out_l, en_out_l2;
reg     full_empty_r;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk)
        if(!valid)      full_empty_r <= #1 full_empty;
 
always @(posedge clk)
        if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) )
                en_out_l <= #1 1'b1;
        else
        if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) )
                en_out_l <= #1 1'b0;
 
always @(posedge clk)
        en_out_l2 <= #1 en_out_l & valid;
 
assign en_out = en_out_l & !en_out_l2 & valid;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// FIFO Control Module ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	14	rudi	`// $Id: ac97_fifo_ctrl.v,v 1.3 2002-09-19 06:30:56 rudi Exp $`
43	4	rudi	`//`
44	14	rudi	`// $Date: 2002-09-19 06:30:56 $`
45			`// $Revision: 1.3 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	14	rudi	`// Revision 1.2 2002/03/05 04:44:05 rudi`
53			`//`
54			`// - Fixed the order of the thrash hold bits to match the spec.`
55			`// - Many minor synthesis cleanup items ...`
56			`//`
57	10	rudi	`// Revision 1.1 2001/08/03 06:54:49 rudi`
58			`//`
59			`//`
60			`// - Changed to new directory structure`
61			`//`
62	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:18 rudi`
63			`// Initial Checkin`
64			`//`
65			`//`
66			`//`
67			`//`
68
69			`include "ac97_defines.v"
70
71			`module ac97_fifo_ctrl( clk,`
72			`valid, ch_en, srs, full_empty, req, crdy,`
73			`en_out, en_out_l`
74			`);`
75			`input clk;`
76			`input valid;`
77			`input ch_en; // Channel Enable`
78			`input srs; // Sample Rate Select`
79			`input full_empty; // Fifo Status`
80			`input req; // Codec Request`
81			`input crdy; // Codec Ready`
82			`output en_out; // Output read/write pulse`
83			`output en_out_l; // Latched Output`
84
85			`////////////////////////////////////////////////////////////////////`
86			`//`
87			`// Local Wires`
88			`//`
89
90			`reg en_out_l, en_out_l2;`
91			`reg full_empty_r;`
92
93			`////////////////////////////////////////////////////////////////////`
94			`//`
95			`// Misc Logic`
96			`//`
97
98			`always @(posedge clk)`
99			`if(!valid) full_empty_r <= #1 full_empty;`
100
101			`always @(posedge clk)`
102			`if(valid & ch_en & !full_empty_r & crdy & (!srs \| (srs & req) ) )`
103	10	rudi	`en_out_l <= #1 1'b1;`
104	4	rudi	`else`
105			`if(!valid & !(ch_en & !full_empty_r & crdy & (!srs \| (srs & req) )) )`
106	10	rudi	`en_out_l <= #1 1'b0;`
107	4	rudi
108			`always @(posedge clk)`
109			`en_out_l2 <= #1 en_out_l & valid;`
110
111			`assign en_out = en_out_l & !en_out_l2 & valid;`
112
113			`endmodule`

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_fifo_ctrl.v] - Blame information for rev 17