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rudi |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE AC 97 Controller ////
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//// FIFO Control Module ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: ac97_fifo_ctrl.v,v 1.1 2001-08-03 06:54:49 rudi Exp $
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//
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// $Date: 2001-08-03 06:54:49 $
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// $Revision: 1.1 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
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// Initial Checkin
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//
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//
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//
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//
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`include "ac97_defines.v"
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module ac97_fifo_ctrl( clk,
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valid, ch_en, srs, full_empty, req, crdy,
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en_out, en_out_l
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);
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input clk;
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input valid;
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input ch_en; // Channel Enable
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input srs; // Sample Rate Select
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input full_empty; // Fifo Status
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input req; // Codec Request
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input crdy; // Codec Ready
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output en_out; // Output read/write pulse
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output en_out_l; // Latched Output
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg en_out_l, en_out_l2;
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reg full_empty_r;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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always @(posedge clk)
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if(!valid) full_empty_r <= #1 full_empty;
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always @(posedge clk)
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if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) )
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en_out_l <= #1 1;
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else
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if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) )
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en_out_l <= #1 0;
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always @(posedge clk)
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en_out_l2 <= #1 en_out_l & valid;
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assign en_out = en_out_l & !en_out_l2 & valid;
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endmodule
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