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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_in_fifo.v] - Blame information for rev 12

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Output FIFO                                                ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_in_fifo.v,v 1.3 2002-03-11 03:21:22 rudi Exp $
//
//  $Date: 2002-03-11 03:21:22 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2002/03/05 04:44:05  rudi
//
//               - Fixed the order of the thrash hold bits to match the spec.
//               - Many minor synthesis cleanup items ...
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:14  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
`ifdef AC97_IN_FIFO_DEPTH_4
 
// 4 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [19:0]   din;
input           we;
output  [31:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:3];
reg     [31:0]   dout;
 
reg     [3:0]    wp;
reg     [2:0]    rp;
 
wire    [3:0]    wp_p1;
 
reg     [1:0]    status;
reg     [15:0]   din_tmp1;
reg     [31:0]   din_tmp;
wire            m16b;
reg             full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 4'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);
 
always @(posedge clk)
        if(!en)         rp <= #1 3'h0;
        else
        if(re)          rp <= #1 rp + 3'h1;
 
always @(posedge clk)
        status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);
 
always @(posedge clk)
        empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
        full  <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]);
 
// Fifo Output
always @(posedge clk)
        dout <= #1 mem[ rp[1:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
        if(we & !wp[0])  din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
        case(mode)      // synopsys parallel_case full_case
           2'h0: din_tmp = {din[19:4], din_tmp1};       // 16 Bit Output
           2'h1: din_tmp = {13'h0, din[17:0]};           // 18 bit Output
           2'h2: din_tmp = {11'h0, din[19:0]};           // 20 Bit Output
        endcase
 
always @(posedge clk)
        if(we & (!m16b | (m16b & wp[0]) ) )      mem[ wp[2:1] ] <= #1 din_tmp;
 
endmodule
 
`endif
 
`ifdef AC97_IN_FIFO_DEPTH_8
 
// 8 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [19:0]   din;
input           we;
output  [31:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:7];
reg     [31:0]   dout;
 
reg     [4:0]    wp;
reg     [3:0]    rp;
 
wire    [4:0]    wp_p1;
 
reg     [1:0]    status;
reg     [15:0]   din_tmp1;
reg     [31:0]   din_tmp;
wire            m16b;
reg             full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 5'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2);
 
always @(posedge clk)
        if(!en)         rp <= #1 4'h0;
        else
        if(re)          rp <= #1 rp + 4'h1;
 
always @(posedge clk)
        status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1);
 
always @(posedge clk)
        empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
        full  <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]);
 
// Fifo Output
always @(posedge clk)
        dout <= #1 mem[ rp[2:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
        if(we & !wp[0])  din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
        case(mode)      // synopsys parallel_case full_case
           2'h0: din_tmp = {din[19:4], din_tmp1};       // 16 Bit Output
           2'h1: din_tmp = {13'h0, din[17:0]};           // 18 bit Output
           2'h2: din_tmp = {11'h0, din[19:0]};           // 20 Bit Output
        endcase
 
always @(posedge clk)
        if(we & (!m16b | (m16b & wp[0]) ) )      mem[ wp[3:1] ] <= #1 din_tmp;
 
endmodule
 
`endif
 
 
`ifdef AC97_IN_FIFO_DEPTH_16
 
// 16 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [19:0]   din;
input           we;
output  [31:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:15];
reg     [31:0]   dout;
 
reg     [5:0]    wp;
reg     [4:0]    rp;
 
wire    [5:0]    wp_p1;
 
reg     [1:0]    status;
reg     [15:0]   din_tmp1;
reg     [31:0]   din_tmp;
wire            m16b;
reg             full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 6'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2);
 
always @(posedge clk)
        if(!en)         rp <= #1 5'h0;
        else
        if(re)          rp <= #1 rp + 5'h1;
 
always @(posedge clk)
        status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1);
 
always @(posedge clk)
        empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
        full  <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]);
 
// Fifo Output
always @(posedge clk)
        dout <= #1 mem[ rp[3:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
        if(we & !wp[0])  din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
        case(mode)      // synopsys parallel_case full_case
           2'h0: din_tmp = {din[19:4], din_tmp1};       // 16 Bit Output
           2'h1: din_tmp = {13'h0, din[17:0]};           // 18 bit Output
           2'h2: din_tmp = {11'h0, din[19:0]};           // 20 Bit Output
        endcase
 
always @(posedge clk)
        if(we & (!m16b | (m16b & wp[0]) ) )      mem[ wp[4:1] ] <= #1 din_tmp;
 
endmodule
 
`endif

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_in_fifo.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Output FIFO ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	12	rudi	`// $Id: ac97_in_fifo.v,v 1.3 2002-03-11 03:21:22 rudi Exp $`
42	4	rudi	`//`
43	12	rudi	`// $Date: 2002-03-11 03:21:22 $`
44			`// $Revision: 1.3 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	12	rudi	`// Revision 1.2 2002/03/05 04:44:05 rudi`
52			`//`
53			`// - Fixed the order of the thrash hold bits to match the spec.`
54			`// - Many minor synthesis cleanup items ...`
55			`//`
56	10	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
57			`//`
58			`//`
59			`// - Changed to new directory structure`
60			`//`
61	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:14 rudi`
62			`// Initial Checkin`
63			`//`
64			`//`
65			`//`
66			`//`
67
68			`include "ac97_defines.v"
69
70	12	rudi	`ifdef AC97_IN_FIFO_DEPTH_4
71
72			`// 4 entry deep verion of the input FIFO`
73
74	4	rudi	`module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
75
76			`input clk, rst;`
77			`input en;`
78			`input [1:0] mode;`
79			`input [19:0] din;`
80			`input we;`
81			`output [31:0] dout;`
82			`input re;`
83			`output [1:0] status;`
84			`output full;`
85			`output empty;`
86
87
88			`////////////////////////////////////////////////////////////////////`
89			`//`
90			`// Local Wires`
91			`//`
92
93			`reg [31:0] mem[0:3];`
94			`reg [31:0] dout;`
95
96			`reg [3:0] wp;`
97			`reg [2:0] rp;`
98
99			`wire [3:0] wp_p1;`
100
101			`reg [1:0] status;`
102			`reg [15:0] din_tmp1;`
103			`reg [31:0] din_tmp;`
104			`wire m16b;`
105			`reg full, empty;`
106
107			`////////////////////////////////////////////////////////////////////`
108			`//`
109			`// Misc Logic`
110			`//`
111
112			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
113
114			`always @(posedge clk)`
115	10	rudi	`if(!en) wp <= #1 4'h0;`
116	4	rudi	`else`
117			`if(we) wp <= #1 wp_p1;`
118
119	10	rudi	`assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);`
120	4	rudi
121			`always @(posedge clk)`
122	10	rudi	`if(!en) rp <= #1 3'h0;`
123	4	rudi	`else`
124	10	rudi	`if(re) rp <= #1 rp + 3'h1;`
125	4	rudi
126			`always @(posedge clk)`
127	12	rudi	`status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);`
128	4	rudi
129			`always @(posedge clk)`
130			`empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);`
131
132			`always @(posedge clk)`
133			`full <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]);`
134
135			`// Fifo Output`
136			`always @(posedge clk)`
137			`dout <= #1 mem[ rp[1:0] ];`
138
139			`// Fifo Input Half Word Latch`
140			`always @(posedge clk)`
141			`if(we & !wp[0]) din_tmp1 <= #1 din[19:4];`
142
143			`always @(mode or din_tmp1 or din)`
144			`case(mode) // synopsys parallel_case full_case`
145	12	rudi	`2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output`
146			`2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output`
147			`2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output`
148	4	rudi	`endcase`
149
150			`always @(posedge clk)`
151			`if(we & (!m16b \| (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;`
152
153			`endmodule`
154	12	rudi
155			`endif
156
157			`ifdef AC97_IN_FIFO_DEPTH_8
158
159			`// 8 entry deep verion of the input FIFO`
160
161			`module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
162
163			`input clk, rst;`
164			`input en;`
165			`input [1:0] mode;`
166			`input [19:0] din;`
167			`input we;`
168			`output [31:0] dout;`
169			`input re;`
170			`output [1:0] status;`
171			`output full;`
172			`output empty;`
173
174
175			`////////////////////////////////////////////////////////////////////`
176			`//`
177			`// Local Wires`
178			`//`
179
180			`reg [31:0] mem[0:7];`
181			`reg [31:0] dout;`
182
183			`reg [4:0] wp;`
184			`reg [3:0] rp;`
185
186			`wire [4:0] wp_p1;`
187
188			`reg [1:0] status;`
189			`reg [15:0] din_tmp1;`
190			`reg [31:0] din_tmp;`
191			`wire m16b;`
192			`reg full, empty;`
193
194			`////////////////////////////////////////////////////////////////////`
195			`//`
196			`// Misc Logic`
197			`//`
198
199			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
200
201			`always @(posedge clk)`
202			`if(!en) wp <= #1 5'h0;`
203			`else`
204			`if(we) wp <= #1 wp_p1;`
205
206			`assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2);`
207
208			`always @(posedge clk)`
209			`if(!en) rp <= #1 4'h0;`
210			`else`
211			`if(re) rp <= #1 rp + 4'h1;`
212
213			`always @(posedge clk)`
214			`status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1);`
215
216			`always @(posedge clk)`
217			`empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0);`
218
219			`always @(posedge clk)`
220			`full <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]);`
221
222			`// Fifo Output`
223			`always @(posedge clk)`
224			`dout <= #1 mem[ rp[2:0] ];`
225
226			`// Fifo Input Half Word Latch`
227			`always @(posedge clk)`
228			`if(we & !wp[0]) din_tmp1 <= #1 din[19:4];`
229
230			`always @(mode or din_tmp1 or din)`
231			`case(mode) // synopsys parallel_case full_case`
232			`2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output`
233			`2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output`
234			`2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output`
235			`endcase`
236
237			`always @(posedge clk)`
238			`if(we & (!m16b \| (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp;`
239
240			`endmodule`
241
242			`endif
243
244
245			`ifdef AC97_IN_FIFO_DEPTH_16
246
247			`// 16 entry deep verion of the input FIFO`
248
249			`module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
250
251			`input clk, rst;`
252			`input en;`
253			`input [1:0] mode;`
254			`input [19:0] din;`
255			`input we;`
256			`output [31:0] dout;`
257			`input re;`
258			`output [1:0] status;`
259			`output full;`
260			`output empty;`
261
262
263			`////////////////////////////////////////////////////////////////////`
264			`//`
265			`// Local Wires`
266			`//`
267
268			`reg [31:0] mem[0:15];`
269			`reg [31:0] dout;`
270
271			`reg [5:0] wp;`
272			`reg [4:0] rp;`
273
274			`wire [5:0] wp_p1;`
275
276			`reg [1:0] status;`
277			`reg [15:0] din_tmp1;`
278			`reg [31:0] din_tmp;`
279			`wire m16b;`
280			`reg full, empty;`
281
282			`////////////////////////////////////////////////////////////////////`
283			`//`
284			`// Misc Logic`
285			`//`
286
287			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
288
289			`always @(posedge clk)`
290			`if(!en) wp <= #1 6'h0;`
291			`else`
292			`if(we) wp <= #1 wp_p1;`
293
294			`assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2);`
295
296			`always @(posedge clk)`
297			`if(!en) rp <= #1 5'h0;`
298			`else`
299			`if(re) rp <= #1 rp + 5'h1;`
300
301			`always @(posedge clk)`
302			`status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1);`
303
304			`always @(posedge clk)`
305			`empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0);`
306
307			`always @(posedge clk)`
308			`full <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]);`
309
310			`// Fifo Output`
311			`always @(posedge clk)`
312			`dout <= #1 mem[ rp[3:0] ];`
313
314			`// Fifo Input Half Word Latch`
315			`always @(posedge clk)`
316			`if(we & !wp[0]) din_tmp1 <= #1 din[19:4];`
317
318			`always @(mode or din_tmp1 or din)`
319			`case(mode) // synopsys parallel_case full_case`
320			`2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output`
321			`2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output`
322			`2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output`
323			`endcase`
324
325			`always @(posedge clk)`
326			`if(we & (!m16b \| (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp;`
327
328			`endmodule`
329
330			`endif