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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_in_fifo.v] - Blame information for rev 14

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Output FIFO                                                ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_in_fifo.v,v 1.4 2002-09-19 06:30:56 rudi Exp $
//
//  $Date: 2002-09-19 06:30:56 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2002/03/11 03:21:22  rudi
//
//               - Added defines to select fifo depth between 4, 8 and 16 entries.
//
//               Revision 1.2  2002/03/05 04:44:05  rudi
//
//               - Fixed the order of the thrash hold bits to match the spec.
//               - Many minor synthesis cleanup items ...
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:14  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
`ifdef AC97_IN_FIFO_DEPTH_4
 
// 4 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [19:0]   din;
input           we;
output  [31:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:3];
reg     [31:0]   dout;
 
reg     [3:0]    wp;
reg     [2:0]    rp;
 
wire    [3:0]    wp_p1;
 
reg     [1:0]    status;
reg     [15:0]   din_tmp1;
reg     [31:0]   din_tmp;
wire            m16b;
reg             full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 4'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);
 
always @(posedge clk)
        if(!en)         rp <= #1 3'h0;
        else
        if(re)          rp <= #1 rp + 3'h1;
 
always @(posedge clk)
        status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);
 
always @(posedge clk)
        empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
        full  <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]);
 
// Fifo Output
always @(posedge clk)
        dout <= #1 mem[ rp[1:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
        if(we & !wp[0])  din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
        case(mode)      // synopsys parallel_case full_case
           2'h0: din_tmp = {din[19:4], din_tmp1};       // 16 Bit Output
           2'h1: din_tmp = {13'h0, din[17:0]};           // 18 bit Output
           2'h2: din_tmp = {11'h0, din[19:0]};           // 20 Bit Output
        endcase
 
always @(posedge clk)
        if(we & (!m16b | (m16b & wp[0]) ) )      mem[ wp[2:1] ] <= #1 din_tmp;
 
endmodule
 
`endif
 
`ifdef AC97_IN_FIFO_DEPTH_8
 
// 8 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [19:0]   din;
input           we;
output  [31:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:7];
reg     [31:0]   dout;
 
reg     [4:0]    wp;
reg     [3:0]    rp;
 
wire    [4:0]    wp_p1;
 
reg     [1:0]    status;
reg     [15:0]   din_tmp1;
reg     [31:0]   din_tmp;
wire            m16b;
reg             full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 5'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2);
 
always @(posedge clk)
        if(!en)         rp <= #1 4'h0;
        else
        if(re)          rp <= #1 rp + 4'h1;
 
always @(posedge clk)
        status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1);
 
always @(posedge clk)
        empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
        full  <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]);
 
// Fifo Output
always @(posedge clk)
        dout <= #1 mem[ rp[2:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
        if(we & !wp[0])  din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
        case(mode)      // synopsys parallel_case full_case
           2'h0: din_tmp = {din[19:4], din_tmp1};       // 16 Bit Output
           2'h1: din_tmp = {13'h0, din[17:0]};           // 18 bit Output
           2'h2: din_tmp = {11'h0, din[19:0]};           // 20 Bit Output
        endcase
 
always @(posedge clk)
        if(we & (!m16b | (m16b & wp[0]) ) )      mem[ wp[3:1] ] <= #1 din_tmp;
 
endmodule
 
`endif
 
 
`ifdef AC97_IN_FIFO_DEPTH_16
 
// 16 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [19:0]   din;
input           we;
output  [31:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:15];
reg     [31:0]   dout;
 
reg     [5:0]    wp;
reg     [4:0]    rp;
 
wire    [5:0]    wp_p1;
 
reg     [1:0]    status;
reg     [15:0]   din_tmp1;
reg     [31:0]   din_tmp;
wire            m16b;
reg             full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 6'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2);
 
always @(posedge clk)
        if(!en)         rp <= #1 5'h0;
        else
        if(re)          rp <= #1 rp + 5'h1;
 
always @(posedge clk)
        status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1);
 
always @(posedge clk)
        empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
        full  <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]);
 
// Fifo Output
always @(posedge clk)
        dout <= #1 mem[ rp[3:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
        if(we & !wp[0])  din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
        case(mode)      // synopsys parallel_case full_case
           2'h0: din_tmp = {din[19:4], din_tmp1};       // 16 Bit Output
           2'h1: din_tmp = {13'h0, din[17:0]};           // 18 bit Output
           2'h2: din_tmp = {11'h0, din[19:0]};           // 20 Bit Output
        endcase
 
always @(posedge clk)
        if(we & (!m16b | (m16b & wp[0]) ) )      mem[ wp[4:1] ] <= #1 din_tmp;
 
endmodule
 
`endif

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_in_fifo.v] - Blame information for rev 14

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Output FIFO ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	14	rudi	`// $Id: ac97_in_fifo.v,v 1.4 2002-09-19 06:30:56 rudi Exp $`
43	4	rudi	`//`
44	14	rudi	`// $Date: 2002-09-19 06:30:56 $`
45			`// $Revision: 1.4 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	14	rudi	`// Revision 1.3 2002/03/11 03:21:22 rudi`
53			`//`
54			`// - Added defines to select fifo depth between 4, 8 and 16 entries.`
55			`//`
56	12	rudi	`// Revision 1.2 2002/03/05 04:44:05 rudi`
57			`//`
58			`// - Fixed the order of the thrash hold bits to match the spec.`
59			`// - Many minor synthesis cleanup items ...`
60			`//`
61	10	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
62			`//`
63			`//`
64			`// - Changed to new directory structure`
65			`//`
66	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:14 rudi`
67			`// Initial Checkin`
68			`//`
69			`//`
70			`//`
71			`//`
72
73			`include "ac97_defines.v"
74
75	12	rudi	`ifdef AC97_IN_FIFO_DEPTH_4
76
77			`// 4 entry deep verion of the input FIFO`
78
79	4	rudi	`module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
80
81			`input clk, rst;`
82			`input en;`
83			`input [1:0] mode;`
84			`input [19:0] din;`
85			`input we;`
86			`output [31:0] dout;`
87			`input re;`
88			`output [1:0] status;`
89			`output full;`
90			`output empty;`
91
92
93			`////////////////////////////////////////////////////////////////////`
94			`//`
95			`// Local Wires`
96			`//`
97
98			`reg [31:0] mem[0:3];`
99			`reg [31:0] dout;`
100
101			`reg [3:0] wp;`
102			`reg [2:0] rp;`
103
104			`wire [3:0] wp_p1;`
105
106			`reg [1:0] status;`
107			`reg [15:0] din_tmp1;`
108			`reg [31:0] din_tmp;`
109			`wire m16b;`
110			`reg full, empty;`
111
112			`////////////////////////////////////////////////////////////////////`
113			`//`
114			`// Misc Logic`
115			`//`
116
117			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
118
119			`always @(posedge clk)`
120	10	rudi	`if(!en) wp <= #1 4'h0;`
121	4	rudi	`else`
122			`if(we) wp <= #1 wp_p1;`
123
124	10	rudi	`assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);`
125	4	rudi
126			`always @(posedge clk)`
127	10	rudi	`if(!en) rp <= #1 3'h0;`
128	4	rudi	`else`
129	10	rudi	`if(re) rp <= #1 rp + 3'h1;`
130	4	rudi
131			`always @(posedge clk)`
132	12	rudi	`status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);`
133	4	rudi
134			`always @(posedge clk)`
135			`empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);`
136
137			`always @(posedge clk)`
138			`full <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]);`
139
140			`// Fifo Output`
141			`always @(posedge clk)`
142			`dout <= #1 mem[ rp[1:0] ];`
143
144			`// Fifo Input Half Word Latch`
145			`always @(posedge clk)`
146			`if(we & !wp[0]) din_tmp1 <= #1 din[19:4];`
147
148			`always @(mode or din_tmp1 or din)`
149			`case(mode) // synopsys parallel_case full_case`
150	12	rudi	`2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output`
151			`2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output`
152			`2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output`
153	4	rudi	`endcase`
154
155			`always @(posedge clk)`
156			`if(we & (!m16b \| (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;`
157
158			`endmodule`
159	12	rudi
160			`endif
161
162			`ifdef AC97_IN_FIFO_DEPTH_8
163
164			`// 8 entry deep verion of the input FIFO`
165
166			`module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
167
168			`input clk, rst;`
169			`input en;`
170			`input [1:0] mode;`
171			`input [19:0] din;`
172			`input we;`
173			`output [31:0] dout;`
174			`input re;`
175			`output [1:0] status;`
176			`output full;`
177			`output empty;`
178
179
180			`////////////////////////////////////////////////////////////////////`
181			`//`
182			`// Local Wires`
183			`//`
184
185			`reg [31:0] mem[0:7];`
186			`reg [31:0] dout;`
187
188			`reg [4:0] wp;`
189			`reg [3:0] rp;`
190
191			`wire [4:0] wp_p1;`
192
193			`reg [1:0] status;`
194			`reg [15:0] din_tmp1;`
195			`reg [31:0] din_tmp;`
196			`wire m16b;`
197			`reg full, empty;`
198
199			`////////////////////////////////////////////////////////////////////`
200			`//`
201			`// Misc Logic`
202			`//`
203
204			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
205
206			`always @(posedge clk)`
207			`if(!en) wp <= #1 5'h0;`
208			`else`
209			`if(we) wp <= #1 wp_p1;`
210
211			`assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2);`
212
213			`always @(posedge clk)`
214			`if(!en) rp <= #1 4'h0;`
215			`else`
216			`if(re) rp <= #1 rp + 4'h1;`
217
218			`always @(posedge clk)`
219			`status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1);`
220
221			`always @(posedge clk)`
222			`empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0);`
223
224			`always @(posedge clk)`
225			`full <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]);`
226
227			`// Fifo Output`
228			`always @(posedge clk)`
229			`dout <= #1 mem[ rp[2:0] ];`
230
231			`// Fifo Input Half Word Latch`
232			`always @(posedge clk)`
233			`if(we & !wp[0]) din_tmp1 <= #1 din[19:4];`
234
235			`always @(mode or din_tmp1 or din)`
236			`case(mode) // synopsys parallel_case full_case`
237			`2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output`
238			`2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output`
239			`2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output`
240			`endcase`
241
242			`always @(posedge clk)`
243			`if(we & (!m16b \| (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp;`
244
245			`endmodule`
246
247			`endif
248
249
250			`ifdef AC97_IN_FIFO_DEPTH_16
251
252			`// 16 entry deep verion of the input FIFO`
253
254			`module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
255
256			`input clk, rst;`
257			`input en;`
258			`input [1:0] mode;`
259			`input [19:0] din;`
260			`input we;`
261			`output [31:0] dout;`
262			`input re;`
263			`output [1:0] status;`
264			`output full;`
265			`output empty;`
266
267
268			`////////////////////////////////////////////////////////////////////`
269			`//`
270			`// Local Wires`
271			`//`
272
273			`reg [31:0] mem[0:15];`
274			`reg [31:0] dout;`
275
276			`reg [5:0] wp;`
277			`reg [4:0] rp;`
278
279			`wire [5:0] wp_p1;`
280
281			`reg [1:0] status;`
282			`reg [15:0] din_tmp1;`
283			`reg [31:0] din_tmp;`
284			`wire m16b;`
285			`reg full, empty;`
286
287			`////////////////////////////////////////////////////////////////////`
288			`//`
289			`// Misc Logic`
290			`//`
291
292			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
293
294			`always @(posedge clk)`
295			`if(!en) wp <= #1 6'h0;`
296			`else`
297			`if(we) wp <= #1 wp_p1;`
298
299			`assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2);`
300
301			`always @(posedge clk)`
302			`if(!en) rp <= #1 5'h0;`
303			`else`
304			`if(re) rp <= #1 rp + 5'h1;`
305
306			`always @(posedge clk)`
307			`status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1);`
308
309			`always @(posedge clk)`
310			`empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0);`
311
312			`always @(posedge clk)`
313			`full <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]);`
314
315			`// Fifo Output`
316			`always @(posedge clk)`
317			`dout <= #1 mem[ rp[3:0] ];`
318
319			`// Fifo Input Half Word Latch`
320			`always @(posedge clk)`
321			`if(we & !wp[0]) din_tmp1 <= #1 din[19:4];`
322
323			`always @(mode or din_tmp1 or din)`
324			`case(mode) // synopsys parallel_case full_case`
325			`2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output`
326			`2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output`
327			`2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output`
328			`endcase`
329
330			`always @(posedge clk)`
331			`if(we & (!m16b \| (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp;`
332
333			`endmodule`
334
335			`endif