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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_in_fifo.v] - Blame information for rev 16

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Output FIFO                                                ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_in_fifo.v,v 1.5 2002-11-14 17:10:12 rudi Exp $
//
//  $Date: 2002-11-14 17:10:12 $
//  $Revision: 1.5 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.4  2002/09/19 06:30:56  rudi
//               Fixed a bug reported by Igor. Apparently this bug only shows up when
//               the WB clock is very low (2x bit_clk). Updated Copyright header.
//
//               Revision 1.3  2002/03/11 03:21:22  rudi
//
//               - Added defines to select fifo depth between 4, 8 and 16 entries.
//
//               Revision 1.2  2002/03/05 04:44:05  rudi
//
//               - Fixed the order of the thrash hold bits to match the spec.
//               - Many minor synthesis cleanup items ...
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:14  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
`ifdef AC97_IN_FIFO_DEPTH_4
 
// 4 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [19:0]   din;
input           we;
output  [31:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:3];
reg     [31:0]   dout;
 
reg     [3:0]    wp;
reg     [2:0]    rp;
 
wire    [3:0]    wp_p1;
 
reg     [1:0]    status;
reg     [15:0]   din_tmp1;
reg     [31:0]   din_tmp;
wire            m16b;
reg             full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 4'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);
 
always @(posedge clk)
        if(!en)         rp <= #1 3'h0;
        else
        if(re)          rp <= #1 rp + 3'h1;
 
always @(posedge clk)
        status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);
 
always @(posedge clk)
        empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
        full  <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]);
 
// Fifo Output
always @(posedge clk)
        dout <= #1 mem[ rp[1:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
        if(we & !wp[0])  din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
        case(mode)      // synopsys parallel_case full_case
           2'h0: din_tmp = {din[19:4], din_tmp1};       // 16 Bit Output
           2'h1: din_tmp = {14'h0, din[19:2]};          // 18 bit Output
           2'h2: din_tmp = {11'h0, din[19:0]};           // 20 Bit Output
        endcase
 
always @(posedge clk)
        if(we & (!m16b | (m16b & wp[0]) ) )      mem[ wp[2:1] ] <= #1 din_tmp;
 
endmodule
 
`endif
 
`ifdef AC97_IN_FIFO_DEPTH_8
 
// 8 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [19:0]   din;
input           we;
output  [31:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:7];
reg     [31:0]   dout;
 
reg     [4:0]    wp;
reg     [3:0]    rp;
 
wire    [4:0]    wp_p1;
 
reg     [1:0]    status;
reg     [15:0]   din_tmp1;
reg     [31:0]   din_tmp;
wire            m16b;
reg             full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 5'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2);
 
always @(posedge clk)
        if(!en)         rp <= #1 4'h0;
        else
        if(re)          rp <= #1 rp + 4'h1;
 
always @(posedge clk)
        status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1);
 
always @(posedge clk)
        empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
        full  <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]);
 
// Fifo Output
always @(posedge clk)
        dout <= #1 mem[ rp[2:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
        if(we & !wp[0])  din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
        case(mode)      // synopsys parallel_case full_case
           2'h0: din_tmp = {din[19:4], din_tmp1};       // 16 Bit Output
           2'h1: din_tmp = {14'h0, din[19:2]};          // 18 bit Output
           2'h2: din_tmp = {11'h0, din[19:0]};           // 20 Bit Output
        endcase
 
always @(posedge clk)
        if(we & (!m16b | (m16b & wp[0]) ) )      mem[ wp[3:1] ] <= #1 din_tmp;
 
endmodule
 
`endif
 
 
`ifdef AC97_IN_FIFO_DEPTH_16
 
// 16 entry deep verion of the input FIFO
 
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [19:0]   din;
input           we;
output  [31:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:15];
reg     [31:0]   dout;
 
reg     [5:0]    wp;
reg     [4:0]    rp;
 
wire    [5:0]    wp_p1;
 
reg     [1:0]    status;
reg     [15:0]   din_tmp1;
reg     [31:0]   din_tmp;
wire            m16b;
reg             full, empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 6'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2);
 
always @(posedge clk)
        if(!en)         rp <= #1 5'h0;
        else
        if(re)          rp <= #1 rp + 5'h1;
 
always @(posedge clk)
        status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1);
 
always @(posedge clk)
        empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0);
 
always @(posedge clk)
        full  <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]);
 
// Fifo Output
always @(posedge clk)
        dout <= #1 mem[ rp[3:0] ];
 
// Fifo Input Half Word Latch
always @(posedge clk)
        if(we & !wp[0])  din_tmp1 <= #1 din[19:4];
 
always @(mode or din_tmp1 or din)
        case(mode)      // synopsys parallel_case full_case
           2'h0: din_tmp = {din[19:4], din_tmp1};       // 16 Bit Output
           2'h1: din_tmp = {14'h0, din[19:2]};          // 18 bit Output
           2'h2: din_tmp = {11'h0, din[19:0]};           // 20 Bit Output
        endcase
 
always @(posedge clk)
        if(we & (!m16b | (m16b & wp[0]) ) )      mem[ wp[4:1] ] <= #1 din_tmp;
 
endmodule
 
`endif

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_in_fifo.v] - Blame information for rev 16

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Output FIFO ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	16	rudi	`// $Id: ac97_in_fifo.v,v 1.5 2002-11-14 17:10:12 rudi Exp $`
43	4	rudi	`//`
44	16	rudi	`// $Date: 2002-11-14 17:10:12 $`
45			`// $Revision: 1.5 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	16	rudi	`// Revision 1.4 2002/09/19 06:30:56 rudi`
53			`// Fixed a bug reported by Igor. Apparently this bug only shows up when`
54			`// the WB clock is very low (2x bit_clk). Updated Copyright header.`
55			`//`
56	14	rudi	`// Revision 1.3 2002/03/11 03:21:22 rudi`
57			`//`
58			`// - Added defines to select fifo depth between 4, 8 and 16 entries.`
59			`//`
60	12	rudi	`// Revision 1.2 2002/03/05 04:44:05 rudi`
61			`//`
62			`// - Fixed the order of the thrash hold bits to match the spec.`
63			`// - Many minor synthesis cleanup items ...`
64			`//`
65	10	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
66			`//`
67			`//`
68			`// - Changed to new directory structure`
69			`//`
70	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:14 rudi`
71			`// Initial Checkin`
72			`//`
73			`//`
74			`//`
75			`//`
76
77			`include "ac97_defines.v"
78
79	12	rudi	`ifdef AC97_IN_FIFO_DEPTH_4
80
81			`// 4 entry deep verion of the input FIFO`
82
83	4	rudi	`module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
84
85			`input clk, rst;`
86			`input en;`
87			`input [1:0] mode;`
88			`input [19:0] din;`
89			`input we;`
90			`output [31:0] dout;`
91			`input re;`
92			`output [1:0] status;`
93			`output full;`
94			`output empty;`
95
96
97			`////////////////////////////////////////////////////////////////////`
98			`//`
99			`// Local Wires`
100			`//`
101
102			`reg [31:0] mem[0:3];`
103			`reg [31:0] dout;`
104
105			`reg [3:0] wp;`
106			`reg [2:0] rp;`
107
108			`wire [3:0] wp_p1;`
109
110			`reg [1:0] status;`
111			`reg [15:0] din_tmp1;`
112			`reg [31:0] din_tmp;`
113			`wire m16b;`
114			`reg full, empty;`
115
116			`////////////////////////////////////////////////////////////////////`
117			`//`
118			`// Misc Logic`
119			`//`
120
121			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
122
123			`always @(posedge clk)`
124	10	rudi	`if(!en) wp <= #1 4'h0;`
125	4	rudi	`else`
126			`if(we) wp <= #1 wp_p1;`
127
128	10	rudi	`assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);`
129	4	rudi
130			`always @(posedge clk)`
131	10	rudi	`if(!en) rp <= #1 3'h0;`
132	4	rudi	`else`
133	10	rudi	`if(re) rp <= #1 rp + 3'h1;`
134	4	rudi
135			`always @(posedge clk)`
136	12	rudi	`status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);`
137	4	rudi
138			`always @(posedge clk)`
139			`empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);`
140
141			`always @(posedge clk)`
142			`full <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]);`
143
144			`// Fifo Output`
145			`always @(posedge clk)`
146			`dout <= #1 mem[ rp[1:0] ];`
147
148			`// Fifo Input Half Word Latch`
149			`always @(posedge clk)`
150			`if(we & !wp[0]) din_tmp1 <= #1 din[19:4];`
151
152			`always @(mode or din_tmp1 or din)`
153			`case(mode) // synopsys parallel_case full_case`
154	12	rudi	`2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output`
155	16	rudi	`2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output`
156	12	rudi	`2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output`
157	4	rudi	`endcase`
158
159			`always @(posedge clk)`
160			`if(we & (!m16b \| (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;`
161
162			`endmodule`
163	12	rudi
164			`endif
165
166			`ifdef AC97_IN_FIFO_DEPTH_8
167
168			`// 8 entry deep verion of the input FIFO`
169
170			`module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
171
172			`input clk, rst;`
173			`input en;`
174			`input [1:0] mode;`
175			`input [19:0] din;`
176			`input we;`
177			`output [31:0] dout;`
178			`input re;`
179			`output [1:0] status;`
180			`output full;`
181			`output empty;`
182
183
184			`////////////////////////////////////////////////////////////////////`
185			`//`
186			`// Local Wires`
187			`//`
188
189			`reg [31:0] mem[0:7];`
190			`reg [31:0] dout;`
191
192			`reg [4:0] wp;`
193			`reg [3:0] rp;`
194
195			`wire [4:0] wp_p1;`
196
197			`reg [1:0] status;`
198			`reg [15:0] din_tmp1;`
199			`reg [31:0] din_tmp;`
200			`wire m16b;`
201			`reg full, empty;`
202
203			`////////////////////////////////////////////////////////////////////`
204			`//`
205			`// Misc Logic`
206			`//`
207
208			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
209
210			`always @(posedge clk)`
211			`if(!en) wp <= #1 5'h0;`
212			`else`
213			`if(we) wp <= #1 wp_p1;`
214
215			`assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2);`
216
217			`always @(posedge clk)`
218			`if(!en) rp <= #1 4'h0;`
219			`else`
220			`if(re) rp <= #1 rp + 4'h1;`
221
222			`always @(posedge clk)`
223			`status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1);`
224
225			`always @(posedge clk)`
226			`empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0);`
227
228			`always @(posedge clk)`
229			`full <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]);`
230
231			`// Fifo Output`
232			`always @(posedge clk)`
233			`dout <= #1 mem[ rp[2:0] ];`
234
235			`// Fifo Input Half Word Latch`
236			`always @(posedge clk)`
237			`if(we & !wp[0]) din_tmp1 <= #1 din[19:4];`
238
239			`always @(mode or din_tmp1 or din)`
240			`case(mode) // synopsys parallel_case full_case`
241			`2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output`
242	16	rudi	`2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output`
243	12	rudi	`2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output`
244			`endcase`
245
246			`always @(posedge clk)`
247			`if(we & (!m16b \| (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp;`
248
249			`endmodule`
250
251			`endif
252
253
254			`ifdef AC97_IN_FIFO_DEPTH_16
255
256			`// 16 entry deep verion of the input FIFO`
257
258			`module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
259
260			`input clk, rst;`
261			`input en;`
262			`input [1:0] mode;`
263			`input [19:0] din;`
264			`input we;`
265			`output [31:0] dout;`
266			`input re;`
267			`output [1:0] status;`
268			`output full;`
269			`output empty;`
270
271
272			`////////////////////////////////////////////////////////////////////`
273			`//`
274			`// Local Wires`
275			`//`
276
277			`reg [31:0] mem[0:15];`
278			`reg [31:0] dout;`
279
280			`reg [5:0] wp;`
281			`reg [4:0] rp;`
282
283			`wire [5:0] wp_p1;`
284
285			`reg [1:0] status;`
286			`reg [15:0] din_tmp1;`
287			`reg [31:0] din_tmp;`
288			`wire m16b;`
289			`reg full, empty;`
290
291			`////////////////////////////////////////////////////////////////////`
292			`//`
293			`// Misc Logic`
294			`//`
295
296			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
297
298			`always @(posedge clk)`
299			`if(!en) wp <= #1 6'h0;`
300			`else`
301			`if(we) wp <= #1 wp_p1;`
302
303			`assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2);`
304
305			`always @(posedge clk)`
306			`if(!en) rp <= #1 5'h0;`
307			`else`
308			`if(re) rp <= #1 rp + 5'h1;`
309
310			`always @(posedge clk)`
311			`status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1);`
312
313			`always @(posedge clk)`
314			`empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0);`
315
316			`always @(posedge clk)`
317			`full <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]);`
318
319			`// Fifo Output`
320			`always @(posedge clk)`
321			`dout <= #1 mem[ rp[3:0] ];`
322
323			`// Fifo Input Half Word Latch`
324			`always @(posedge clk)`
325			`if(we & !wp[0]) din_tmp1 <= #1 din[19:4];`
326
327			`always @(mode or din_tmp1 or din)`
328			`case(mode) // synopsys parallel_case full_case`
329			`2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output`
330	16	rudi	`2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output`
331	12	rudi	`2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output`
332			`endcase`
333
334			`always @(posedge clk)`
335			`if(we & (!m16b \| (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp;`
336
337			`endmodule`
338
339			`endif