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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_int.v] - Blame information for rev 10

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Interrupt Logic                                            ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_int.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
//  $Date: 2002-03-05 04:44:05 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:18  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_int(clk, rst,
 
                // Register File Interface
                int_set,
 
                // FIFO Interface
                cfg, status, full_empty, full, empty, re, we
                );
 
input           clk, rst;
output  [2:0]    int_set;
 
input   [7:0]    cfg;
input   [1:0]    status;
input           full_empty, full, empty, re, we;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [2:0]    int_set;
 
////////////////////////////////////////////////////////////////////
//
// Interrupt Logic
//
 
always @(posedge clk or negedge rst)
        if(!rst)        int_set[0] <= #1 1'b0;
        else
        case(cfg[5:4])  // synopsys parallel_case full_case
                        // 1/4 full/empty
           2'h2: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'h0));
                        // 1/2 full/empty
           2'h1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'h0));
                        // 3/4 full/empty
           2'h0: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'h3));
           2'h3: int_set[0] <= #1 cfg[0] & full_empty;
        endcase
 
always @(posedge clk or negedge rst)
        if(!rst)        int_set[1] <= #1 1'b0;
        else
        if(empty & re)  int_set[1] <= #1 1'b1;
 
always @(posedge clk or negedge rst)
        if(!rst)        int_set[2] <= #1 1'b0;
        else
        if(full & we)   int_set[2] <= #1 1'b1;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Interrupt Logic ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	10	rudi	`// $Id: ac97_int.v,v 1.2 2002-03-05 04:44:05 rudi Exp $`
42	4	rudi	`//`
43	10	rudi	`// $Date: 2002-03-05 04:44:05 $`
44			`// $Revision: 1.2 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	10	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
52			`//`
53			`//`
54			`// - Changed to new directory structure`
55			`//`
56	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:18 rudi`
57			`// Initial Checkin`
58			`//`
59			`//`
60			`//`
61			`//`
62
63			`include "ac97_defines.v"
64
65			`module ac97_int(clk, rst,`
66
67			`// Register File Interface`
68			`int_set,`
69
70			`// FIFO Interface`
71			`cfg, status, full_empty, full, empty, re, we`
72			`);`
73
74			`input clk, rst;`
75			`output [2:0] int_set;`
76
77			`input [7:0] cfg;`
78			`input [1:0] status;`
79			`input full_empty, full, empty, re, we;`
80
81			`////////////////////////////////////////////////////////////////////`
82			`//`
83			`// Local Wires`
84			`//`
85
86			`reg [2:0] int_set;`
87
88			`////////////////////////////////////////////////////////////////////`
89			`//`
90			`// Interrupt Logic`
91			`//`
92
93			`always @(posedge clk or negedge rst)`
94	10	rudi	`if(!rst) int_set[0] <= #1 1'b0;`
95	4	rudi	`else`
96			`case(cfg[5:4]) // synopsys parallel_case full_case`
97			`// 1/4 full/empty`
98	10	rudi	`2'h2: int_set[0] <= #1 cfg[0] & (full_empty \| (status == 2'h0));`
99	4	rudi	`// 1/2 full/empty`
100	10	rudi	`2'h1: int_set[0] <= #1 cfg[0] & (full_empty \| (status[1] == 1'h0));`
101	4	rudi	`// 3/4 full/empty`
102	10	rudi	`2'h0: int_set[0] <= #1 cfg[0] & (full_empty \| (status < 2'h3));`
103			`2'h3: int_set[0] <= #1 cfg[0] & full_empty;`
104	4	rudi	`endcase`
105
106			`always @(posedge clk or negedge rst)`
107	10	rudi	`if(!rst) int_set[1] <= #1 1'b0;`
108	4	rudi	`else`
109	10	rudi	`if(empty & re) int_set[1] <= #1 1'b1;`
110	4	rudi
111			`always @(posedge clk or negedge rst)`
112	10	rudi	`if(!rst) int_set[2] <= #1 1'b0;`
113	4	rudi	`else`
114	10	rudi	`if(full & we) int_set[2] <= #1 1'b1;`
115	4	rudi
116			`endmodule`

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_int.v] - Blame information for rev 10