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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_out_fifo.v] - Blame information for rev 12

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Output FIFO                                                ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_out_fifo.v,v 1.3 2002-03-11 03:21:22 rudi Exp $
//
//  $Date: 2002-03-11 03:21:22 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:16  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
`ifdef AC97_OUT_FIFO_DEPTH_4
 
// 4 Entry Deep version of the Output FIFO
 
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [31:0]   din;
input           we;
output  [19:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:3];
 
reg     [2:0]    wp;
reg     [3:0]    rp;
 
wire    [2:0]    wp_p1;
 
reg     [1:0]    status;
reg     [19:0]   dout;
wire    [31:0]   dout_tmp;
wire    [15:0]   dout_tmp1;
wire            m16b;
reg             empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 3'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = wp + 3'h1;
 
always @(posedge clk)
        if(!en)         rp <= #1 4'h0;
        else
        if(re & m16b)   rp <= #1 rp + 4'h1;
        else
        if(re & !m16b)  rp <= #1 rp + 4'h2;
 
always @(posedge clk)
        status <= #1 (wp[1:0] - rp[2:1]) - 2'h1;
 
wire    [3:0]    rp_p1 = rp[3:0] + 4'h1;
 
always @(posedge clk)
        empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1);
 
assign full  = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]);
 
// Fifo Output
assign dout_tmp = mem[ rp[2:1] ];
 
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
 
always @(posedge clk)
        if(!en)         dout <= #1 20'h0;
        else
        if(re)
                case(mode)      // synopsys parallel_case full_case
                   2'h0: dout <= #1 {dout_tmp1, 4'h0};          // 16 Bit Output
                   2'h1: dout <= #1 {dout_tmp[17:0], 2'h0};      // 18 bit Output
                   2'h2: dout <= #1 dout_tmp[19:0];              // 20 Bit Output
                endcase
 
always @(posedge clk)
        if(we)  mem[wp[1:0]] <= #1 din;
 
endmodule
 
`endif
 
`ifdef AC97_OUT_FIFO_DEPTH_8
 
// 8 Entry Deep version of the Output FIFO
 
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [31:0]   din;
input           we;
output  [19:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:7];
 
reg     [3:0]    wp;
reg     [4:0]    rp;
 
wire    [3:0]    wp_p1;
 
reg     [1:0]    status;
reg     [19:0]   dout;
wire    [31:0]   dout_tmp;
wire    [15:0]   dout_tmp1;
wire            m16b;
reg             empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 4'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = wp + 4'h1;
 
always @(posedge clk)
        if(!en)         rp <= #1 5'h0;
        else
        if(re & m16b)   rp <= #1 rp + 5'h1;
        else
        if(re & !m16b)  rp <= #1 rp + 5'h2;
 
always @(posedge clk)
        status <= #1 (wp[2:1] - rp[3:2]) - 2'h1;
 
wire    [4:0]    rp_p1 = rp[4:0] + 5'h1;
 
always @(posedge clk)
        empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1);
 
assign full  = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]);
 
// Fifo Output
assign dout_tmp = mem[ rp[3:1] ];
 
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
 
always @(posedge clk)
        if(!en)         dout <= #1 20'h0;
        else
        if(re)
                case(mode)      // synopsys parallel_case full_case
                   2'h0: dout <= #1 {dout_tmp1, 4'h0};          // 16 Bit Output
                   2'h1: dout <= #1 {dout_tmp[17:0], 2'h0};      // 18 bit Output
                   2'h2: dout <= #1 dout_tmp[19:0];              // 20 Bit Output
                endcase
 
 
always @(posedge clk)
        if(we)  mem[wp[2:0]] <= #1 din;
 
endmodule
 
`endif
 
 
`ifdef AC97_OUT_FIFO_DEPTH_16
 
// 16 Entry Deep version of the Output FIFO
 
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [31:0]   din;
input           we;
output  [19:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:15];
 
reg     [4:0]    wp;
reg     [5:0]    rp;
 
wire    [4:0]    wp_p1;
 
reg     [1:0]    status;
reg     [19:0]   dout;
wire    [31:0]   dout_tmp;
wire    [15:0]   dout_tmp1;
wire            m16b;
reg             empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 5'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = wp + 4'h1;
 
always @(posedge clk)
        if(!en)         rp <= #1 6'h0;
        else
        if(re & m16b)   rp <= #1 rp + 6'h1;
        else
        if(re & !m16b)  rp <= #1 rp + 6'h2;
 
always @(posedge clk)
        status <= #1 (wp[3:2] - rp[4:3]) - 2'h1;
 
wire    [5:0]    rp_p1 = rp[5:0] + 6'h1;
 
always @(posedge clk)
        empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1);
 
assign full  = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]);
 
// Fifo Output
assign dout_tmp = mem[ rp[4:1] ];
 
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
 
always @(posedge clk)
        if(!en)         dout <= #1 20'h0;
        else
        if(re)
                case(mode)      // synopsys parallel_case full_case
                   2'h0: dout <= #1 {dout_tmp1, 4'h0};          // 16 Bit Output
                   2'h1: dout <= #1 {dout_tmp[17:0], 2'h0};      // 18 bit Output
                   2'h2: dout <= #1 dout_tmp[19:0];              // 20 Bit Output
                endcase
 
 
always @(posedge clk)
        if(we)  mem[wp[3:0]] <= #1 din;
 
endmodule
 
`endif

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_out_fifo.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Output FIFO ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	12	rudi	`// $Id: ac97_out_fifo.v,v 1.3 2002-03-11 03:21:22 rudi Exp $`
42	4	rudi	`//`
43	12	rudi	`// $Date: 2002-03-11 03:21:22 $`
44			`// $Revision: 1.3 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	10	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
52			`//`
53			`//`
54			`// - Changed to new directory structure`
55			`//`
56	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:16 rudi`
57			`// Initial Checkin`
58			`//`
59			`//`
60			`//`
61			`//`
62
63			`include "ac97_defines.v"
64
65	12	rudi	`ifdef AC97_OUT_FIFO_DEPTH_4
66
67			`// 4 Entry Deep version of the Output FIFO`
68
69	4	rudi	`module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
70
71			`input clk, rst;`
72			`input en;`
73			`input [1:0] mode;`
74			`input [31:0] din;`
75			`input we;`
76			`output [19:0] dout;`
77			`input re;`
78			`output [1:0] status;`
79			`output full;`
80			`output empty;`
81
82
83			`////////////////////////////////////////////////////////////////////`
84			`//`
85			`// Local Wires`
86			`//`
87
88			`reg [31:0] mem[0:3];`
89
90			`reg [2:0] wp;`
91			`reg [3:0] rp;`
92
93			`wire [2:0] wp_p1;`
94
95			`reg [1:0] status;`
96			`reg [19:0] dout;`
97			`wire [31:0] dout_tmp;`
98			`wire [15:0] dout_tmp1;`
99			`wire m16b;`
100			`reg empty;`
101
102			`////////////////////////////////////////////////////////////////////`
103			`//`
104			`// Misc Logic`
105			`//`
106
107			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
108
109			`always @(posedge clk)`
110	10	rudi	`if(!en) wp <= #1 3'h0;`
111	4	rudi	`else`
112			`if(we) wp <= #1 wp_p1;`
113
114	10	rudi	`assign wp_p1 = wp + 3'h1;`
115	4	rudi
116			`always @(posedge clk)`
117	10	rudi	`if(!en) rp <= #1 4'h0;`
118	4	rudi	`else`
119	10	rudi	`if(re & m16b) rp <= #1 rp + 4'h1;`
120	4	rudi	`else`
121	10	rudi	`if(re & !m16b) rp <= #1 rp + 4'h2;`
122	4	rudi
123			`always @(posedge clk)`
124	10	rudi	`status <= #1 (wp[1:0] - rp[2:1]) - 2'h1;`
125	4	rudi
126	10	rudi	`wire [3:0] rp_p1 = rp[3:0] + 4'h1;`
127	4	rudi
128			`always @(posedge clk)`
129			`empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1);`
130
131			`assign full = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]);`
132
133			`// Fifo Output`
134			`assign dout_tmp = mem[ rp[2:1] ];`
135
136			`// Fifo Output Half Word Select`
137			`assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];`
138
139			`always @(posedge clk)`
140			`if(!en) dout <= #1 20'h0;`
141			`else`
142			`if(re)`
143			`case(mode) // synopsys parallel_case full_case`
144	12	rudi	`2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output`
145			`2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output`
146			`2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output`
147	4	rudi	`endcase`
148
149			`always @(posedge clk)`
150			`if(we) mem[wp[1:0]] <= #1 din;`
151
152			`endmodule`
153	10	rudi
154	12	rudi	`endif
155
156			`ifdef AC97_OUT_FIFO_DEPTH_8
157
158			`// 8 Entry Deep version of the Output FIFO`
159
160			`module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
161
162			`input clk, rst;`
163			`input en;`
164			`input [1:0] mode;`
165			`input [31:0] din;`
166			`input we;`
167			`output [19:0] dout;`
168			`input re;`
169			`output [1:0] status;`
170			`output full;`
171			`output empty;`
172
173
174			`////////////////////////////////////////////////////////////////////`
175			`//`
176			`// Local Wires`
177			`//`
178
179			`reg [31:0] mem[0:7];`
180
181			`reg [3:0] wp;`
182			`reg [4:0] rp;`
183
184			`wire [3:0] wp_p1;`
185
186			`reg [1:0] status;`
187			`reg [19:0] dout;`
188			`wire [31:0] dout_tmp;`
189			`wire [15:0] dout_tmp1;`
190			`wire m16b;`
191			`reg empty;`
192
193			`////////////////////////////////////////////////////////////////////`
194			`//`
195			`// Misc Logic`
196			`//`
197
198			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
199
200			`always @(posedge clk)`
201			`if(!en) wp <= #1 4'h0;`
202			`else`
203			`if(we) wp <= #1 wp_p1;`
204
205			`assign wp_p1 = wp + 4'h1;`
206
207			`always @(posedge clk)`
208			`if(!en) rp <= #1 5'h0;`
209			`else`
210			`if(re & m16b) rp <= #1 rp + 5'h1;`
211			`else`
212			`if(re & !m16b) rp <= #1 rp + 5'h2;`
213
214			`always @(posedge clk)`
215			`status <= #1 (wp[2:1] - rp[3:2]) - 2'h1;`
216
217			`wire [4:0] rp_p1 = rp[4:0] + 5'h1;`
218
219			`always @(posedge clk)`
220			`empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1);`
221
222			`assign full = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]);`
223
224			`// Fifo Output`
225			`assign dout_tmp = mem[ rp[3:1] ];`
226
227			`// Fifo Output Half Word Select`
228			`assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];`
229
230			`always @(posedge clk)`
231			`if(!en) dout <= #1 20'h0;`
232			`else`
233			`if(re)`
234			`case(mode) // synopsys parallel_case full_case`
235			`2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output`
236			`2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output`
237			`2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output`
238			`endcase`
239
240
241			`always @(posedge clk)`
242			`if(we) mem[wp[2:0]] <= #1 din;`
243
244			`endmodule`
245
246			`endif
247
248
249			`ifdef AC97_OUT_FIFO_DEPTH_16
250
251			`// 16 Entry Deep version of the Output FIFO`
252
253			`module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
254
255			`input clk, rst;`
256			`input en;`
257			`input [1:0] mode;`
258			`input [31:0] din;`
259			`input we;`
260			`output [19:0] dout;`
261			`input re;`
262			`output [1:0] status;`
263			`output full;`
264			`output empty;`
265
266
267			`////////////////////////////////////////////////////////////////////`
268			`//`
269			`// Local Wires`
270			`//`
271
272			`reg [31:0] mem[0:15];`
273
274			`reg [4:0] wp;`
275			`reg [5:0] rp;`
276
277			`wire [4:0] wp_p1;`
278
279			`reg [1:0] status;`
280			`reg [19:0] dout;`
281			`wire [31:0] dout_tmp;`
282			`wire [15:0] dout_tmp1;`
283			`wire m16b;`
284			`reg empty;`
285
286			`////////////////////////////////////////////////////////////////////`
287			`//`
288			`// Misc Logic`
289			`//`
290
291			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
292
293			`always @(posedge clk)`
294			`if(!en) wp <= #1 5'h0;`
295			`else`
296			`if(we) wp <= #1 wp_p1;`
297
298			`assign wp_p1 = wp + 4'h1;`
299
300			`always @(posedge clk)`
301			`if(!en) rp <= #1 6'h0;`
302			`else`
303			`if(re & m16b) rp <= #1 rp + 6'h1;`
304			`else`
305			`if(re & !m16b) rp <= #1 rp + 6'h2;`
306
307			`always @(posedge clk)`
308			`status <= #1 (wp[3:2] - rp[4:3]) - 2'h1;`
309
310			`wire [5:0] rp_p1 = rp[5:0] + 6'h1;`
311
312			`always @(posedge clk)`
313			`empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1);`
314
315			`assign full = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]);`
316
317			`// Fifo Output`
318			`assign dout_tmp = mem[ rp[4:1] ];`
319
320			`// Fifo Output Half Word Select`
321			`assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];`
322
323			`always @(posedge clk)`
324			`if(!en) dout <= #1 20'h0;`
325			`else`
326			`if(re)`
327			`case(mode) // synopsys parallel_case full_case`
328			`2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output`
329			`2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output`
330			`2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output`
331			`endcase`
332
333
334			`always @(posedge clk)`
335			`if(we) mem[wp[3:0]] <= #1 din;`
336
337			`endmodule`
338
339			`endif