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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_out_fifo.v] - Blame information for rev 14

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Output FIFO                                                ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_out_fifo.v,v 1.4 2002-09-19 06:30:56 rudi Exp $
//
//  $Date: 2002-09-19 06:30:56 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2002/03/11 03:21:22  rudi
//
//               - Added defines to select fifo depth between 4, 8 and 16 entries.
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:16  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
`ifdef AC97_OUT_FIFO_DEPTH_4
 
// 4 Entry Deep version of the Output FIFO
 
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [31:0]   din;
input           we;
output  [19:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:3];
 
reg     [2:0]    wp;
reg     [3:0]    rp;
 
wire    [2:0]    wp_p1;
 
reg     [1:0]    status;
reg     [19:0]   dout;
wire    [31:0]   dout_tmp;
wire    [15:0]   dout_tmp1;
wire            m16b;
reg             empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 3'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = wp + 3'h1;
 
always @(posedge clk)
        if(!en)         rp <= #1 4'h0;
        else
        if(re & m16b)   rp <= #1 rp + 4'h1;
        else
        if(re & !m16b)  rp <= #1 rp + 4'h2;
 
always @(posedge clk)
        status <= #1 (wp[1:0] - rp[2:1]) - 2'h1;
 
wire    [3:0]    rp_p1 = rp[3:0] + 4'h1;
 
always @(posedge clk)
        empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1);
 
assign full  = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]);
 
// Fifo Output
assign dout_tmp = mem[ rp[2:1] ];
 
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
 
always @(posedge clk)
        if(!en)         dout <= #1 20'h0;
        else
        if(re)
                case(mode)      // synopsys parallel_case full_case
                   2'h0: dout <= #1 {dout_tmp1, 4'h0};          // 16 Bit Output
                   2'h1: dout <= #1 {dout_tmp[17:0], 2'h0};      // 18 bit Output
                   2'h2: dout <= #1 dout_tmp[19:0];              // 20 Bit Output
                endcase
 
always @(posedge clk)
        if(we)  mem[wp[1:0]] <= #1 din;
 
endmodule
 
`endif
 
`ifdef AC97_OUT_FIFO_DEPTH_8
 
// 8 Entry Deep version of the Output FIFO
 
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [31:0]   din;
input           we;
output  [19:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:7];
 
reg     [3:0]    wp;
reg     [4:0]    rp;
 
wire    [3:0]    wp_p1;
 
reg     [1:0]    status;
reg     [19:0]   dout;
wire    [31:0]   dout_tmp;
wire    [15:0]   dout_tmp1;
wire            m16b;
reg             empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 4'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = wp + 4'h1;
 
always @(posedge clk)
        if(!en)         rp <= #1 5'h0;
        else
        if(re & m16b)   rp <= #1 rp + 5'h1;
        else
        if(re & !m16b)  rp <= #1 rp + 5'h2;
 
always @(posedge clk)
        status <= #1 (wp[2:1] - rp[3:2]) - 2'h1;
 
wire    [4:0]    rp_p1 = rp[4:0] + 5'h1;
 
always @(posedge clk)
        empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1);
 
assign full  = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]);
 
// Fifo Output
assign dout_tmp = mem[ rp[3:1] ];
 
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
 
always @(posedge clk)
        if(!en)         dout <= #1 20'h0;
        else
        if(re)
                case(mode)      // synopsys parallel_case full_case
                   2'h0: dout <= #1 {dout_tmp1, 4'h0};          // 16 Bit Output
                   2'h1: dout <= #1 {dout_tmp[17:0], 2'h0};      // 18 bit Output
                   2'h2: dout <= #1 dout_tmp[19:0];              // 20 Bit Output
                endcase
 
 
always @(posedge clk)
        if(we)  mem[wp[2:0]] <= #1 din;
 
endmodule
 
`endif
 
 
`ifdef AC97_OUT_FIFO_DEPTH_16
 
// 16 Entry Deep version of the Output FIFO
 
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
 
input           clk, rst;
input           en;
input   [1:0]    mode;
input   [31:0]   din;
input           we;
output  [19:0]   dout;
input           re;
output  [1:0]    status;
output          full;
output          empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   mem[0:15];
 
reg     [4:0]    wp;
reg     [5:0]    rp;
 
wire    [4:0]    wp_p1;
 
reg     [1:0]    status;
reg     [19:0]   dout;
wire    [31:0]   dout_tmp;
wire    [15:0]   dout_tmp1;
wire            m16b;
reg             empty;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign m16b = (mode == 2'h0);   // 16 Bit Mode
 
always @(posedge clk)
        if(!en)         wp <= #1 5'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = wp + 4'h1;
 
always @(posedge clk)
        if(!en)         rp <= #1 6'h0;
        else
        if(re & m16b)   rp <= #1 rp + 6'h1;
        else
        if(re & !m16b)  rp <= #1 rp + 6'h2;
 
always @(posedge clk)
        status <= #1 (wp[3:2] - rp[4:3]) - 2'h1;
 
wire    [5:0]    rp_p1 = rp[5:0] + 6'h1;
 
always @(posedge clk)
        empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1);
 
assign full  = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]);
 
// Fifo Output
assign dout_tmp = mem[ rp[4:1] ];
 
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
 
always @(posedge clk)
        if(!en)         dout <= #1 20'h0;
        else
        if(re)
                case(mode)      // synopsys parallel_case full_case
                   2'h0: dout <= #1 {dout_tmp1, 4'h0};          // 16 Bit Output
                   2'h1: dout <= #1 {dout_tmp[17:0], 2'h0};      // 18 bit Output
                   2'h2: dout <= #1 dout_tmp[19:0];              // 20 Bit Output
                endcase
 
 
always @(posedge clk)
        if(we)  mem[wp[3:0]] <= #1 din;
 
endmodule
 
`endif

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_out_fifo.v] - Blame information for rev 14

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Output FIFO ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	14	rudi	`// $Id: ac97_out_fifo.v,v 1.4 2002-09-19 06:30:56 rudi Exp $`
43	4	rudi	`//`
44	14	rudi	`// $Date: 2002-09-19 06:30:56 $`
45			`// $Revision: 1.4 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	14	rudi	`// Revision 1.3 2002/03/11 03:21:22 rudi`
53			`//`
54			`// - Added defines to select fifo depth between 4, 8 and 16 entries.`
55			`//`
56	10	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
57			`//`
58			`//`
59			`// - Changed to new directory structure`
60			`//`
61	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:16 rudi`
62			`// Initial Checkin`
63			`//`
64			`//`
65			`//`
66			`//`
67
68			`include "ac97_defines.v"
69
70	12	rudi	`ifdef AC97_OUT_FIFO_DEPTH_4
71
72			`// 4 Entry Deep version of the Output FIFO`
73
74	4	rudi	`module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
75
76			`input clk, rst;`
77			`input en;`
78			`input [1:0] mode;`
79			`input [31:0] din;`
80			`input we;`
81			`output [19:0] dout;`
82			`input re;`
83			`output [1:0] status;`
84			`output full;`
85			`output empty;`
86
87
88			`////////////////////////////////////////////////////////////////////`
89			`//`
90			`// Local Wires`
91			`//`
92
93			`reg [31:0] mem[0:3];`
94
95			`reg [2:0] wp;`
96			`reg [3:0] rp;`
97
98			`wire [2:0] wp_p1;`
99
100			`reg [1:0] status;`
101			`reg [19:0] dout;`
102			`wire [31:0] dout_tmp;`
103			`wire [15:0] dout_tmp1;`
104			`wire m16b;`
105			`reg empty;`
106
107			`////////////////////////////////////////////////////////////////////`
108			`//`
109			`// Misc Logic`
110			`//`
111
112			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
113
114			`always @(posedge clk)`
115	10	rudi	`if(!en) wp <= #1 3'h0;`
116	4	rudi	`else`
117			`if(we) wp <= #1 wp_p1;`
118
119	10	rudi	`assign wp_p1 = wp + 3'h1;`
120	4	rudi
121			`always @(posedge clk)`
122	10	rudi	`if(!en) rp <= #1 4'h0;`
123	4	rudi	`else`
124	10	rudi	`if(re & m16b) rp <= #1 rp + 4'h1;`
125	4	rudi	`else`
126	10	rudi	`if(re & !m16b) rp <= #1 rp + 4'h2;`
127	4	rudi
128			`always @(posedge clk)`
129	10	rudi	`status <= #1 (wp[1:0] - rp[2:1]) - 2'h1;`
130	4	rudi
131	10	rudi	`wire [3:0] rp_p1 = rp[3:0] + 4'h1;`
132	4	rudi
133			`always @(posedge clk)`
134			`empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1);`
135
136			`assign full = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]);`
137
138			`// Fifo Output`
139			`assign dout_tmp = mem[ rp[2:1] ];`
140
141			`// Fifo Output Half Word Select`
142			`assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];`
143
144			`always @(posedge clk)`
145			`if(!en) dout <= #1 20'h0;`
146			`else`
147			`if(re)`
148			`case(mode) // synopsys parallel_case full_case`
149	12	rudi	`2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output`
150			`2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output`
151			`2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output`
152	4	rudi	`endcase`
153
154			`always @(posedge clk)`
155			`if(we) mem[wp[1:0]] <= #1 din;`
156
157			`endmodule`
158	10	rudi
159	12	rudi	`endif
160
161			`ifdef AC97_OUT_FIFO_DEPTH_8
162
163			`// 8 Entry Deep version of the Output FIFO`
164
165			`module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
166
167			`input clk, rst;`
168			`input en;`
169			`input [1:0] mode;`
170			`input [31:0] din;`
171			`input we;`
172			`output [19:0] dout;`
173			`input re;`
174			`output [1:0] status;`
175			`output full;`
176			`output empty;`
177
178
179			`////////////////////////////////////////////////////////////////////`
180			`//`
181			`// Local Wires`
182			`//`
183
184			`reg [31:0] mem[0:7];`
185
186			`reg [3:0] wp;`
187			`reg [4:0] rp;`
188
189			`wire [3:0] wp_p1;`
190
191			`reg [1:0] status;`
192			`reg [19:0] dout;`
193			`wire [31:0] dout_tmp;`
194			`wire [15:0] dout_tmp1;`
195			`wire m16b;`
196			`reg empty;`
197
198			`////////////////////////////////////////////////////////////////////`
199			`//`
200			`// Misc Logic`
201			`//`
202
203			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
204
205			`always @(posedge clk)`
206			`if(!en) wp <= #1 4'h0;`
207			`else`
208			`if(we) wp <= #1 wp_p1;`
209
210			`assign wp_p1 = wp + 4'h1;`
211
212			`always @(posedge clk)`
213			`if(!en) rp <= #1 5'h0;`
214			`else`
215			`if(re & m16b) rp <= #1 rp + 5'h1;`
216			`else`
217			`if(re & !m16b) rp <= #1 rp + 5'h2;`
218
219			`always @(posedge clk)`
220			`status <= #1 (wp[2:1] - rp[3:2]) - 2'h1;`
221
222			`wire [4:0] rp_p1 = rp[4:0] + 5'h1;`
223
224			`always @(posedge clk)`
225			`empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1);`
226
227			`assign full = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]);`
228
229			`// Fifo Output`
230			`assign dout_tmp = mem[ rp[3:1] ];`
231
232			`// Fifo Output Half Word Select`
233			`assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];`
234
235			`always @(posedge clk)`
236			`if(!en) dout <= #1 20'h0;`
237			`else`
238			`if(re)`
239			`case(mode) // synopsys parallel_case full_case`
240			`2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output`
241			`2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output`
242			`2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output`
243			`endcase`
244
245
246			`always @(posedge clk)`
247			`if(we) mem[wp[2:0]] <= #1 din;`
248
249			`endmodule`
250
251			`endif
252
253
254			`ifdef AC97_OUT_FIFO_DEPTH_16
255
256			`// 16 Entry Deep version of the Output FIFO`
257
258			`module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);`
259
260			`input clk, rst;`
261			`input en;`
262			`input [1:0] mode;`
263			`input [31:0] din;`
264			`input we;`
265			`output [19:0] dout;`
266			`input re;`
267			`output [1:0] status;`
268			`output full;`
269			`output empty;`
270
271
272			`////////////////////////////////////////////////////////////////////`
273			`//`
274			`// Local Wires`
275			`//`
276
277			`reg [31:0] mem[0:15];`
278
279			`reg [4:0] wp;`
280			`reg [5:0] rp;`
281
282			`wire [4:0] wp_p1;`
283
284			`reg [1:0] status;`
285			`reg [19:0] dout;`
286			`wire [31:0] dout_tmp;`
287			`wire [15:0] dout_tmp1;`
288			`wire m16b;`
289			`reg empty;`
290
291			`////////////////////////////////////////////////////////////////////`
292			`//`
293			`// Misc Logic`
294			`//`
295
296			`assign m16b = (mode == 2'h0); // 16 Bit Mode`
297
298			`always @(posedge clk)`
299			`if(!en) wp <= #1 5'h0;`
300			`else`
301			`if(we) wp <= #1 wp_p1;`
302
303			`assign wp_p1 = wp + 4'h1;`
304
305			`always @(posedge clk)`
306			`if(!en) rp <= #1 6'h0;`
307			`else`
308			`if(re & m16b) rp <= #1 rp + 6'h1;`
309			`else`
310			`if(re & !m16b) rp <= #1 rp + 6'h2;`
311
312			`always @(posedge clk)`
313			`status <= #1 (wp[3:2] - rp[4:3]) - 2'h1;`
314
315			`wire [5:0] rp_p1 = rp[5:0] + 6'h1;`
316
317			`always @(posedge clk)`
318			`empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1);`
319
320			`assign full = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]);`
321
322			`// Fifo Output`
323			`assign dout_tmp = mem[ rp[4:1] ];`
324
325			`// Fifo Output Half Word Select`
326			`assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];`
327
328			`always @(posedge clk)`
329			`if(!en) dout <= #1 20'h0;`
330			`else`
331			`if(re)`
332			`case(mode) // synopsys parallel_case full_case`
333			`2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output`
334			`2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output`
335			`2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output`
336			`endcase`
337
338
339			`always @(posedge clk)`
340			`if(we) mem[wp[3:0]] <= #1 din;`
341
342			`endmodule`
343
344			`endif