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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  PCM Request Controller                                     ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_prc.v,v 1.4 2002-09-19 06:30:56 rudi Exp $
//
//  $Date: 2002-09-19 06:30:56 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2002/03/05 04:44:05  rudi
//
//               - Fixed the order of the thrash hold bits to match the spec.
//               - Many minor synthesis cleanup items ...
//
//               Revision 1.2  2001/08/10 08:09:42  rudi
//
//               - Removed RTY_O output.
//               - Added Clock and Reset Inputs to documentation.
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:17  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_prc(clk, rst,
 
                // SR Slot Interface
                valid, in_valid, out_slt0,
                in_slt0, in_slt1,
 
                // Codec Register Access
                crac_valid, crac_wr,
 
                // Channel Configuration
                oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
                ic0_cfg, ic1_cfg, ic2_cfg,
 
                // FIFO Status
                o3_empty, o4_empty, o6_empty, o7_empty, o8_empty,
                o9_empty, i3_full, i4_full, i6_full,
 
                // FIFO Control
                o3_re, o4_re, o6_re, o7_re, o8_re, o9_re,
                i3_we, i4_we, i6_we
 
        );
input           clk, rst;
 
input           valid;
input   [2:0]    in_valid;
output  [15:0]   out_slt0;
input   [15:0]   in_slt0;
input   [19:0]   in_slt1;
 
input           crac_valid;
input           crac_wr;
 
input   [7:0]    oc0_cfg;
input   [7:0]    oc1_cfg;
input   [7:0]    oc2_cfg;
input   [7:0]    oc3_cfg;
input   [7:0]    oc4_cfg;
input   [7:0]    oc5_cfg;
 
input   [7:0]    ic0_cfg;
input   [7:0]    ic1_cfg;
input   [7:0]    ic2_cfg;
 
input           o3_empty;
input           o4_empty;
input           o6_empty;
input           o7_empty;
input           o8_empty;
input           o9_empty;
input           i3_full;
input           i4_full;
input           i6_full;
 
output          o3_re;
output          o4_re;
output          o6_re;
output          o7_re;
output          o8_re;
output          o9_re;
output          i3_we;
output          i4_we;
output          i6_we;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
wire            o3_re_l;
wire            o4_re_l;
wire            o6_re_l;
wire            o7_re_l;
wire            o8_re_l;
wire            o9_re_l;
 
reg             crac_valid_r;
reg             crac_wr_r;
 
////////////////////////////////////////////////////////////////////
//
// Output Tag Assembly
//
 
assign out_slt0[15] = |out_slt0[14:6];
 
assign out_slt0[14] = crac_valid_r;
assign out_slt0[13] = crac_wr_r;
 
assign out_slt0[12] = o3_re_l;
assign out_slt0[11] = o4_re_l;
assign out_slt0[10] = 1'b0;
assign out_slt0[09] = o6_re_l;
assign out_slt0[08] = o7_re_l;
assign out_slt0[07] = o8_re_l;
assign out_slt0[06] = o9_re_l;
assign out_slt0[5:0] = 6'h0;
 
////////////////////////////////////////////////////////////////////
//
// FIFO Control
//
 
always @(posedge clk)
        if(valid)       crac_valid_r <= #1 crac_valid;
 
always @(posedge clk)
        if(valid)       crac_wr_r <= #1 crac_valid & crac_wr;
 
// Output Channel 0 (Out Slot 3)
ac97_fifo_ctrl u0(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc0_cfg[0]       ),
                .srs(           oc0_cfg[1]      ),
                .full_empty(    o3_empty        ),
                .req(           ~in_slt1[11]    ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o3_re           ),
                .en_out_l(      o3_re_l         )
                );
 
// Output Channel 1 (Out Slot 4)
ac97_fifo_ctrl u1(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc1_cfg[0]       ),
                .srs(           oc1_cfg[1]      ),
                .full_empty(    o4_empty        ),
                .req(           ~in_slt1[10]    ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o4_re           ),
                .en_out_l(      o4_re_l         )
                );
 
`ifdef AC97_CENTER
// Output Channel 2 (Out Slot 6)
ac97_fifo_ctrl u2(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc2_cfg[0]       ),
                .srs(           oc2_cfg[1]      ),
                .full_empty(    o6_empty        ),
                .req(           ~in_slt1[8]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o6_re           ),
                .en_out_l(      o6_re_l         )
                );
`else
assign o6_re = 1'b0;
assign o6_re_l = 1'b0;
`endif
 
`ifdef AC97_SURROUND
// Output Channel 3 (Out Slot 7)
ac97_fifo_ctrl u3(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc3_cfg[0]       ),
                .srs(           oc3_cfg[1]      ),
                .full_empty(    o7_empty        ),
                .req(           ~in_slt1[7]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o7_re           ),
                .en_out_l(      o7_re_l         )
                );
 
// Output Channel 4 (Out Slot 8)
ac97_fifo_ctrl u4(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc4_cfg[0]       ),
                .srs(           oc4_cfg[1]      ),
                .full_empty(    o8_empty        ),
                .req(           ~in_slt1[6]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o8_re           ),
                .en_out_l(      o8_re_l         )
                );
`else
assign o7_re = 1'b0;
assign o7_re_l = 1'b0;
assign o8_re = 1'b0;
assign o8_re_l = 1'b0;
`endif
 
`ifdef AC97_LFE
// Output Channel 5 (Out Slot 9)
ac97_fifo_ctrl u5(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc5_cfg[0]       ),
                .srs(           oc5_cfg[1]      ),
                .full_empty(    o9_empty        ),
                .req(           ~in_slt1[5]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o9_re           ),
                .en_out_l(      o9_re_l         )
                );
`else
assign o9_re = 1'b0;
assign o9_re_l = 1'b0;
`endif
 
`ifdef AC97_SIN
// Input Channel 0 (In Slot 3)
ac97_fifo_ctrl u6(
                .clk(           clk             ),
                .valid(         in_valid[0]      ),
                .ch_en(         ic0_cfg[0]       ),
                .srs(           ic0_cfg[1]      ),
                .full_empty(    i3_full         ),
                .req(           in_slt0[12]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        i3_we           ),
                .en_out_l(                      )
                );
 
// Input Channel 1 (In Slot 4)
ac97_fifo_ctrl u7(
                .clk(           clk             ),
                .valid(         in_valid[1]     ),
                .ch_en(         ic1_cfg[0]       ),
                .srs(           ic1_cfg[1]      ),
                .full_empty(    i4_full         ),
                .req(           in_slt0[11]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        i4_we           ),
                .en_out_l(                      )
                );
`else
assign i3_we = 1'b0;
assign i4_we = 1'b0;
`endif
 
`ifdef AC97_MICIN
// Input Channel 2 (In Slot 6)
ac97_fifo_ctrl u8(
                .clk(           clk             ),
                .valid(         in_valid[2]     ),
                .ch_en(         ic2_cfg[0]       ),
                .srs(           ic2_cfg[1]      ),
                .full_empty(    i6_full         ),
                .req(           in_slt0[9]      ),
                .crdy(          in_slt0[15]     ),
                .en_out(        i6_we           ),
                .en_out_l(                      )
                );
`else
assign i6_we = 1'b0;
`endif
 
endmodule
 
 

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// PCM Request Controller ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	14	rudi	`// $Id: ac97_prc.v,v 1.4 2002-09-19 06:30:56 rudi Exp $`
43	4	rudi	`//`
44	14	rudi	`// $Date: 2002-09-19 06:30:56 $`
45			`// $Revision: 1.4 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	14	rudi	`// Revision 1.3 2002/03/05 04:44:05 rudi`
53			`//`
54			`// - Fixed the order of the thrash hold bits to match the spec.`
55			`// - Many minor synthesis cleanup items ...`
56			`//`
57	10	rudi	`// Revision 1.2 2001/08/10 08:09:42 rudi`
58			`//`
59			`// - Removed RTY_O output.`
60			`// - Added Clock and Reset Inputs to documentation.`
61			`// - Changed IO names to be more clear.`
62			`// - Uniquifyed define names to be core specific.`
63			`//`
64	6	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
65			`//`
66			`//`
67			`// - Changed to new directory structure`
68			`//`
69	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:17 rudi`
70			`// Initial Checkin`
71			`//`
72			`//`
73			`//`
74			`//`
75
76			`include "ac97_defines.v"
77
78			`module ac97_prc(clk, rst,`
79
80			`// SR Slot Interface`
81			`valid, in_valid, out_slt0,`
82			`in_slt0, in_slt1,`
83
84			`// Codec Register Access`
85			`crac_valid, crac_wr,`
86
87			`// Channel Configuration`
88			`oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,`
89			`ic0_cfg, ic1_cfg, ic2_cfg,`
90
91			`// FIFO Status`
92			`o3_empty, o4_empty, o6_empty, o7_empty, o8_empty,`
93			`o9_empty, i3_full, i4_full, i6_full,`
94
95			`// FIFO Control`
96			`o3_re, o4_re, o6_re, o7_re, o8_re, o9_re,`
97			`i3_we, i4_we, i6_we`
98
99			`);`
100			`input clk, rst;`
101
102			`input valid;`
103			`input [2:0] in_valid;`
104			`output [15:0] out_slt0;`
105			`input [15:0] in_slt0;`
106			`input [19:0] in_slt1;`
107
108			`input crac_valid;`
109			`input crac_wr;`
110
111			`input [7:0] oc0_cfg;`
112			`input [7:0] oc1_cfg;`
113			`input [7:0] oc2_cfg;`
114			`input [7:0] oc3_cfg;`
115			`input [7:0] oc4_cfg;`
116			`input [7:0] oc5_cfg;`
117
118			`input [7:0] ic0_cfg;`
119			`input [7:0] ic1_cfg;`
120			`input [7:0] ic2_cfg;`
121
122			`input o3_empty;`
123			`input o4_empty;`
124			`input o6_empty;`
125			`input o7_empty;`
126			`input o8_empty;`
127			`input o9_empty;`
128			`input i3_full;`
129			`input i4_full;`
130			`input i6_full;`
131
132			`output o3_re;`
133			`output o4_re;`
134			`output o6_re;`
135			`output o7_re;`
136			`output o8_re;`
137			`output o9_re;`
138			`output i3_we;`
139			`output i4_we;`
140			`output i6_we;`
141
142			`////////////////////////////////////////////////////////////////////`
143			`//`
144			`// Local Wires`
145			`//`
146
147			`wire o3_re_l;`
148			`wire o4_re_l;`
149			`wire o6_re_l;`
150			`wire o7_re_l;`
151			`wire o8_re_l;`
152			`wire o9_re_l;`
153
154			`reg crac_valid_r;`
155			`reg crac_wr_r;`
156
157			`////////////////////////////////////////////////////////////////////`
158			`//`
159			`// Output Tag Assembly`
160			`//`
161
162			`assign out_slt0[15] = \|out_slt0[14:6];`
163
164			`assign out_slt0[14] = crac_valid_r;`
165			`assign out_slt0[13] = crac_wr_r;`
166
167			`assign out_slt0[12] = o3_re_l;`
168			`assign out_slt0[11] = o4_re_l;`
169	10	rudi	`assign out_slt0[10] = 1'b0;`
170	4	rudi	`assign out_slt0[09] = o6_re_l;`
171			`assign out_slt0[08] = o7_re_l;`
172			`assign out_slt0[07] = o8_re_l;`
173			`assign out_slt0[06] = o9_re_l;`
174			`assign out_slt0[5:0] = 6'h0;`
175
176			`////////////////////////////////////////////////////////////////////`
177			`//`
178			`// FIFO Control`
179			`//`
180
181			`always @(posedge clk)`
182			`if(valid) crac_valid_r <= #1 crac_valid;`
183
184			`always @(posedge clk)`
185			`if(valid) crac_wr_r <= #1 crac_valid & crac_wr;`
186
187			`// Output Channel 0 (Out Slot 3)`
188			`ac97_fifo_ctrl u0(`
189			`.clk( clk ),`
190			`.valid( valid ),`
191			`.ch_en( oc0_cfg[0] ),`
192			`.srs( oc0_cfg[1] ),`
193			`.full_empty( o3_empty ),`
194			`.req( ~in_slt1[11] ),`
195			`.crdy( in_slt0[15] ),`
196			`.en_out( o3_re ),`
197			`.en_out_l( o3_re_l )`
198			`);`
199
200			`// Output Channel 1 (Out Slot 4)`
201			`ac97_fifo_ctrl u1(`
202			`.clk( clk ),`
203			`.valid( valid ),`
204			`.ch_en( oc1_cfg[0] ),`
205			`.srs( oc1_cfg[1] ),`
206			`.full_empty( o4_empty ),`
207			`.req( ~in_slt1[10] ),`
208			`.crdy( in_slt0[15] ),`
209			`.en_out( o4_re ),`
210			`.en_out_l( o4_re_l )`
211			`);`
212
213	6	rudi	`ifdef AC97_CENTER
214	4	rudi	`// Output Channel 2 (Out Slot 6)`
215			`ac97_fifo_ctrl u2(`
216			`.clk( clk ),`
217			`.valid( valid ),`
218			`.ch_en( oc2_cfg[0] ),`
219			`.srs( oc2_cfg[1] ),`
220			`.full_empty( o6_empty ),`
221			`.req( ~in_slt1[8] ),`
222			`.crdy( in_slt0[15] ),`
223			`.en_out( o6_re ),`
224			`.en_out_l( o6_re_l )`
225			`);`
226			`else
227	10	rudi	`assign o6_re = 1'b0;`
228			`assign o6_re_l = 1'b0;`
229	4	rudi	`endif
230
231	6	rudi	`ifdef AC97_SURROUND
232	4	rudi	`// Output Channel 3 (Out Slot 7)`
233			`ac97_fifo_ctrl u3(`
234			`.clk( clk ),`
235			`.valid( valid ),`
236			`.ch_en( oc3_cfg[0] ),`
237			`.srs( oc3_cfg[1] ),`
238			`.full_empty( o7_empty ),`
239			`.req( ~in_slt1[7] ),`
240			`.crdy( in_slt0[15] ),`
241			`.en_out( o7_re ),`
242			`.en_out_l( o7_re_l )`
243			`);`
244
245			`// Output Channel 4 (Out Slot 8)`
246			`ac97_fifo_ctrl u4(`
247			`.clk( clk ),`
248			`.valid( valid ),`
249			`.ch_en( oc4_cfg[0] ),`
250			`.srs( oc4_cfg[1] ),`
251			`.full_empty( o8_empty ),`
252			`.req( ~in_slt1[6] ),`
253			`.crdy( in_slt0[15] ),`
254			`.en_out( o8_re ),`
255			`.en_out_l( o8_re_l )`
256			`);`
257			`else
258	10	rudi	`assign o7_re = 1'b0;`
259			`assign o7_re_l = 1'b0;`
260			`assign o8_re = 1'b0;`
261			`assign o8_re_l = 1'b0;`
262	4	rudi	`endif
263
264	6	rudi	`ifdef AC97_LFE
265	4	rudi	`// Output Channel 5 (Out Slot 9)`
266			`ac97_fifo_ctrl u5(`
267			`.clk( clk ),`
268			`.valid( valid ),`
269			`.ch_en( oc5_cfg[0] ),`
270			`.srs( oc5_cfg[1] ),`
271			`.full_empty( o9_empty ),`
272			`.req( ~in_slt1[5] ),`
273			`.crdy( in_slt0[15] ),`
274			`.en_out( o9_re ),`
275			`.en_out_l( o9_re_l )`
276			`);`
277			`else
278	10	rudi	`assign o9_re = 1'b0;`
279			`assign o9_re_l = 1'b0;`
280	4	rudi	`endif
281
282	6	rudi	`ifdef AC97_SIN
283	4	rudi	`// Input Channel 0 (In Slot 3)`
284			`ac97_fifo_ctrl u6(`
285			`.clk( clk ),`
286			`.valid( in_valid[0] ),`
287			`.ch_en( ic0_cfg[0] ),`
288			`.srs( ic0_cfg[1] ),`
289			`.full_empty( i3_full ),`
290			`.req( in_slt0[12] ),`
291			`.crdy( in_slt0[15] ),`
292			`.en_out( i3_we ),`
293			`.en_out_l( )`
294			`);`
295
296			`// Input Channel 1 (In Slot 4)`
297			`ac97_fifo_ctrl u7(`
298			`.clk( clk ),`
299			`.valid( in_valid[1] ),`
300			`.ch_en( ic1_cfg[0] ),`
301			`.srs( ic1_cfg[1] ),`
302			`.full_empty( i4_full ),`
303			`.req( in_slt0[11] ),`
304			`.crdy( in_slt0[15] ),`
305			`.en_out( i4_we ),`
306			`.en_out_l( )`
307			`);`
308			`else
309	10	rudi	`assign i3_we = 1'b0;`
310			`assign i4_we = 1'b0;`
311	4	rudi	`endif
312
313	6	rudi	`ifdef AC97_MICIN
314	4	rudi	`// Input Channel 2 (In Slot 6)`
315			`ac97_fifo_ctrl u8(`
316			`.clk( clk ),`
317			`.valid( in_valid[2] ),`
318			`.ch_en( ic2_cfg[0] ),`
319			`.srs( ic2_cfg[1] ),`
320			`.full_empty( i6_full ),`
321			`.req( in_slt0[9] ),`
322			`.crdy( in_slt0[15] ),`
323			`.en_out( i6_we ),`
324			`.en_out_l( )`
325			`);`
326			`else
327	10	rudi	`assign i6_we = 1'b0;`
328	4	rudi	`endif
329
330			`endmodule`
331
332

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