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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_prc.v] - Blame information for rev 4

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1 4 rudi
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE AC 97 Controller                                  ////
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////  PCM Request Controller                                     ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2001 Rudolf Usselmann                         ////
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////                    rudi@asics.ws                            ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: ac97_prc.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
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//
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//  $Date: 2001-08-03 06:54:50 $
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//  $Revision: 1.1 $
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//  $Author: rudi $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.1.1.1  2001/05/19 02:29:17  rudi
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//               Initial Checkin
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//
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//
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//
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//
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`include "ac97_defines.v"
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module ac97_prc(clk, rst,
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                // SR Slot Interface
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                valid, in_valid, out_slt0,
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                in_slt0, in_slt1,
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                // Codec Register Access
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                crac_valid, crac_wr,
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                // Channel Configuration
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                oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
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                ic0_cfg, ic1_cfg, ic2_cfg,
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                // FIFO Status
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                o3_empty, o4_empty, o6_empty, o7_empty, o8_empty,
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                o9_empty, i3_full, i4_full, i6_full,
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                // FIFO Control
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                o3_re, o4_re, o6_re, o7_re, o8_re, o9_re,
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                i3_we, i4_we, i6_we
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        );
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input           clk, rst;
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input           valid;
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input   [2:0]    in_valid;
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output  [15:0]   out_slt0;
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input   [15:0]   in_slt0;
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input   [19:0]   in_slt1;
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input           crac_valid;
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input           crac_wr;
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input   [7:0]    oc0_cfg;
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input   [7:0]    oc1_cfg;
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input   [7:0]    oc2_cfg;
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input   [7:0]    oc3_cfg;
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input   [7:0]    oc4_cfg;
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input   [7:0]    oc5_cfg;
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input   [7:0]    ic0_cfg;
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input   [7:0]    ic1_cfg;
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input   [7:0]    ic2_cfg;
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input           o3_empty;
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input           o4_empty;
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input           o6_empty;
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input           o7_empty;
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input           o8_empty;
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input           o9_empty;
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input           i3_full;
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input           i4_full;
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input           i6_full;
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output          o3_re;
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output          o4_re;
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output          o6_re;
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output          o7_re;
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output          o8_re;
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output          o9_re;
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output          i3_we;
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output          i4_we;
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output          i6_we;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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wire            o3_re_l;
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wire            o4_re_l;
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wire            o6_re_l;
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wire            o7_re_l;
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wire            o8_re_l;
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wire            o9_re_l;
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reg             crac_valid_r;
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reg             crac_wr_r;
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////////////////////////////////////////////////////////////////////
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//
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// Output Tag Assembly
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//
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assign out_slt0[15] = |out_slt0[14:6];
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assign out_slt0[14] = crac_valid_r;
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assign out_slt0[13] = crac_wr_r;
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assign out_slt0[12] = o3_re_l;
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assign out_slt0[11] = o4_re_l;
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assign out_slt0[10] = 0;
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assign out_slt0[09] = o6_re_l;
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assign out_slt0[08] = o7_re_l;
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assign out_slt0[07] = o8_re_l;
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assign out_slt0[06] = o9_re_l;
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assign out_slt0[5:0] = 6'h0;
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////////////////////////////////////////////////////////////////////
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//
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// FIFO Control
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//
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always @(posedge clk)
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        if(valid)       crac_valid_r <= #1 crac_valid;
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always @(posedge clk)
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        if(valid)       crac_wr_r <= #1 crac_valid & crac_wr;
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// Output Channel 0 (Out Slot 3)
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ac97_fifo_ctrl u0(
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                .clk(           clk             ),
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                .valid(         valid           ),
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                .ch_en(         oc0_cfg[0]       ),
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                .srs(           oc0_cfg[1]      ),
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                .full_empty(    o3_empty        ),
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                .req(           ~in_slt1[11]    ),
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                .crdy(          in_slt0[15]     ),
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                .en_out(        o3_re           ),
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                .en_out_l(      o3_re_l         )
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                );
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// Output Channel 1 (Out Slot 4)
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ac97_fifo_ctrl u1(
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                .clk(           clk             ),
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                .valid(         valid           ),
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                .ch_en(         oc1_cfg[0]       ),
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                .srs(           oc1_cfg[1]      ),
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                .full_empty(    o4_empty        ),
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                .req(           ~in_slt1[10]    ),
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                .crdy(          in_slt0[15]     ),
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                .en_out(        o4_re           ),
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                .en_out_l(      o4_re_l         )
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                );
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`ifdef CENTER
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// Output Channel 2 (Out Slot 6)
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ac97_fifo_ctrl u2(
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                .clk(           clk             ),
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                .valid(         valid           ),
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                .ch_en(         oc2_cfg[0]       ),
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                .srs(           oc2_cfg[1]      ),
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                .full_empty(    o6_empty        ),
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                .req(           ~in_slt1[8]     ),
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                .crdy(          in_slt0[15]     ),
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                .en_out(        o6_re           ),
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                .en_out_l(      o6_re_l         )
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                );
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`else
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assign o6_re = 0;
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assign o6_re_l = 0;
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`endif
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`ifdef SURROUND
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// Output Channel 3 (Out Slot 7)
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ac97_fifo_ctrl u3(
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                .clk(           clk             ),
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                .valid(         valid           ),
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                .ch_en(         oc3_cfg[0]       ),
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                .srs(           oc3_cfg[1]      ),
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                .full_empty(    o7_empty        ),
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                .req(           ~in_slt1[7]     ),
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                .crdy(          in_slt0[15]     ),
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                .en_out(        o7_re           ),
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                .en_out_l(      o7_re_l         )
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                );
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// Output Channel 4 (Out Slot 8)
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ac97_fifo_ctrl u4(
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                .clk(           clk             ),
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                .valid(         valid           ),
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                .ch_en(         oc4_cfg[0]       ),
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                .srs(           oc4_cfg[1]      ),
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                .full_empty(    o8_empty        ),
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                .req(           ~in_slt1[6]     ),
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                .crdy(          in_slt0[15]     ),
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                .en_out(        o8_re           ),
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                .en_out_l(      o8_re_l         )
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                );
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`else
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assign o7_re = 0;
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assign o7_re_l = 0;
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assign o8_re = 0;
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assign o8_re_l = 0;
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`endif
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`ifdef LFE
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// Output Channel 5 (Out Slot 9)
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ac97_fifo_ctrl u5(
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                .clk(           clk             ),
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                .valid(         valid           ),
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                .ch_en(         oc5_cfg[0]       ),
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                .srs(           oc5_cfg[1]      ),
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                .full_empty(    o9_empty        ),
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                .req(           ~in_slt1[5]     ),
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                .crdy(          in_slt0[15]     ),
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                .en_out(        o9_re           ),
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                .en_out_l(      o9_re_l         )
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                );
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`else
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assign o9_re = 0;
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assign o9_re_l = 0;
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`endif
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`ifdef SIN
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// Input Channel 0 (In Slot 3)
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ac97_fifo_ctrl u6(
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                .clk(           clk             ),
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                .valid(         in_valid[0]      ),
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                .ch_en(         ic0_cfg[0]       ),
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                .srs(           ic0_cfg[1]      ),
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                .full_empty(    i3_full         ),
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                .req(           in_slt0[12]     ),
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                .crdy(          in_slt0[15]     ),
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                .en_out(        i3_we           ),
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                .en_out_l(                      )
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                );
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// Input Channel 1 (In Slot 4)
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ac97_fifo_ctrl u7(
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                .clk(           clk             ),
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                .valid(         in_valid[1]     ),
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                .ch_en(         ic1_cfg[0]       ),
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                .srs(           ic1_cfg[1]      ),
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                .full_empty(    i4_full         ),
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                .req(           in_slt0[11]     ),
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                .crdy(          in_slt0[15]     ),
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                .en_out(        i4_we           ),
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                .en_out_l(                      )
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                );
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`else
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assign i3_we = 0;
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assign i4_we = 0;
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`endif
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`ifdef MICIN
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// Input Channel 2 (In Slot 6)
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ac97_fifo_ctrl u8(
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                .clk(           clk             ),
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                .valid(         in_valid[2]     ),
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                .ch_en(         ic2_cfg[0]       ),
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                .srs(           ic2_cfg[1]      ),
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                .full_empty(    i6_full         ),
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                .req(           in_slt0[9]      ),
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                .crdy(          in_slt0[15]     ),
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                .en_out(        i6_we           ),
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                .en_out_l(                      )
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                );
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`else
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assign i6_we = 0;
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`endif
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endmodule
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