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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_prc.v] - Blame information for rev 4

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  PCM Request Controller                                     ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_prc.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
//
//  $Date: 2001-08-03 06:54:50 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2001/05/19 02:29:17  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_prc(clk, rst,
 
                // SR Slot Interface
                valid, in_valid, out_slt0,
                in_slt0, in_slt1,
 
                // Codec Register Access
                crac_valid, crac_wr,
 
                // Channel Configuration
                oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
                ic0_cfg, ic1_cfg, ic2_cfg,
 
                // FIFO Status
                o3_empty, o4_empty, o6_empty, o7_empty, o8_empty,
                o9_empty, i3_full, i4_full, i6_full,
 
                // FIFO Control
                o3_re, o4_re, o6_re, o7_re, o8_re, o9_re,
                i3_we, i4_we, i6_we
 
        );
input           clk, rst;
 
input           valid;
input   [2:0]    in_valid;
output  [15:0]   out_slt0;
input   [15:0]   in_slt0;
input   [19:0]   in_slt1;
 
input           crac_valid;
input           crac_wr;
 
input   [7:0]    oc0_cfg;
input   [7:0]    oc1_cfg;
input   [7:0]    oc2_cfg;
input   [7:0]    oc3_cfg;
input   [7:0]    oc4_cfg;
input   [7:0]    oc5_cfg;
 
input   [7:0]    ic0_cfg;
input   [7:0]    ic1_cfg;
input   [7:0]    ic2_cfg;
 
input           o3_empty;
input           o4_empty;
input           o6_empty;
input           o7_empty;
input           o8_empty;
input           o9_empty;
input           i3_full;
input           i4_full;
input           i6_full;
 
output          o3_re;
output          o4_re;
output          o6_re;
output          o7_re;
output          o8_re;
output          o9_re;
output          i3_we;
output          i4_we;
output          i6_we;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
wire            o3_re_l;
wire            o4_re_l;
wire            o6_re_l;
wire            o7_re_l;
wire            o8_re_l;
wire            o9_re_l;
 
reg             crac_valid_r;
reg             crac_wr_r;
 
////////////////////////////////////////////////////////////////////
//
// Output Tag Assembly
//
 
assign out_slt0[15] = |out_slt0[14:6];
 
assign out_slt0[14] = crac_valid_r;
assign out_slt0[13] = crac_wr_r;
 
assign out_slt0[12] = o3_re_l;
assign out_slt0[11] = o4_re_l;
assign out_slt0[10] = 0;
assign out_slt0[09] = o6_re_l;
assign out_slt0[08] = o7_re_l;
assign out_slt0[07] = o8_re_l;
assign out_slt0[06] = o9_re_l;
assign out_slt0[5:0] = 6'h0;
 
////////////////////////////////////////////////////////////////////
//
// FIFO Control
//
 
always @(posedge clk)
        if(valid)       crac_valid_r <= #1 crac_valid;
 
always @(posedge clk)
        if(valid)       crac_wr_r <= #1 crac_valid & crac_wr;
 
// Output Channel 0 (Out Slot 3)
ac97_fifo_ctrl u0(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc0_cfg[0]       ),
                .srs(           oc0_cfg[1]      ),
                .full_empty(    o3_empty        ),
                .req(           ~in_slt1[11]    ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o3_re           ),
                .en_out_l(      o3_re_l         )
                );
 
// Output Channel 1 (Out Slot 4)
ac97_fifo_ctrl u1(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc1_cfg[0]       ),
                .srs(           oc1_cfg[1]      ),
                .full_empty(    o4_empty        ),
                .req(           ~in_slt1[10]    ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o4_re           ),
                .en_out_l(      o4_re_l         )
                );
 
`ifdef CENTER
// Output Channel 2 (Out Slot 6)
ac97_fifo_ctrl u2(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc2_cfg[0]       ),
                .srs(           oc2_cfg[1]      ),
                .full_empty(    o6_empty        ),
                .req(           ~in_slt1[8]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o6_re           ),
                .en_out_l(      o6_re_l         )
                );
`else
assign o6_re = 0;
assign o6_re_l = 0;
`endif
 
`ifdef SURROUND
// Output Channel 3 (Out Slot 7)
ac97_fifo_ctrl u3(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc3_cfg[0]       ),
                .srs(           oc3_cfg[1]      ),
                .full_empty(    o7_empty        ),
                .req(           ~in_slt1[7]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o7_re           ),
                .en_out_l(      o7_re_l         )
                );
 
// Output Channel 4 (Out Slot 8)
ac97_fifo_ctrl u4(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc4_cfg[0]       ),
                .srs(           oc4_cfg[1]      ),
                .full_empty(    o8_empty        ),
                .req(           ~in_slt1[6]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o8_re           ),
                .en_out_l(      o8_re_l         )
                );
`else
assign o7_re = 0;
assign o7_re_l = 0;
assign o8_re = 0;
assign o8_re_l = 0;
`endif
 
`ifdef LFE
// Output Channel 5 (Out Slot 9)
ac97_fifo_ctrl u5(
                .clk(           clk             ),
                .valid(         valid           ),
                .ch_en(         oc5_cfg[0]       ),
                .srs(           oc5_cfg[1]      ),
                .full_empty(    o9_empty        ),
                .req(           ~in_slt1[5]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        o9_re           ),
                .en_out_l(      o9_re_l         )
                );
`else
assign o9_re = 0;
assign o9_re_l = 0;
`endif
 
`ifdef SIN
// Input Channel 0 (In Slot 3)
ac97_fifo_ctrl u6(
                .clk(           clk             ),
                .valid(         in_valid[0]      ),
                .ch_en(         ic0_cfg[0]       ),
                .srs(           ic0_cfg[1]      ),
                .full_empty(    i3_full         ),
                .req(           in_slt0[12]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        i3_we           ),
                .en_out_l(                      )
                );
 
// Input Channel 1 (In Slot 4)
ac97_fifo_ctrl u7(
                .clk(           clk             ),
                .valid(         in_valid[1]     ),
                .ch_en(         ic1_cfg[0]       ),
                .srs(           ic1_cfg[1]      ),
                .full_empty(    i4_full         ),
                .req(           in_slt0[11]     ),
                .crdy(          in_slt0[15]     ),
                .en_out(        i4_we           ),
                .en_out_l(                      )
                );
`else
assign i3_we = 0;
assign i4_we = 0;
`endif
 
`ifdef MICIN
// Input Channel 2 (In Slot 6)
ac97_fifo_ctrl u8(
                .clk(           clk             ),
                .valid(         in_valid[2]     ),
                .ch_en(         ic2_cfg[0]       ),
                .srs(           ic2_cfg[1]      ),
                .full_empty(    i6_full         ),
                .req(           in_slt0[9]      ),
                .crdy(          in_slt0[15]     ),
                .en_out(        i6_we           ),
                .en_out_l(                      )
                );
`else
assign i6_we = 0;
`endif
 
endmodule
 
 

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_prc.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// PCM Request Controller ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: ac97_prc.v,v 1.1 2001-08-03 06:54:50 rudi Exp $`
42			`//`
43			`// $Date: 2001-08-03 06:54:50 $`
44			`// $Revision: 1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.1.1.1 2001/05/19 02:29:17 rudi`
52			`// Initial Checkin`
53			`//`
54			`//`
55			`//`
56			`//`
57
58			`include "ac97_defines.v"
59
60			`module ac97_prc(clk, rst,`
61
62			`// SR Slot Interface`
63			`valid, in_valid, out_slt0,`
64			`in_slt0, in_slt1,`
65
66			`// Codec Register Access`
67			`crac_valid, crac_wr,`
68
69			`// Channel Configuration`
70			`oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,`
71			`ic0_cfg, ic1_cfg, ic2_cfg,`
72
73			`// FIFO Status`
74			`o3_empty, o4_empty, o6_empty, o7_empty, o8_empty,`
75			`o9_empty, i3_full, i4_full, i6_full,`
76
77			`// FIFO Control`
78			`o3_re, o4_re, o6_re, o7_re, o8_re, o9_re,`
79			`i3_we, i4_we, i6_we`
80
81			`);`
82			`input clk, rst;`
83
84			`input valid;`
85			`input [2:0] in_valid;`
86			`output [15:0] out_slt0;`
87			`input [15:0] in_slt0;`
88			`input [19:0] in_slt1;`
89
90			`input crac_valid;`
91			`input crac_wr;`
92
93			`input [7:0] oc0_cfg;`
94			`input [7:0] oc1_cfg;`
95			`input [7:0] oc2_cfg;`
96			`input [7:0] oc3_cfg;`
97			`input [7:0] oc4_cfg;`
98			`input [7:0] oc5_cfg;`
99
100			`input [7:0] ic0_cfg;`
101			`input [7:0] ic1_cfg;`
102			`input [7:0] ic2_cfg;`
103
104			`input o3_empty;`
105			`input o4_empty;`
106			`input o6_empty;`
107			`input o7_empty;`
108			`input o8_empty;`
109			`input o9_empty;`
110			`input i3_full;`
111			`input i4_full;`
112			`input i6_full;`
113
114			`output o3_re;`
115			`output o4_re;`
116			`output o6_re;`
117			`output o7_re;`
118			`output o8_re;`
119			`output o9_re;`
120			`output i3_we;`
121			`output i4_we;`
122			`output i6_we;`
123
124			`////////////////////////////////////////////////////////////////////`
125			`//`
126			`// Local Wires`
127			`//`
128
129			`wire o3_re_l;`
130			`wire o4_re_l;`
131			`wire o6_re_l;`
132			`wire o7_re_l;`
133			`wire o8_re_l;`
134			`wire o9_re_l;`
135
136			`reg crac_valid_r;`
137			`reg crac_wr_r;`
138
139			`////////////////////////////////////////////////////////////////////`
140			`//`
141			`// Output Tag Assembly`
142			`//`
143
144			`assign out_slt0[15] = \|out_slt0[14:6];`
145
146			`assign out_slt0[14] = crac_valid_r;`
147			`assign out_slt0[13] = crac_wr_r;`
148
149			`assign out_slt0[12] = o3_re_l;`
150			`assign out_slt0[11] = o4_re_l;`
151			`assign out_slt0[10] = 0;`
152			`assign out_slt0[09] = o6_re_l;`
153			`assign out_slt0[08] = o7_re_l;`
154			`assign out_slt0[07] = o8_re_l;`
155			`assign out_slt0[06] = o9_re_l;`
156			`assign out_slt0[5:0] = 6'h0;`
157
158			`////////////////////////////////////////////////////////////////////`
159			`//`
160			`// FIFO Control`
161			`//`
162
163			`always @(posedge clk)`
164			`if(valid) crac_valid_r <= #1 crac_valid;`
165
166			`always @(posedge clk)`
167			`if(valid) crac_wr_r <= #1 crac_valid & crac_wr;`
168
169			`// Output Channel 0 (Out Slot 3)`
170			`ac97_fifo_ctrl u0(`
171			`.clk( clk ),`
172			`.valid( valid ),`
173			`.ch_en( oc0_cfg[0] ),`
174			`.srs( oc0_cfg[1] ),`
175			`.full_empty( o3_empty ),`
176			`.req( ~in_slt1[11] ),`
177			`.crdy( in_slt0[15] ),`
178			`.en_out( o3_re ),`
179			`.en_out_l( o3_re_l )`
180			`);`
181
182			`// Output Channel 1 (Out Slot 4)`
183			`ac97_fifo_ctrl u1(`
184			`.clk( clk ),`
185			`.valid( valid ),`
186			`.ch_en( oc1_cfg[0] ),`
187			`.srs( oc1_cfg[1] ),`
188			`.full_empty( o4_empty ),`
189			`.req( ~in_slt1[10] ),`
190			`.crdy( in_slt0[15] ),`
191			`.en_out( o4_re ),`
192			`.en_out_l( o4_re_l )`
193			`);`
194
195			`ifdef CENTER
196			`// Output Channel 2 (Out Slot 6)`
197			`ac97_fifo_ctrl u2(`
198			`.clk( clk ),`
199			`.valid( valid ),`
200			`.ch_en( oc2_cfg[0] ),`
201			`.srs( oc2_cfg[1] ),`
202			`.full_empty( o6_empty ),`
203			`.req( ~in_slt1[8] ),`
204			`.crdy( in_slt0[15] ),`
205			`.en_out( o6_re ),`
206			`.en_out_l( o6_re_l )`
207			`);`
208			`else
209			`assign o6_re = 0;`
210			`assign o6_re_l = 0;`
211			`endif
212
213			`ifdef SURROUND
214			`// Output Channel 3 (Out Slot 7)`
215			`ac97_fifo_ctrl u3(`
216			`.clk( clk ),`
217			`.valid( valid ),`
218			`.ch_en( oc3_cfg[0] ),`
219			`.srs( oc3_cfg[1] ),`
220			`.full_empty( o7_empty ),`
221			`.req( ~in_slt1[7] ),`
222			`.crdy( in_slt0[15] ),`
223			`.en_out( o7_re ),`
224			`.en_out_l( o7_re_l )`
225			`);`
226
227			`// Output Channel 4 (Out Slot 8)`
228			`ac97_fifo_ctrl u4(`
229			`.clk( clk ),`
230			`.valid( valid ),`
231			`.ch_en( oc4_cfg[0] ),`
232			`.srs( oc4_cfg[1] ),`
233			`.full_empty( o8_empty ),`
234			`.req( ~in_slt1[6] ),`
235			`.crdy( in_slt0[15] ),`
236			`.en_out( o8_re ),`
237			`.en_out_l( o8_re_l )`
238			`);`
239			`else
240			`assign o7_re = 0;`
241			`assign o7_re_l = 0;`
242			`assign o8_re = 0;`
243			`assign o8_re_l = 0;`
244			`endif
245
246			`ifdef LFE
247			`// Output Channel 5 (Out Slot 9)`
248			`ac97_fifo_ctrl u5(`
249			`.clk( clk ),`
250			`.valid( valid ),`
251			`.ch_en( oc5_cfg[0] ),`
252			`.srs( oc5_cfg[1] ),`
253			`.full_empty( o9_empty ),`
254			`.req( ~in_slt1[5] ),`
255			`.crdy( in_slt0[15] ),`
256			`.en_out( o9_re ),`
257			`.en_out_l( o9_re_l )`
258			`);`
259			`else
260			`assign o9_re = 0;`
261			`assign o9_re_l = 0;`
262			`endif
263
264			`ifdef SIN
265			`// Input Channel 0 (In Slot 3)`
266			`ac97_fifo_ctrl u6(`
267			`.clk( clk ),`
268			`.valid( in_valid[0] ),`
269			`.ch_en( ic0_cfg[0] ),`
270			`.srs( ic0_cfg[1] ),`
271			`.full_empty( i3_full ),`
272			`.req( in_slt0[12] ),`
273			`.crdy( in_slt0[15] ),`
274			`.en_out( i3_we ),`
275			`.en_out_l( )`
276			`);`
277
278			`// Input Channel 1 (In Slot 4)`
279			`ac97_fifo_ctrl u7(`
280			`.clk( clk ),`
281			`.valid( in_valid[1] ),`
282			`.ch_en( ic1_cfg[0] ),`
283			`.srs( ic1_cfg[1] ),`
284			`.full_empty( i4_full ),`
285			`.req( in_slt0[11] ),`
286			`.crdy( in_slt0[15] ),`
287			`.en_out( i4_we ),`
288			`.en_out_l( )`
289			`);`
290			`else
291			`assign i3_we = 0;`
292			`assign i4_we = 0;`
293			`endif
294
295			`ifdef MICIN
296			`// Input Channel 2 (In Slot 6)`
297			`ac97_fifo_ctrl u8(`
298			`.clk( clk ),`
299			`.valid( in_valid[2] ),`
300			`.ch_en( ic2_cfg[0] ),`
301			`.srs( ic2_cfg[1] ),`
302			`.full_empty( i6_full ),`
303			`.req( in_slt0[9] ),`
304			`.crdy( in_slt0[15] ),`
305			`.en_out( i6_we ),`
306			`.en_out_l( )`
307			`);`
308			`else
309			`assign i6_we = 0;`
310			`endif
311
312			`endmodule`
313
314