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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Register File                                              ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_rf.v,v 1.4 2002-09-19 06:30:56 rudi Exp $
//
//  $Date: 2002-09-19 06:30:56 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2002/03/05 04:44:05  rudi
//
//               - Fixed the order of the thrash hold bits to match the spec.
//               - Many minor synthesis cleanup items ...
//
//               Revision 1.2  2001/08/10 08:09:42  rudi
//
//               - Removed RTY_O output.
//               - Added Clock and Reset Inputs to documentation.
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:17  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_rf(clk, rst,
 
                adr, rf_dout, rf_din,
                rf_we, rf_re, int, ac97_rst_force,
                resume_req, suspended,
 
                crac_we, crac_din, crac_out,
                crac_rd_done, crac_wr_done,
 
                oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
                ic0_cfg, ic1_cfg, ic2_cfg,
                oc0_int_set, oc1_int_set, oc2_int_set, oc3_int_set,
                oc4_int_set, oc5_int_set,
                ic0_int_set, ic1_int_set, ic2_int_set
 
                );
 
input           clk,rst;
 
input   [3:0]    adr;
output  [31:0]   rf_dout;
input   [31:0]   rf_din;
input           rf_we;
input           rf_re;
output          int;
output          ac97_rst_force;
output          resume_req;
input           suspended;
 
output          crac_we;
input   [15:0]   crac_din;
output  [31:0]   crac_out;
input           crac_rd_done, crac_wr_done;
 
output  [7:0]    oc0_cfg;
output  [7:0]    oc1_cfg;
output  [7:0]    oc2_cfg;
output  [7:0]    oc3_cfg;
output  [7:0]    oc4_cfg;
output  [7:0]    oc5_cfg;
 
output  [7:0]    ic0_cfg;
output  [7:0]    ic1_cfg;
output  [7:0]    ic2_cfg;
 
input   [2:0]    oc0_int_set;
input   [2:0]    oc1_int_set;
input   [2:0]    oc2_int_set;
input   [2:0]    oc3_int_set;
input   [2:0]    oc4_int_set;
input   [2:0]    oc5_int_set;
input   [2:0]    ic0_int_set;
input   [2:0]    ic1_int_set;
input   [2:0]    ic2_int_set;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   rf_dout;
 
reg     [31:0]   csr_r;
reg     [31:0]   occ0_r;
reg     [15:0]   occ1_r;
reg     [23:0]   icc_r;
reg     [31:0]   crac_r;
reg     [28:0]   intm_r;
reg     [28:0]   ints_r;
reg             int;
wire    [28:0]   int_all;
wire    [31:0]   csr, occ0, occ1, icc, crac, intm, ints;
reg     [15:0]   crac_dout_r;
reg             ac97_rst_force;
reg             resume_req;
 
// Aliases
assign csr  = {30'h0, suspended, 1'h0};
assign occ0 = occ0_r;
assign occ1 = {16'h0, occ1_r};
assign icc  = {8'h0,  icc_r};
assign crac = {crac_r[7], 8'h0, crac_r[6:0], crac_din};
assign intm = {3'h0, intm_r};
assign ints = {3'h0, ints_r};
 
assign crac_out = {crac_r[7], 8'h0, crac_r[6:0], crac_dout_r};
 
////////////////////////////////////////////////////////////////////
//
// Register WISHBONE Interface
//
 
always @(adr or csr or occ0 or occ1 or icc or crac or intm or ints)
        case(adr[2:0])   // synopsys parallel_case full_case
           0: rf_dout = csr;
           1: rf_dout = occ0;
           2: rf_dout = occ1;
           3: rf_dout = icc;
           4: rf_dout = crac;
           5: rf_dout = intm;
           6: rf_dout = ints;
        endcase
 
always @(posedge clk or negedge rst)
        if(!rst)                        csr_r <= #1 1'b0;
        else
        if(rf_we & (adr[2:0]==3'h0))     csr_r <= #1 rf_din;
 
always @(posedge clk)
        if(rf_we & (adr[2:0]==3'h0))     ac97_rst_force <= #1 rf_din[0];
        else                            ac97_rst_force <= #1 1'b0;
 
always @(posedge clk)
        if(rf_we & (adr[2:0]==3'h0))     resume_req <= #1 rf_din[1];
        else                            resume_req <= #1 1'b0;
 
always @(posedge clk or negedge rst)
        if(!rst)                        occ0_r <= #1 1'b0;
        else
        if(rf_we & (adr[2:0]==3'h1))     occ0_r <= #1 rf_din;
 
always @(posedge clk or negedge rst)
        if(!rst)                        occ1_r <= #1 1'b0;
        else
        if(rf_we & (adr[2:0]==3'h2))     occ1_r <= #1 rf_din[23:0];
 
always @(posedge clk or negedge rst)
        if(!rst)                        icc_r <= #1 1'b0;
        else
        if(rf_we & (adr[2:0]==3'h3))     icc_r <= #1 rf_din[23:0];
 
assign crac_we = rf_we & (adr[2:0]==3'h4);
 
always @(posedge clk or negedge rst)
        if(!rst)                        crac_r <= #1 1'b0;
        else
        if(crac_we)                     crac_r <= #1 {rf_din[31], rf_din[22:16]};
 
always @(posedge clk)
        if(crac_we)                     crac_dout_r <= #1 rf_din[15:0];
 
always @(posedge clk or negedge rst)
        if(!rst)                        intm_r <= #1 1'b0;
        else
        if(rf_we & (adr[2:0]==3'h5))     intm_r <= #1 rf_din[28:0];
 
// Interrupt Source Register
always @(posedge clk or negedge rst)
        if(!rst)                        ints_r <= #1 1'b0;
        else
        if(rf_re & (adr[2:0]==3'h6))     ints_r <= #1 1'b0;
        else
           begin
                if(crac_rd_done)        ints_r[0] <= #1 1'b1;
                if(crac_wr_done)        ints_r[1] <= #1 1'b1;
                if(oc0_int_set[0])       ints_r[2] <= #1 1'b1;
                if(oc0_int_set[1])      ints_r[3] <= #1 1'b1;
                if(oc0_int_set[2])      ints_r[4] <= #1 1'b1;
                if(oc1_int_set[0])       ints_r[5] <= #1 1'b1;
                if(oc1_int_set[1])      ints_r[6] <= #1 1'b1;
                if(oc1_int_set[2])      ints_r[7] <= #1 1'b1;
`ifdef AC97_CENTER
                if(oc2_int_set[0])       ints_r[8] <= #1 1'b1;
                if(oc2_int_set[1])      ints_r[9] <= #1 1'b1;
                if(oc2_int_set[2])      ints_r[10] <= #1 1'b1;
`endif
 
`ifdef AC97_SURROUND
                if(oc3_int_set[0])       ints_r[11] <= #1 1'b1;
                if(oc3_int_set[1])      ints_r[12] <= #1 1'b1;
                if(oc3_int_set[2])      ints_r[13] <= #1 1'b1;
                if(oc4_int_set[0])       ints_r[14] <= #1 1'b1;
                if(oc4_int_set[1])      ints_r[15] <= #1 1'b1;
                if(oc4_int_set[2])      ints_r[16] <= #1 1'b1;
`endif
 
`ifdef AC97_LFE
                if(oc5_int_set[0])       ints_r[17] <= #1 1'b1;
                if(oc5_int_set[1])      ints_r[18] <= #1 1'b1;
                if(oc5_int_set[2])      ints_r[19] <= #1 1'b1;
`endif
 
`ifdef AC97_SIN
                if(ic0_int_set[0])       ints_r[20] <= #1 1'b1;
                if(ic0_int_set[1])      ints_r[21] <= #1 1'b1;
                if(ic0_int_set[2])      ints_r[22] <= #1 1'b1;
                if(ic1_int_set[0])       ints_r[23] <= #1 1'b1;
                if(ic1_int_set[1])      ints_r[24] <= #1 1'b1;
                if(ic1_int_set[2])      ints_r[25] <= #1 1'b1;
`endif
 
`ifdef AC97_MICIN
                if(ic2_int_set[0])       ints_r[26] <= #1 1'b1;
                if(ic2_int_set[1])      ints_r[27] <= #1 1'b1;
                if(ic2_int_set[2])      ints_r[28] <= #1 1'b1;
`endif
           end
 
////////////////////////////////////////////////////////////////////
//
// Register Internal Interface
//
 
assign oc0_cfg = occ0[7:0];
assign oc1_cfg = occ0[15:8];
assign oc2_cfg = occ0[23:16];
assign oc3_cfg = occ0[31:24];
assign oc4_cfg = occ1[7:0];
assign oc5_cfg = occ1[15:8];
 
assign ic0_cfg = icc[7:0];
assign ic1_cfg = icc[15:8];
assign ic2_cfg = icc[23:16];
 
////////////////////////////////////////////////////////////////////
//
// Interrupt Generation
//
 
assign int_all = intm_r & ints_r;
 
always @(posedge clk)
        int <= #1 |int_all;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Register File ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	14	rudi	`// $Id: ac97_rf.v,v 1.4 2002-09-19 06:30:56 rudi Exp $`
43	4	rudi	`//`
44	14	rudi	`// $Date: 2002-09-19 06:30:56 $`
45			`// $Revision: 1.4 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	14	rudi	`// Revision 1.3 2002/03/05 04:44:05 rudi`
53			`//`
54			`// - Fixed the order of the thrash hold bits to match the spec.`
55			`// - Many minor synthesis cleanup items ...`
56			`//`
57	10	rudi	`// Revision 1.2 2001/08/10 08:09:42 rudi`
58			`//`
59			`// - Removed RTY_O output.`
60			`// - Added Clock and Reset Inputs to documentation.`
61			`// - Changed IO names to be more clear.`
62			`// - Uniquifyed define names to be core specific.`
63			`//`
64	6	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
65			`//`
66			`//`
67			`// - Changed to new directory structure`
68			`//`
69	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:17 rudi`
70			`// Initial Checkin`
71			`//`
72			`//`
73			`//`
74			`//`
75
76			`include "ac97_defines.v"
77
78			`module ac97_rf(clk, rst,`
79
80			`adr, rf_dout, rf_din,`
81			`rf_we, rf_re, int, ac97_rst_force,`
82			`resume_req, suspended,`
83
84			`crac_we, crac_din, crac_out,`
85			`crac_rd_done, crac_wr_done,`
86
87			`oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,`
88			`ic0_cfg, ic1_cfg, ic2_cfg,`
89			`oc0_int_set, oc1_int_set, oc2_int_set, oc3_int_set,`
90			`oc4_int_set, oc5_int_set,`
91			`ic0_int_set, ic1_int_set, ic2_int_set`
92
93			`);`
94
95			`input clk,rst;`
96
97			`input [3:0] adr;`
98			`output [31:0] rf_dout;`
99			`input [31:0] rf_din;`
100			`input rf_we;`
101			`input rf_re;`
102			`output int;`
103			`output ac97_rst_force;`
104			`output resume_req;`
105			`input suspended;`
106
107			`output crac_we;`
108			`input [15:0] crac_din;`
109			`output [31:0] crac_out;`
110			`input crac_rd_done, crac_wr_done;`
111
112			`output [7:0] oc0_cfg;`
113			`output [7:0] oc1_cfg;`
114			`output [7:0] oc2_cfg;`
115			`output [7:0] oc3_cfg;`
116			`output [7:0] oc4_cfg;`
117			`output [7:0] oc5_cfg;`
118
119			`output [7:0] ic0_cfg;`
120			`output [7:0] ic1_cfg;`
121			`output [7:0] ic2_cfg;`
122
123			`input [2:0] oc0_int_set;`
124			`input [2:0] oc1_int_set;`
125			`input [2:0] oc2_int_set;`
126			`input [2:0] oc3_int_set;`
127			`input [2:0] oc4_int_set;`
128			`input [2:0] oc5_int_set;`
129			`input [2:0] ic0_int_set;`
130			`input [2:0] ic1_int_set;`
131			`input [2:0] ic2_int_set;`
132
133			`////////////////////////////////////////////////////////////////////`
134			`//`
135			`// Local Wires`
136			`//`
137
138			`reg [31:0] rf_dout;`
139
140			`reg [31:0] csr_r;`
141			`reg [31:0] occ0_r;`
142			`reg [15:0] occ1_r;`
143			`reg [23:0] icc_r;`
144			`reg [31:0] crac_r;`
145			`reg [28:0] intm_r;`
146			`reg [28:0] ints_r;`
147			`reg int;`
148			`wire [28:0] int_all;`
149			`wire [31:0] csr, occ0, occ1, icc, crac, intm, ints;`
150			`reg [15:0] crac_dout_r;`
151			`reg ac97_rst_force;`
152			`reg resume_req;`
153
154			`// Aliases`
155			`assign csr = {30'h0, suspended, 1'h0};`
156			`assign occ0 = occ0_r;`
157			`assign occ1 = {16'h0, occ1_r};`
158			`assign icc = {8'h0, icc_r};`
159			`assign crac = {crac_r[7], 8'h0, crac_r[6:0], crac_din};`
160			`assign intm = {3'h0, intm_r};`
161			`assign ints = {3'h0, ints_r};`
162
163			`assign crac_out = {crac_r[7], 8'h0, crac_r[6:0], crac_dout_r};`
164
165			`////////////////////////////////////////////////////////////////////`
166			`//`
167			`// Register WISHBONE Interface`
168			`//`
169
170			`always @(adr or csr or occ0 or occ1 or icc or crac or intm or ints)`
171			`case(adr[2:0]) // synopsys parallel_case full_case`
172			`0: rf_dout = csr;`
173			`1: rf_dout = occ0;`
174			`2: rf_dout = occ1;`
175			`3: rf_dout = icc;`
176			`4: rf_dout = crac;`
177			`5: rf_dout = intm;`
178			`6: rf_dout = ints;`
179			`endcase`
180
181			`always @(posedge clk or negedge rst)`
182	10	rudi	`if(!rst) csr_r <= #1 1'b0;`
183	4	rudi	`else`
184	10	rudi	`if(rf_we & (adr[2:0]==3'h0)) csr_r <= #1 rf_din;`
185	4	rudi
186			`always @(posedge clk)`
187	10	rudi	`if(rf_we & (adr[2:0]==3'h0)) ac97_rst_force <= #1 rf_din[0];`
188			`else ac97_rst_force <= #1 1'b0;`
189	4	rudi
190			`always @(posedge clk)`
191	10	rudi	`if(rf_we & (adr[2:0]==3'h0)) resume_req <= #1 rf_din[1];`
192			`else resume_req <= #1 1'b0;`
193	4	rudi
194			`always @(posedge clk or negedge rst)`
195	10	rudi	`if(!rst) occ0_r <= #1 1'b0;`
196	4	rudi	`else`
197	10	rudi	`if(rf_we & (adr[2:0]==3'h1)) occ0_r <= #1 rf_din;`
198	4	rudi
199			`always @(posedge clk or negedge rst)`
200	10	rudi	`if(!rst) occ1_r <= #1 1'b0;`
201	4	rudi	`else`
202	10	rudi	`if(rf_we & (adr[2:0]==3'h2)) occ1_r <= #1 rf_din[23:0];`
203	4	rudi
204			`always @(posedge clk or negedge rst)`
205	10	rudi	`if(!rst) icc_r <= #1 1'b0;`
206	4	rudi	`else`
207	10	rudi	`if(rf_we & (adr[2:0]==3'h3)) icc_r <= #1 rf_din[23:0];`
208	4	rudi
209	10	rudi	`assign crac_we = rf_we & (adr[2:0]==3'h4);`
210	4	rudi
211			`always @(posedge clk or negedge rst)`
212	10	rudi	`if(!rst) crac_r <= #1 1'b0;`
213	4	rudi	`else`
214			`if(crac_we) crac_r <= #1 {rf_din[31], rf_din[22:16]};`
215
216			`always @(posedge clk)`
217			`if(crac_we) crac_dout_r <= #1 rf_din[15:0];`
218
219			`always @(posedge clk or negedge rst)`
220	10	rudi	`if(!rst) intm_r <= #1 1'b0;`
221	4	rudi	`else`
222	10	rudi	`if(rf_we & (adr[2:0]==3'h5)) intm_r <= #1 rf_din[28:0];`
223	4	rudi
224			`// Interrupt Source Register`
225			`always @(posedge clk or negedge rst)`
226	10	rudi	`if(!rst) ints_r <= #1 1'b0;`
227	4	rudi	`else`
228	10	rudi	`if(rf_re & (adr[2:0]==3'h6)) ints_r <= #1 1'b0;`
229	4	rudi	`else`
230			`begin`
231	10	rudi	`if(crac_rd_done) ints_r[0] <= #1 1'b1;`
232			`if(crac_wr_done) ints_r[1] <= #1 1'b1;`
233			`if(oc0_int_set[0]) ints_r[2] <= #1 1'b1;`
234			`if(oc0_int_set[1]) ints_r[3] <= #1 1'b1;`
235			`if(oc0_int_set[2]) ints_r[4] <= #1 1'b1;`
236			`if(oc1_int_set[0]) ints_r[5] <= #1 1'b1;`
237			`if(oc1_int_set[1]) ints_r[6] <= #1 1'b1;`
238			`if(oc1_int_set[2]) ints_r[7] <= #1 1'b1;`
239	6	rudi	`ifdef AC97_CENTER
240	10	rudi	`if(oc2_int_set[0]) ints_r[8] <= #1 1'b1;`
241			`if(oc2_int_set[1]) ints_r[9] <= #1 1'b1;`
242			`if(oc2_int_set[2]) ints_r[10] <= #1 1'b1;`
243	4	rudi	`endif
244
245	6	rudi	`ifdef AC97_SURROUND
246	10	rudi	`if(oc3_int_set[0]) ints_r[11] <= #1 1'b1;`
247			`if(oc3_int_set[1]) ints_r[12] <= #1 1'b1;`
248			`if(oc3_int_set[2]) ints_r[13] <= #1 1'b1;`
249			`if(oc4_int_set[0]) ints_r[14] <= #1 1'b1;`
250			`if(oc4_int_set[1]) ints_r[15] <= #1 1'b1;`
251			`if(oc4_int_set[2]) ints_r[16] <= #1 1'b1;`
252	4	rudi	`endif
253
254	6	rudi	`ifdef AC97_LFE
255	10	rudi	`if(oc5_int_set[0]) ints_r[17] <= #1 1'b1;`
256			`if(oc5_int_set[1]) ints_r[18] <= #1 1'b1;`
257			`if(oc5_int_set[2]) ints_r[19] <= #1 1'b1;`
258	4	rudi	`endif
259
260	6	rudi	`ifdef AC97_SIN
261	10	rudi	`if(ic0_int_set[0]) ints_r[20] <= #1 1'b1;`
262			`if(ic0_int_set[1]) ints_r[21] <= #1 1'b1;`
263			`if(ic0_int_set[2]) ints_r[22] <= #1 1'b1;`
264			`if(ic1_int_set[0]) ints_r[23] <= #1 1'b1;`
265			`if(ic1_int_set[1]) ints_r[24] <= #1 1'b1;`
266			`if(ic1_int_set[2]) ints_r[25] <= #1 1'b1;`
267	4	rudi	`endif
268
269	6	rudi	`ifdef AC97_MICIN
270	10	rudi	`if(ic2_int_set[0]) ints_r[26] <= #1 1'b1;`
271			`if(ic2_int_set[1]) ints_r[27] <= #1 1'b1;`
272			`if(ic2_int_set[2]) ints_r[28] <= #1 1'b1;`
273	4	rudi	`endif
274			`end`
275
276			`////////////////////////////////////////////////////////////////////`
277			`//`
278			`// Register Internal Interface`
279			`//`
280
281			`assign oc0_cfg = occ0[7:0];`
282			`assign oc1_cfg = occ0[15:8];`
283			`assign oc2_cfg = occ0[23:16];`
284			`assign oc3_cfg = occ0[31:24];`
285			`assign oc4_cfg = occ1[7:0];`
286			`assign oc5_cfg = occ1[15:8];`
287
288			`assign ic0_cfg = icc[7:0];`
289			`assign ic1_cfg = icc[15:8];`
290			`assign ic2_cfg = icc[23:16];`
291
292			`////////////////////////////////////////////////////////////////////`
293			`//`
294			`// Interrupt Generation`
295			`//`
296
297			`assign int_all = intm_r & ints_r;`
298
299			`always @(posedge clk)`
300			`int <= #1 \|int_all;`
301
302			`endmodule`

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