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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Register File                                              ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_rf.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
//
//  $Date: 2001-08-03 06:54:50 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2001/05/19 02:29:17  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_rf(clk, rst,
 
                adr, rf_dout, rf_din,
                rf_we, rf_re, int, ac97_rst_force,
                resume_req, suspended,
 
                crac_we, crac_din, crac_out,
                crac_rd_done, crac_wr_done,
 
                oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
                ic0_cfg, ic1_cfg, ic2_cfg,
                oc0_int_set, oc1_int_set, oc2_int_set, oc3_int_set,
                oc4_int_set, oc5_int_set,
                ic0_int_set, ic1_int_set, ic2_int_set
 
                );
 
input           clk,rst;
 
input   [3:0]    adr;
output  [31:0]   rf_dout;
input   [31:0]   rf_din;
input           rf_we;
input           rf_re;
output          int;
output          ac97_rst_force;
output          resume_req;
input           suspended;
 
output          crac_we;
input   [15:0]   crac_din;
output  [31:0]   crac_out;
input           crac_rd_done, crac_wr_done;
 
output  [7:0]    oc0_cfg;
output  [7:0]    oc1_cfg;
output  [7:0]    oc2_cfg;
output  [7:0]    oc3_cfg;
output  [7:0]    oc4_cfg;
output  [7:0]    oc5_cfg;
 
output  [7:0]    ic0_cfg;
output  [7:0]    ic1_cfg;
output  [7:0]    ic2_cfg;
 
input   [2:0]    oc0_int_set;
input   [2:0]    oc1_int_set;
input   [2:0]    oc2_int_set;
input   [2:0]    oc3_int_set;
input   [2:0]    oc4_int_set;
input   [2:0]    oc5_int_set;
input   [2:0]    ic0_int_set;
input   [2:0]    ic1_int_set;
input   [2:0]    ic2_int_set;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   rf_dout;
 
reg     [31:0]   csr_r;
reg     [31:0]   occ0_r;
reg     [15:0]   occ1_r;
reg     [23:0]   icc_r;
reg     [31:0]   crac_r;
reg     [28:0]   intm_r;
reg     [28:0]   ints_r;
reg             int;
wire    [28:0]   int_all;
wire    [31:0]   csr, occ0, occ1, icc, crac, intm, ints;
reg     [15:0]   crac_dout_r;
reg             ac97_rst_force;
reg             resume_req;
 
// Aliases
assign csr  = {30'h0, suspended, 1'h0};
assign occ0 = occ0_r;
assign occ1 = {16'h0, occ1_r};
assign icc  = {8'h0,  icc_r};
assign crac = {crac_r[7], 8'h0, crac_r[6:0], crac_din};
assign intm = {3'h0, intm_r};
assign ints = {3'h0, ints_r};
 
assign crac_out = {crac_r[7], 8'h0, crac_r[6:0], crac_dout_r};
 
////////////////////////////////////////////////////////////////////
//
// Register WISHBONE Interface
//
 
always @(adr or csr or occ0 or occ1 or icc or crac or intm or ints)
        case(adr[2:0])   // synopsys parallel_case full_case
           0: rf_dout = csr;
           1: rf_dout = occ0;
           2: rf_dout = occ1;
           3: rf_dout = icc;
           4: rf_dout = crac;
           5: rf_dout = intm;
           6: rf_dout = ints;
        endcase
 
always @(posedge clk or negedge rst)
        if(!rst)                        csr_r <= #1 0;
        else
        if(rf_we & (adr[2:0]==0)) csr_r <= #1 rf_din;
 
always @(posedge clk)
        if(rf_we & (adr[2:0]==0)) ac97_rst_force <= #1 rf_din[0];
        else                            ac97_rst_force <= #1 0;
 
always @(posedge clk)
        if(rf_we & (adr[2:0]==0)) resume_req <= #1 rf_din[1];
        else                            resume_req <= #1 0;
 
always @(posedge clk or negedge rst)
        if(!rst)                        occ0_r <= #1 0;
        else
        if(rf_we & (adr[2:0]==1))        occ0_r <= #1 rf_din;
 
always @(posedge clk or negedge rst)
        if(!rst)                        occ1_r <= #1 0;
        else
        if(rf_we & (adr[2:0]==2))        occ1_r <= #1 rf_din[23:0];
 
always @(posedge clk or negedge rst)
        if(!rst)                        icc_r <= #1 0;
        else
        if(rf_we & (adr[2:0]==3))        icc_r <= #1 rf_din[23:0];
 
assign crac_we = rf_we & (adr[2:0]==4);
 
always @(posedge clk or negedge rst)
        if(!rst)                        crac_r <= #1 0;
        else
        if(crac_we)                     crac_r <= #1 {rf_din[31], rf_din[22:16]};
 
always @(posedge clk)
        if(crac_we)                     crac_dout_r <= #1 rf_din[15:0];
 
always @(posedge clk or negedge rst)
        if(!rst)                        intm_r <= #1 0;
        else
        if(rf_we & (adr[2:0]==5))        intm_r <= #1 rf_din[28:0];
 
// Interrupt Source Register
always @(posedge clk or negedge rst)
        if(!rst)                        ints_r <= #1 0;
        else
        if(rf_re & (adr[2:0]==6))        ints_r <= #1 0;
        else
           begin
                if(crac_rd_done)        ints_r[0] <= #1 1;
                if(crac_wr_done)        ints_r[1] <= #1 1;
                if(oc0_int_set[0])       ints_r[2] <= #1 1;
                if(oc0_int_set[1])      ints_r[3] <= #1 1;
                if(oc0_int_set[2])      ints_r[4] <= #1 1;
                if(oc1_int_set[0])       ints_r[5] <= #1 1;
                if(oc1_int_set[1])      ints_r[6] <= #1 1;
                if(oc1_int_set[2])      ints_r[7] <= #1 1;
`ifdef CENTER
                if(oc2_int_set[0])       ints_r[8] <= #1 1;
                if(oc2_int_set[1])      ints_r[9] <= #1 1;
                if(oc2_int_set[2])      ints_r[10] <= #1 1;
`endif
 
`ifdef SURROUND
                if(oc3_int_set[0])       ints_r[11] <= #1 1;
                if(oc3_int_set[1])      ints_r[12] <= #1 1;
                if(oc3_int_set[2])      ints_r[13] <= #1 1;
                if(oc4_int_set[0])       ints_r[14] <= #1 1;
                if(oc4_int_set[1])      ints_r[15] <= #1 1;
                if(oc4_int_set[2])      ints_r[16] <= #1 1;
`endif
 
`ifdef LFE
                if(oc5_int_set[0])       ints_r[17] <= #1 1;
                if(oc5_int_set[1])      ints_r[18] <= #1 1;
                if(oc5_int_set[2])      ints_r[19] <= #1 1;
`endif
 
`ifdef SIN
                if(ic0_int_set[0])       ints_r[20] <= #1 1;
                if(ic0_int_set[1])      ints_r[21] <= #1 1;
                if(ic0_int_set[2])      ints_r[22] <= #1 1;
                if(ic1_int_set[0])       ints_r[23] <= #1 1;
                if(ic1_int_set[1])      ints_r[24] <= #1 1;
                if(ic1_int_set[2])      ints_r[25] <= #1 1;
`endif
 
`ifdef MICIN
                if(ic2_int_set[0])       ints_r[26] <= #1 1;
                if(ic2_int_set[1])      ints_r[27] <= #1 1;
                if(ic2_int_set[2])      ints_r[28] <= #1 1;
`endif
           end
 
////////////////////////////////////////////////////////////////////
//
// Register Internal Interface
//
 
assign oc0_cfg = occ0[7:0];
assign oc1_cfg = occ0[15:8];
assign oc2_cfg = occ0[23:16];
assign oc3_cfg = occ0[31:24];
assign oc4_cfg = occ1[7:0];
assign oc5_cfg = occ1[15:8];
 
assign ic0_cfg = icc[7:0];
assign ic1_cfg = icc[15:8];
assign ic2_cfg = icc[23:16];
 
////////////////////////////////////////////////////////////////////
//
// Interrupt Generation
//
 
assign int_all = intm_r & ints_r;
 
always @(posedge clk)
        int <= #1 |int_all;
 
endmodule

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_rf.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Register File ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: ac97_rf.v,v 1.1 2001-08-03 06:54:50 rudi Exp $`
42			`//`
43			`// $Date: 2001-08-03 06:54:50 $`
44			`// $Revision: 1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.1.1.1 2001/05/19 02:29:17 rudi`
52			`// Initial Checkin`
53			`//`
54			`//`
55			`//`
56			`//`
57
58			`include "ac97_defines.v"
59
60			`module ac97_rf(clk, rst,`
61
62			`adr, rf_dout, rf_din,`
63			`rf_we, rf_re, int, ac97_rst_force,`
64			`resume_req, suspended,`
65
66			`crac_we, crac_din, crac_out,`
67			`crac_rd_done, crac_wr_done,`
68
69			`oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,`
70			`ic0_cfg, ic1_cfg, ic2_cfg,`
71			`oc0_int_set, oc1_int_set, oc2_int_set, oc3_int_set,`
72			`oc4_int_set, oc5_int_set,`
73			`ic0_int_set, ic1_int_set, ic2_int_set`
74
75			`);`
76
77			`input clk,rst;`
78
79			`input [3:0] adr;`
80			`output [31:0] rf_dout;`
81			`input [31:0] rf_din;`
82			`input rf_we;`
83			`input rf_re;`
84			`output int;`
85			`output ac97_rst_force;`
86			`output resume_req;`
87			`input suspended;`
88
89			`output crac_we;`
90			`input [15:0] crac_din;`
91			`output [31:0] crac_out;`
92			`input crac_rd_done, crac_wr_done;`
93
94			`output [7:0] oc0_cfg;`
95			`output [7:0] oc1_cfg;`
96			`output [7:0] oc2_cfg;`
97			`output [7:0] oc3_cfg;`
98			`output [7:0] oc4_cfg;`
99			`output [7:0] oc5_cfg;`
100
101			`output [7:0] ic0_cfg;`
102			`output [7:0] ic1_cfg;`
103			`output [7:0] ic2_cfg;`
104
105			`input [2:0] oc0_int_set;`
106			`input [2:0] oc1_int_set;`
107			`input [2:0] oc2_int_set;`
108			`input [2:0] oc3_int_set;`
109			`input [2:0] oc4_int_set;`
110			`input [2:0] oc5_int_set;`
111			`input [2:0] ic0_int_set;`
112			`input [2:0] ic1_int_set;`
113			`input [2:0] ic2_int_set;`
114
115			`////////////////////////////////////////////////////////////////////`
116			`//`
117			`// Local Wires`
118			`//`
119
120			`reg [31:0] rf_dout;`
121
122			`reg [31:0] csr_r;`
123			`reg [31:0] occ0_r;`
124			`reg [15:0] occ1_r;`
125			`reg [23:0] icc_r;`
126			`reg [31:0] crac_r;`
127			`reg [28:0] intm_r;`
128			`reg [28:0] ints_r;`
129			`reg int;`
130			`wire [28:0] int_all;`
131			`wire [31:0] csr, occ0, occ1, icc, crac, intm, ints;`
132			`reg [15:0] crac_dout_r;`
133			`reg ac97_rst_force;`
134			`reg resume_req;`
135
136			`// Aliases`
137			`assign csr = {30'h0, suspended, 1'h0};`
138			`assign occ0 = occ0_r;`
139			`assign occ1 = {16'h0, occ1_r};`
140			`assign icc = {8'h0, icc_r};`
141			`assign crac = {crac_r[7], 8'h0, crac_r[6:0], crac_din};`
142			`assign intm = {3'h0, intm_r};`
143			`assign ints = {3'h0, ints_r};`
144
145			`assign crac_out = {crac_r[7], 8'h0, crac_r[6:0], crac_dout_r};`
146
147			`////////////////////////////////////////////////////////////////////`
148			`//`
149			`// Register WISHBONE Interface`
150			`//`
151
152			`always @(adr or csr or occ0 or occ1 or icc or crac or intm or ints)`
153			`case(adr[2:0]) // synopsys parallel_case full_case`
154			`0: rf_dout = csr;`
155			`1: rf_dout = occ0;`
156			`2: rf_dout = occ1;`
157			`3: rf_dout = icc;`
158			`4: rf_dout = crac;`
159			`5: rf_dout = intm;`
160			`6: rf_dout = ints;`
161			`endcase`
162
163			`always @(posedge clk or negedge rst)`
164			`if(!rst) csr_r <= #1 0;`
165			`else`
166			`if(rf_we & (adr[2:0]==0)) csr_r <= #1 rf_din;`
167
168			`always @(posedge clk)`
169			`if(rf_we & (adr[2:0]==0)) ac97_rst_force <= #1 rf_din[0];`
170			`else ac97_rst_force <= #1 0;`
171
172			`always @(posedge clk)`
173			`if(rf_we & (adr[2:0]==0)) resume_req <= #1 rf_din[1];`
174			`else resume_req <= #1 0;`
175
176			`always @(posedge clk or negedge rst)`
177			`if(!rst) occ0_r <= #1 0;`
178			`else`
179			`if(rf_we & (adr[2:0]==1)) occ0_r <= #1 rf_din;`
180
181			`always @(posedge clk or negedge rst)`
182			`if(!rst) occ1_r <= #1 0;`
183			`else`
184			`if(rf_we & (adr[2:0]==2)) occ1_r <= #1 rf_din[23:0];`
185
186			`always @(posedge clk or negedge rst)`
187			`if(!rst) icc_r <= #1 0;`
188			`else`
189			`if(rf_we & (adr[2:0]==3)) icc_r <= #1 rf_din[23:0];`
190
191			`assign crac_we = rf_we & (adr[2:0]==4);`
192
193			`always @(posedge clk or negedge rst)`
194			`if(!rst) crac_r <= #1 0;`
195			`else`
196			`if(crac_we) crac_r <= #1 {rf_din[31], rf_din[22:16]};`
197
198			`always @(posedge clk)`
199			`if(crac_we) crac_dout_r <= #1 rf_din[15:0];`
200
201			`always @(posedge clk or negedge rst)`
202			`if(!rst) intm_r <= #1 0;`
203			`else`
204			`if(rf_we & (adr[2:0]==5)) intm_r <= #1 rf_din[28:0];`
205
206			`// Interrupt Source Register`
207			`always @(posedge clk or negedge rst)`
208			`if(!rst) ints_r <= #1 0;`
209			`else`
210			`if(rf_re & (adr[2:0]==6)) ints_r <= #1 0;`
211			`else`
212			`begin`
213			`if(crac_rd_done) ints_r[0] <= #1 1;`
214			`if(crac_wr_done) ints_r[1] <= #1 1;`
215			`if(oc0_int_set[0]) ints_r[2] <= #1 1;`
216			`if(oc0_int_set[1]) ints_r[3] <= #1 1;`
217			`if(oc0_int_set[2]) ints_r[4] <= #1 1;`
218			`if(oc1_int_set[0]) ints_r[5] <= #1 1;`
219			`if(oc1_int_set[1]) ints_r[6] <= #1 1;`
220			`if(oc1_int_set[2]) ints_r[7] <= #1 1;`
221			`ifdef CENTER
222			`if(oc2_int_set[0]) ints_r[8] <= #1 1;`
223			`if(oc2_int_set[1]) ints_r[9] <= #1 1;`
224			`if(oc2_int_set[2]) ints_r[10] <= #1 1;`
225			`endif
226
227			`ifdef SURROUND
228			`if(oc3_int_set[0]) ints_r[11] <= #1 1;`
229			`if(oc3_int_set[1]) ints_r[12] <= #1 1;`
230			`if(oc3_int_set[2]) ints_r[13] <= #1 1;`
231			`if(oc4_int_set[0]) ints_r[14] <= #1 1;`
232			`if(oc4_int_set[1]) ints_r[15] <= #1 1;`
233			`if(oc4_int_set[2]) ints_r[16] <= #1 1;`
234			`endif
235
236			`ifdef LFE
237			`if(oc5_int_set[0]) ints_r[17] <= #1 1;`
238			`if(oc5_int_set[1]) ints_r[18] <= #1 1;`
239			`if(oc5_int_set[2]) ints_r[19] <= #1 1;`
240			`endif
241
242			`ifdef SIN
243			`if(ic0_int_set[0]) ints_r[20] <= #1 1;`
244			`if(ic0_int_set[1]) ints_r[21] <= #1 1;`
245			`if(ic0_int_set[2]) ints_r[22] <= #1 1;`
246			`if(ic1_int_set[0]) ints_r[23] <= #1 1;`
247			`if(ic1_int_set[1]) ints_r[24] <= #1 1;`
248			`if(ic1_int_set[2]) ints_r[25] <= #1 1;`
249			`endif
250
251			`ifdef MICIN
252			`if(ic2_int_set[0]) ints_r[26] <= #1 1;`
253			`if(ic2_int_set[1]) ints_r[27] <= #1 1;`
254			`if(ic2_int_set[2]) ints_r[28] <= #1 1;`
255			`endif
256			`end`
257
258			`////////////////////////////////////////////////////////////////////`
259			`//`
260			`// Register Internal Interface`
261			`//`
262
263			`assign oc0_cfg = occ0[7:0];`
264			`assign oc1_cfg = occ0[15:8];`
265			`assign oc2_cfg = occ0[23:16];`
266			`assign oc3_cfg = occ0[31:24];`
267			`assign oc4_cfg = occ1[7:0];`
268			`assign oc5_cfg = occ1[15:8];`
269
270			`assign ic0_cfg = icc[7:0];`
271			`assign ic1_cfg = icc[15:8];`
272			`assign ic2_cfg = icc[23:16];`
273
274			`////////////////////////////////////////////////////////////////////`
275			`//`
276			`// Interrupt Generation`
277			`//`
278
279			`assign int_all = intm_r & ints_r;`
280
281			`always @(posedge clk)`
282			`int <= #1 \|int_all;`
283
284			`endmodule`