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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_soc.v] - Blame information for rev 20

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Serial Output Controller                                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_soc.v,v 1.3 2002-09-19 06:30:56 rudi Exp $
//
//  $Date: 2002-09-19 06:30:56 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2002/03/05 04:44:05  rudi
//
//               - Fixed the order of the thrash hold bits to match the spec.
//               - Many minor synthesis cleanup items ...
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:15  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_soc(clk, wclk, rst,
                ps_ce, resume, suspended,
                sync, out_le, in_valid, ld, valid
                );
 
input           clk, wclk, rst;
input           ps_ce;
input           resume;
output          suspended;
output          sync;
output  [5:0]    out_le;
output  [2:0]    in_valid;
output          ld;
output          valid;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [7:0]    cnt;
reg             sync_beat;
reg             sync_resume;
reg     [5:0]    out_le;
reg             ld;
reg             valid;
reg     [2:0]    in_valid;
reg             bit_clk_r;
reg             bit_clk_r1;
reg             bit_clk_e;
reg             suspended;
wire            to;
reg     [5:0]    to_cnt;
reg     [3:0]    res_cnt;
wire            resume_done;
 
assign sync = sync_beat | sync_resume;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk or negedge rst)
        if(!rst)                cnt <= #1 8'hff;
        else
        if(suspended)           cnt <= #1 8'hff;
        else                    cnt <= #1 cnt + 8'h1;
 
always @(posedge clk)
        ld <= #1 (cnt == 8'h00);
 
always @(posedge clk)
        sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
 
always @(posedge clk)
        valid <= #1 (cnt > 8'h39);
 
always @(posedge clk)
        out_le[0] <= #1 (cnt == 8'h11);          // Slot 0 Latch Enable
 
always @(posedge clk)
        out_le[1] <= #1 (cnt == 8'h25);         // Slot 1 Latch Enable
 
always @(posedge clk)
        out_le[2] <= #1 (cnt == 8'h39);         // Slot 2 Latch Enable
 
always @(posedge clk)
        out_le[3] <= #1 (cnt == 8'h4d);         // Slot 3 Latch Enable
 
always @(posedge clk)
        out_le[4] <= #1 (cnt == 8'h61);         // Slot 4 Latch Enable
 
always @(posedge clk)
        out_le[5] <= #1 (cnt == 8'h89);         // Slot 6 Latch Enable
 
always @(posedge clk)
        in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
 
always @(posedge clk)
        in_valid[1] <= #1 (cnt > 8'h61);        // Input Slot 3 Valid
 
always @(posedge clk)
        in_valid[2] <= #1 (cnt > 8'h89);        // Input Slot 3 Valid
 
////////////////////////////////////////////////////////////////////
//
// Suspend Detect
//
 
always @(posedge wclk)
        bit_clk_r <= #1 clk;
 
always @(posedge wclk)
        bit_clk_r1 <= #1 bit_clk_r;
 
always @(posedge wclk)
        bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1);
 
always @(posedge wclk)
        suspended <= #1 to;
 
assign to = (to_cnt == `AC97_SUSP_DET);
 
always @(posedge wclk or negedge rst)
        if(!rst)                to_cnt <= #1 6'h0;
        else
        if(bit_clk_e)           to_cnt <= #1 6'h0;
        else
        if(!to)                 to_cnt <= #1 to_cnt + 6'h1;
 
////////////////////////////////////////////////////////////////////
//
// Resume Signaling
//
 
always @(posedge wclk or negedge rst)
        if(!rst)                        sync_resume <= #1 1'b0;
        else
        if(resume_done)                 sync_resume <= #1 1'b0;
        else
        if(suspended & resume)          sync_resume <= #1 1'b1;
 
assign resume_done = (res_cnt == `AC97_RES_SIG);
 
always @(posedge wclk)
        if(!sync_resume)        res_cnt <= #1 4'h0;
        else
        if(ps_ce)               res_cnt <= #1 res_cnt + 4'h1;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Serial Output Controller ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	14	rudi	`// $Id: ac97_soc.v,v 1.3 2002-09-19 06:30:56 rudi Exp $`
43	4	rudi	`//`
44	14	rudi	`// $Date: 2002-09-19 06:30:56 $`
45			`// $Revision: 1.3 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	14	rudi	`// Revision 1.2 2002/03/05 04:44:05 rudi`
53			`//`
54			`// - Fixed the order of the thrash hold bits to match the spec.`
55			`// - Many minor synthesis cleanup items ...`
56			`//`
57	10	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
58			`//`
59			`//`
60			`// - Changed to new directory structure`
61			`//`
62	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:15 rudi`
63			`// Initial Checkin`
64			`//`
65			`//`
66			`//`
67			`//`
68
69			`include "ac97_defines.v"
70
71			`module ac97_soc(clk, wclk, rst,`
72			`ps_ce, resume, suspended,`
73			`sync, out_le, in_valid, ld, valid`
74			`);`
75
76			`input clk, wclk, rst;`
77			`input ps_ce;`
78			`input resume;`
79			`output suspended;`
80			`output sync;`
81			`output [5:0] out_le;`
82			`output [2:0] in_valid;`
83			`output ld;`
84			`output valid;`
85
86			`////////////////////////////////////////////////////////////////////`
87			`//`
88			`// Local Wires`
89			`//`
90
91			`reg [7:0] cnt;`
92			`reg sync_beat;`
93			`reg sync_resume;`
94			`reg [5:0] out_le;`
95			`reg ld;`
96			`reg valid;`
97			`reg [2:0] in_valid;`
98			`reg bit_clk_r;`
99	14	rudi	`reg bit_clk_r1;`
100	4	rudi	`reg bit_clk_e;`
101			`reg suspended;`
102			`wire to;`
103			`reg [5:0] to_cnt;`
104			`reg [3:0] res_cnt;`
105			`wire resume_done;`
106
107			`assign sync = sync_beat \| sync_resume;`
108
109			`////////////////////////////////////////////////////////////////////`
110			`//`
111			`// Misc Logic`
112			`//`
113
114			`always @(posedge clk or negedge rst)`
115			`if(!rst) cnt <= #1 8'hff;`
116			`else`
117			`if(suspended) cnt <= #1 8'hff;`
118	10	rudi	`else cnt <= #1 cnt + 8'h1;`
119	4	rudi
120			`always @(posedge clk)`
121			`ld <= #1 (cnt == 8'h00);`
122
123			`always @(posedge clk)`
124	10	rudi	`sync_beat <= #1 (cnt == 8'h00) \| ((cnt > 8'h00) & (cnt < 8'h10));`
125	4	rudi
126			`always @(posedge clk)`
127	10	rudi	`valid <= #1 (cnt > 8'h39);`
128	4	rudi
129			`always @(posedge clk)`
130	10	rudi	`out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable`
131	4	rudi
132			`always @(posedge clk)`
133	10	rudi	`out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable`
134	4	rudi
135			`always @(posedge clk)`
136	10	rudi	`out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable`
137	4	rudi
138			`always @(posedge clk)`
139	10	rudi	`out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable`
140	4	rudi
141			`always @(posedge clk)`
142	10	rudi	`out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable`
143	4	rudi
144			`always @(posedge clk)`
145	10	rudi	`out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable`
146	4	rudi
147			`always @(posedge clk)`
148	10	rudi	`in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid`
149	4	rudi
150			`always @(posedge clk)`
151	10	rudi	`in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid`
152	4	rudi
153			`always @(posedge clk)`
154	10	rudi	`in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid`
155	4	rudi
156			`////////////////////////////////////////////////////////////////////`
157			`//`
158			`// Suspend Detect`
159			`//`
160
161			`always @(posedge wclk)`
162			`bit_clk_r <= #1 clk;`
163
164			`always @(posedge wclk)`
165	14	rudi	`bit_clk_r1 <= #1 bit_clk_r;`
166	4	rudi
167			`always @(posedge wclk)`
168	14	rudi	`bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) \| (!bit_clk_r & bit_clk_r1);`
169
170			`always @(posedge wclk)`
171	4	rudi	`suspended <= #1 to;`
172
173			assign to = (to_cnt == `AC97_SUSP_DET);
174
175			`always @(posedge wclk or negedge rst)`
176	10	rudi	`if(!rst) to_cnt <= #1 6'h0;`
177	4	rudi	`else`
178	10	rudi	`if(bit_clk_e) to_cnt <= #1 6'h0;`
179	4	rudi	`else`
180	10	rudi	`if(!to) to_cnt <= #1 to_cnt + 6'h1;`
181	4	rudi
182			`////////////////////////////////////////////////////////////////////`
183			`//`
184			`// Resume Signaling`
185			`//`
186
187			`always @(posedge wclk or negedge rst)`
188	10	rudi	`if(!rst) sync_resume <= #1 1'b0;`
189	4	rudi	`else`
190	10	rudi	`if(resume_done) sync_resume <= #1 1'b0;`
191	4	rudi	`else`
192	10	rudi	`if(suspended & resume) sync_resume <= #1 1'b1;`
193	4	rudi
194			assign resume_done = (res_cnt == `AC97_RES_SIG);
195
196			`always @(posedge wclk)`
197	10	rudi	`if(!sync_resume) res_cnt <= #1 4'h0;`
198	4	rudi	`else`
199	10	rudi	`if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;`
200	4	rudi
201			`endmodule`

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_soc.v] - Blame information for rev 20