URL https://opencores.org/ocsvn/ac97/ac97/trunk

Subversion Repositories ac97

[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_soc.v] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Serial Output Controller                                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_soc.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
//  $Date: 2002-03-05 04:44:05 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:15  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_soc(clk, wclk, rst,
                ps_ce, resume, suspended,
                sync, out_le, in_valid, ld, valid
                );
 
input           clk, wclk, rst;
input           ps_ce;
input           resume;
output          suspended;
output          sync;
output  [5:0]    out_le;
output  [2:0]    in_valid;
output          ld;
output          valid;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [7:0]    cnt;
reg             sync_beat;
reg             sync_resume;
reg     [5:0]    out_le;
reg             ld;
reg             valid;
reg     [2:0]    in_valid;
reg             bit_clk_r;
reg             bit_clk_e;
reg             suspended;
wire            to;
reg     [5:0]    to_cnt;
reg     [3:0]    res_cnt;
wire            resume_done;
 
assign sync = sync_beat | sync_resume;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk or negedge rst)
        if(!rst)                cnt <= #1 8'hff;
        else
        if(suspended)           cnt <= #1 8'hff;
        else                    cnt <= #1 cnt + 8'h1;
 
always @(posedge clk)
        ld <= #1 (cnt == 8'h00);
 
always @(posedge clk)
        sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
 
always @(posedge clk)
        valid <= #1 (cnt > 8'h39);
 
always @(posedge clk)
        out_le[0] <= #1 (cnt == 8'h11);          // Slot 0 Latch Enable
 
always @(posedge clk)
        out_le[1] <= #1 (cnt == 8'h25);         // Slot 1 Latch Enable
 
always @(posedge clk)
        out_le[2] <= #1 (cnt == 8'h39);         // Slot 2 Latch Enable
 
always @(posedge clk)
        out_le[3] <= #1 (cnt == 8'h4d);         // Slot 3 Latch Enable
 
always @(posedge clk)
        out_le[4] <= #1 (cnt == 8'h61);         // Slot 4 Latch Enable
 
always @(posedge clk)
        out_le[5] <= #1 (cnt == 8'h89);         // Slot 6 Latch Enable
 
always @(posedge clk)
        in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
 
always @(posedge clk)
        in_valid[1] <= #1 (cnt > 8'h61);        // Input Slot 3 Valid
 
always @(posedge clk)
        in_valid[2] <= #1 (cnt > 8'h89);        // Input Slot 3 Valid
 
////////////////////////////////////////////////////////////////////
//
// Suspend Detect
//
 
always @(posedge wclk)
        bit_clk_r <= #1 clk;
 
always @(posedge wclk)
        bit_clk_e <= #1 (clk & !bit_clk_r) | (!clk & bit_clk_r);
 
always @(posedge wclk)
        suspended <= #1 to;
 
assign to = (to_cnt == `AC97_SUSP_DET);
 
always @(posedge wclk or negedge rst)
        if(!rst)                to_cnt <= #1 6'h0;
        else
        if(bit_clk_e)           to_cnt <= #1 6'h0;
        else
        if(!to)                 to_cnt <= #1 to_cnt + 6'h1;
 
////////////////////////////////////////////////////////////////////
//
// Resume Signaling
//
 
always @(posedge wclk or negedge rst)
        if(!rst)                        sync_resume <= #1 1'b0;
        else
        if(resume_done)                 sync_resume <= #1 1'b0;
        else
        if(suspended & resume)          sync_resume <= #1 1'b1;
 
assign resume_done = (res_cnt == `AC97_RES_SIG);
 
always @(posedge wclk)
        if(!sync_resume)        res_cnt <= #1 4'h0;
        else
        if(ps_ce)               res_cnt <= #1 res_cnt + 4'h1;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Serial Output Controller ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	10	rudi	`// $Id: ac97_soc.v,v 1.2 2002-03-05 04:44:05 rudi Exp $`
42	4	rudi	`//`
43	10	rudi	`// $Date: 2002-03-05 04:44:05 $`
44			`// $Revision: 1.2 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	10	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
52			`//`
53			`//`
54			`// - Changed to new directory structure`
55			`//`
56	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:15 rudi`
57			`// Initial Checkin`
58			`//`
59			`//`
60			`//`
61			`//`
62
63			`include "ac97_defines.v"
64
65			`module ac97_soc(clk, wclk, rst,`
66			`ps_ce, resume, suspended,`
67			`sync, out_le, in_valid, ld, valid`
68			`);`
69
70			`input clk, wclk, rst;`
71			`input ps_ce;`
72			`input resume;`
73			`output suspended;`
74			`output sync;`
75			`output [5:0] out_le;`
76			`output [2:0] in_valid;`
77			`output ld;`
78			`output valid;`
79
80			`////////////////////////////////////////////////////////////////////`
81			`//`
82			`// Local Wires`
83			`//`
84
85			`reg [7:0] cnt;`
86			`reg sync_beat;`
87			`reg sync_resume;`
88			`reg [5:0] out_le;`
89			`reg ld;`
90			`reg valid;`
91			`reg [2:0] in_valid;`
92			`reg bit_clk_r;`
93			`reg bit_clk_e;`
94			`reg suspended;`
95			`wire to;`
96			`reg [5:0] to_cnt;`
97			`reg [3:0] res_cnt;`
98			`wire resume_done;`
99
100			`assign sync = sync_beat \| sync_resume;`
101
102			`////////////////////////////////////////////////////////////////////`
103			`//`
104			`// Misc Logic`
105			`//`
106
107			`always @(posedge clk or negedge rst)`
108			`if(!rst) cnt <= #1 8'hff;`
109			`else`
110			`if(suspended) cnt <= #1 8'hff;`
111	10	rudi	`else cnt <= #1 cnt + 8'h1;`
112	4	rudi
113			`always @(posedge clk)`
114			`ld <= #1 (cnt == 8'h00);`
115
116			`always @(posedge clk)`
117	10	rudi	`sync_beat <= #1 (cnt == 8'h00) \| ((cnt > 8'h00) & (cnt < 8'h10));`
118	4	rudi
119			`always @(posedge clk)`
120	10	rudi	`valid <= #1 (cnt > 8'h39);`
121	4	rudi
122			`always @(posedge clk)`
123	10	rudi	`out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable`
124	4	rudi
125			`always @(posedge clk)`
126	10	rudi	`out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable`
127	4	rudi
128			`always @(posedge clk)`
129	10	rudi	`out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable`
130	4	rudi
131			`always @(posedge clk)`
132	10	rudi	`out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable`
133	4	rudi
134			`always @(posedge clk)`
135	10	rudi	`out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable`
136	4	rudi
137			`always @(posedge clk)`
138	10	rudi	`out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable`
139	4	rudi
140			`always @(posedge clk)`
141	10	rudi	`in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid`
142	4	rudi
143			`always @(posedge clk)`
144	10	rudi	`in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid`
145	4	rudi
146			`always @(posedge clk)`
147	10	rudi	`in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid`
148	4	rudi
149			`////////////////////////////////////////////////////////////////////`
150			`//`
151			`// Suspend Detect`
152			`//`
153
154			`always @(posedge wclk)`
155			`bit_clk_r <= #1 clk;`
156
157			`always @(posedge wclk)`
158			`bit_clk_e <= #1 (clk & !bit_clk_r) \| (!clk & bit_clk_r);`
159
160			`always @(posedge wclk)`
161			`suspended <= #1 to;`
162
163			assign to = (to_cnt == `AC97_SUSP_DET);
164
165			`always @(posedge wclk or negedge rst)`
166	10	rudi	`if(!rst) to_cnt <= #1 6'h0;`
167	4	rudi	`else`
168	10	rudi	`if(bit_clk_e) to_cnt <= #1 6'h0;`
169	4	rudi	`else`
170	10	rudi	`if(!to) to_cnt <= #1 to_cnt + 6'h1;`
171	4	rudi
172			`////////////////////////////////////////////////////////////////////`
173			`//`
174			`// Resume Signaling`
175			`//`
176
177			`always @(posedge wclk or negedge rst)`
178	10	rudi	`if(!rst) sync_resume <= #1 1'b0;`
179	4	rudi	`else`
180	10	rudi	`if(resume_done) sync_resume <= #1 1'b0;`
181	4	rudi	`else`
182	10	rudi	`if(suspended & resume) sync_resume <= #1 1'b1;`
183	4	rudi
184			assign resume_done = (res_cnt == `AC97_RES_SIG);
185
186			`always @(posedge wclk)`
187	10	rudi	`if(!sync_resume) res_cnt <= #1 4'h0;`
188	4	rudi	`else`
189	10	rudi	`if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;`
190	4	rudi
191			`endmodule`

Browse

Tools

Subversion Repositories ac97

[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_soc.v] - Blame information for rev 10