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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_soc.v] - Blame information for rev 4

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Serial Output Controller                                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_soc.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
//
//  $Date: 2001-08-03 06:54:50 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2001/05/19 02:29:15  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_soc(clk, wclk, rst,
                ps_ce, resume, suspended,
                sync, out_le, in_valid, ld, valid
                );
 
input           clk, wclk, rst;
input           ps_ce;
input           resume;
output          suspended;
output          sync;
output  [5:0]    out_le;
output  [2:0]    in_valid;
output          ld;
output          valid;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [7:0]    cnt;
reg             sync_beat;
reg             sync_resume;
reg     [5:0]    out_le;
reg             ld;
reg             valid;
reg     [2:0]    in_valid;
reg             bit_clk_r;
reg             bit_clk_e;
reg             suspended;
wire            to;
reg     [5:0]    to_cnt;
reg     [3:0]    res_cnt;
wire            resume_done;
 
assign sync = sync_beat | sync_resume;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk or negedge rst)
        if(!rst)                cnt <= #1 8'hff;
        else
        if(suspended)           cnt <= #1 8'hff;
        else                    cnt <= #1 cnt + 1;
 
always @(posedge clk)
        ld <= #1 (cnt == 8'h00);
 
always @(posedge clk)
        sync_beat <= #1 (cnt == 8'h00) | ((cnt > 0) & (cnt < 16));
 
always @(posedge clk)
        valid <= #1 (cnt > 57);
 
always @(posedge clk)
        out_le[0] <= #1 (cnt == 8'd17);          // Slot 0 Latch Enable
 
always @(posedge clk)
        out_le[1] <= #1 (cnt == 8'd37);         // Slot 1 Latch Enable
 
always @(posedge clk)
        out_le[2] <= #1 (cnt == 8'd57);         // Slot 2 Latch Enable
 
always @(posedge clk)
        out_le[3] <= #1 (cnt == 8'd77);         // Slot 3 Latch Enable
 
always @(posedge clk)
        out_le[4] <= #1 (cnt == 8'd97);         // Slot 4 Latch Enable
 
always @(posedge clk)
        out_le[5] <= #1 (cnt == 8'd137);        // Slot 6 Latch Enable
 
always @(posedge clk)
        in_valid[0] <= #1 (cnt > 8'd77); // Input Slot 3 Valid
 
always @(posedge clk)
        in_valid[1] <= #1 (cnt > 8'd97);        // Input Slot 3 Valid
 
always @(posedge clk)
        in_valid[2] <= #1 (cnt > 8'd137);       // Input Slot 3 Valid
 
////////////////////////////////////////////////////////////////////
//
// Suspend Detect
//
 
always @(posedge wclk)
        bit_clk_r <= #1 clk;
 
always @(posedge wclk)
        bit_clk_e <= #1 (clk & !bit_clk_r) | (!clk & bit_clk_r);
 
always @(posedge wclk)
        suspended <= #1 to;
 
assign to = (to_cnt == `AC97_SUSP_DET);
 
always @(posedge wclk or negedge rst)
        if(!rst)                to_cnt <= #1 0;
        else
        if(bit_clk_e)           to_cnt <= #1 0;
        else
        if(!to)                 to_cnt <= #1 to_cnt + 1;
 
////////////////////////////////////////////////////////////////////
//
// Resume Signaling
//
 
always @(posedge wclk or negedge rst)
        if(!rst)                        sync_resume <= #1 0;
        else
        if(resume_done)                 sync_resume <= #1 0;
        else
        if(suspended & resume)          sync_resume <= #1 1;
 
assign resume_done = (res_cnt == `AC97_RES_SIG);
 
always @(posedge wclk)
        if(!sync_resume)        res_cnt <= #1 0;
        else
        if(ps_ce)               res_cnt <= #1 res_cnt + 1;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Serial Output Controller ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: ac97_soc.v,v 1.1 2001-08-03 06:54:50 rudi Exp $`
42			`//`
43			`// $Date: 2001-08-03 06:54:50 $`
44			`// $Revision: 1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.1.1.1 2001/05/19 02:29:15 rudi`
52			`// Initial Checkin`
53			`//`
54			`//`
55			`//`
56			`//`
57
58			`include "ac97_defines.v"
59
60			`module ac97_soc(clk, wclk, rst,`
61			`ps_ce, resume, suspended,`
62			`sync, out_le, in_valid, ld, valid`
63			`);`
64
65			`input clk, wclk, rst;`
66			`input ps_ce;`
67			`input resume;`
68			`output suspended;`
69			`output sync;`
70			`output [5:0] out_le;`
71			`output [2:0] in_valid;`
72			`output ld;`
73			`output valid;`
74
75			`////////////////////////////////////////////////////////////////////`
76			`//`
77			`// Local Wires`
78			`//`
79
80			`reg [7:0] cnt;`
81			`reg sync_beat;`
82			`reg sync_resume;`
83			`reg [5:0] out_le;`
84			`reg ld;`
85			`reg valid;`
86			`reg [2:0] in_valid;`
87			`reg bit_clk_r;`
88			`reg bit_clk_e;`
89			`reg suspended;`
90			`wire to;`
91			`reg [5:0] to_cnt;`
92			`reg [3:0] res_cnt;`
93			`wire resume_done;`
94
95			`assign sync = sync_beat \| sync_resume;`
96
97			`////////////////////////////////////////////////////////////////////`
98			`//`
99			`// Misc Logic`
100			`//`
101
102			`always @(posedge clk or negedge rst)`
103			`if(!rst) cnt <= #1 8'hff;`
104			`else`
105			`if(suspended) cnt <= #1 8'hff;`
106			`else cnt <= #1 cnt + 1;`
107
108			`always @(posedge clk)`
109			`ld <= #1 (cnt == 8'h00);`
110
111			`always @(posedge clk)`
112			`sync_beat <= #1 (cnt == 8'h00) \| ((cnt > 0) & (cnt < 16));`
113
114			`always @(posedge clk)`
115			`valid <= #1 (cnt > 57);`
116
117			`always @(posedge clk)`
118			`out_le[0] <= #1 (cnt == 8'd17); // Slot 0 Latch Enable`
119
120			`always @(posedge clk)`
121			`out_le[1] <= #1 (cnt == 8'd37); // Slot 1 Latch Enable`
122
123			`always @(posedge clk)`
124			`out_le[2] <= #1 (cnt == 8'd57); // Slot 2 Latch Enable`
125
126			`always @(posedge clk)`
127			`out_le[3] <= #1 (cnt == 8'd77); // Slot 3 Latch Enable`
128
129			`always @(posedge clk)`
130			`out_le[4] <= #1 (cnt == 8'd97); // Slot 4 Latch Enable`
131
132			`always @(posedge clk)`
133			`out_le[5] <= #1 (cnt == 8'd137); // Slot 6 Latch Enable`
134
135			`always @(posedge clk)`
136			`in_valid[0] <= #1 (cnt > 8'd77); // Input Slot 3 Valid`
137
138			`always @(posedge clk)`
139			`in_valid[1] <= #1 (cnt > 8'd97); // Input Slot 3 Valid`
140
141			`always @(posedge clk)`
142			`in_valid[2] <= #1 (cnt > 8'd137); // Input Slot 3 Valid`
143
144			`////////////////////////////////////////////////////////////////////`
145			`//`
146			`// Suspend Detect`
147			`//`
148
149			`always @(posedge wclk)`
150			`bit_clk_r <= #1 clk;`
151
152			`always @(posedge wclk)`
153			`bit_clk_e <= #1 (clk & !bit_clk_r) \| (!clk & bit_clk_r);`
154
155			`always @(posedge wclk)`
156			`suspended <= #1 to;`
157
158			assign to = (to_cnt == `AC97_SUSP_DET);
159
160			`always @(posedge wclk or negedge rst)`
161			`if(!rst) to_cnt <= #1 0;`
162			`else`
163			`if(bit_clk_e) to_cnt <= #1 0;`
164			`else`
165			`if(!to) to_cnt <= #1 to_cnt + 1;`
166
167			`////////////////////////////////////////////////////////////////////`
168			`//`
169			`// Resume Signaling`
170			`//`
171
172			`always @(posedge wclk or negedge rst)`
173			`if(!rst) sync_resume <= #1 0;`
174			`else`
175			`if(resume_done) sync_resume <= #1 0;`
176			`else`
177			`if(suspended & resume) sync_resume <= #1 1;`
178
179			assign resume_done = (res_cnt == `AC97_RES_SIG);
180
181			`always @(posedge wclk)`
182			`if(!sync_resume) res_cnt <= #1 0;`
183			`else`
184			`if(ps_ce) res_cnt <= #1 res_cnt + 1;`
185
186			`endmodule`

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_soc.v] - Blame information for rev 4