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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_sout.v] - Blame information for rev 20

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Serial Output Block                                        ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_sout.v,v 1.2 2002-09-19 06:30:56 rudi Exp $
//
//  $Date: 2002-09-19 06:30:56 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:15  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_sout(clk, rst,
 
        so_ld, slt0, slt1, slt2, slt3, slt4,
        slt6, slt7, slt8, slt9,
 
        sdata_out
        );
 
input           clk, rst;
 
// --------------------------------------
// Misc Signals
input           so_ld;
input   [15:0]   slt0;
input   [19:0]   slt1;
input   [19:0]   slt2;
input   [19:0]   slt3;
input   [19:0]   slt4;
input   [19:0]   slt6;
input   [19:0]   slt7;
input   [19:0]   slt8;
input   [19:0]   slt9;
 
// --------------------------------------
// AC97 Codec Interface
output          sdata_out;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
wire            sdata_out;
 
reg     [15:0]   slt0_r;
reg     [19:0]   slt1_r;
reg     [19:0]   slt2_r;
reg     [19:0]   slt3_r;
reg     [19:0]   slt4_r;
reg     [19:0]   slt5_r;
reg     [19:0]   slt6_r;
reg     [19:0]   slt7_r;
reg     [19:0]   slt8_r;
reg     [19:0]   slt9_r;
reg     [19:0]   slt10_r;
reg     [19:0]   slt11_r;
reg     [19:0]   slt12_r;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
////////////////////////////////////////////////////////////////////
//
// Serial Shift Register
//
 
assign  sdata_out = slt0_r[15];
 
always @(posedge clk)
        if(so_ld)       slt0_r <= #1 slt0;
        else            slt0_r <= #1 {slt0_r[14:0], slt1_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt1_r <= #1 slt1;
        else            slt1_r <= #1 {slt1_r[18:0], slt2_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt2_r <= #1 slt2;
        else            slt2_r <= #1 {slt2_r[18:0], slt3_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt3_r <= #1 slt3;
        else            slt3_r <= #1 {slt3_r[18:0], slt4_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt4_r <= #1 slt4;
        else            slt4_r <= #1 {slt4_r[18:0], slt5_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt5_r <= #1 20'h0;
        else            slt5_r <= #1 {slt5_r[18:0], slt6_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt6_r <= #1 slt6;
        else            slt6_r <= #1 {slt6_r[18:0], slt7_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt7_r <= #1 slt7;
        else            slt7_r <= #1 {slt7_r[18:0], slt8_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt8_r <= #1 slt8;
        else            slt8_r <= #1 {slt8_r[18:0], slt9_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt9_r <= #1 slt9;
        else            slt9_r <= #1 {slt9_r[18:0], slt10_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt10_r <= #1 20'h0;
        else            slt10_r <= #1 {slt10_r[18:0], slt11_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt11_r <= #1 20'h0;
        else            slt11_r <= #1 {slt11_r[18:0], slt12_r[19]};
 
always @(posedge clk)
        if(so_ld)       slt12_r <= #1 20'h0;
        else            slt12_r <= #1 {slt12_r[18:0], 1'b0 };
 
endmodule
 

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Serial Output Block ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	14	rudi	`// $Id: ac97_sout.v,v 1.2 2002-09-19 06:30:56 rudi Exp $`
43	4	rudi	`//`
44	14	rudi	`// $Date: 2002-09-19 06:30:56 $`
45			`// $Revision: 1.2 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	14	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
53			`//`
54			`//`
55			`// - Changed to new directory structure`
56			`//`
57	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:15 rudi`
58			`// Initial Checkin`
59			`//`
60			`//`
61			`//`
62			`//`
63
64			`include "ac97_defines.v"
65
66			`module ac97_sout(clk, rst,`
67
68			`so_ld, slt0, slt1, slt2, slt3, slt4,`
69			`slt6, slt7, slt8, slt9,`
70
71			`sdata_out`
72			`);`
73
74			`input clk, rst;`
75
76			`// --------------------------------------`
77			`// Misc Signals`
78			`input so_ld;`
79			`input [15:0] slt0;`
80			`input [19:0] slt1;`
81			`input [19:0] slt2;`
82			`input [19:0] slt3;`
83			`input [19:0] slt4;`
84			`input [19:0] slt6;`
85			`input [19:0] slt7;`
86			`input [19:0] slt8;`
87			`input [19:0] slt9;`
88
89			`// --------------------------------------`
90			`// AC97 Codec Interface`
91			`output sdata_out;`
92
93			`////////////////////////////////////////////////////////////////////`
94			`//`
95			`// Local Wires`
96			`//`
97
98			`wire sdata_out;`
99
100			`reg [15:0] slt0_r;`
101			`reg [19:0] slt1_r;`
102			`reg [19:0] slt2_r;`
103			`reg [19:0] slt3_r;`
104			`reg [19:0] slt4_r;`
105			`reg [19:0] slt5_r;`
106			`reg [19:0] slt6_r;`
107			`reg [19:0] slt7_r;`
108			`reg [19:0] slt8_r;`
109			`reg [19:0] slt9_r;`
110			`reg [19:0] slt10_r;`
111			`reg [19:0] slt11_r;`
112			`reg [19:0] slt12_r;`
113
114			`////////////////////////////////////////////////////////////////////`
115			`//`
116			`// Misc Logic`
117			`//`
118
119			`////////////////////////////////////////////////////////////////////`
120			`//`
121			`// Serial Shift Register`
122			`//`
123
124			`assign sdata_out = slt0_r[15];`
125
126			`always @(posedge clk)`
127			`if(so_ld) slt0_r <= #1 slt0;`
128			`else slt0_r <= #1 {slt0_r[14:0], slt1_r[19]};`
129
130			`always @(posedge clk)`
131			`if(so_ld) slt1_r <= #1 slt1;`
132			`else slt1_r <= #1 {slt1_r[18:0], slt2_r[19]};`
133
134			`always @(posedge clk)`
135			`if(so_ld) slt2_r <= #1 slt2;`
136			`else slt2_r <= #1 {slt2_r[18:0], slt3_r[19]};`
137
138			`always @(posedge clk)`
139			`if(so_ld) slt3_r <= #1 slt3;`
140			`else slt3_r <= #1 {slt3_r[18:0], slt4_r[19]};`
141
142			`always @(posedge clk)`
143			`if(so_ld) slt4_r <= #1 slt4;`
144			`else slt4_r <= #1 {slt4_r[18:0], slt5_r[19]};`
145
146			`always @(posedge clk)`
147			`if(so_ld) slt5_r <= #1 20'h0;`
148			`else slt5_r <= #1 {slt5_r[18:0], slt6_r[19]};`
149
150			`always @(posedge clk)`
151			`if(so_ld) slt6_r <= #1 slt6;`
152			`else slt6_r <= #1 {slt6_r[18:0], slt7_r[19]};`
153
154			`always @(posedge clk)`
155			`if(so_ld) slt7_r <= #1 slt7;`
156			`else slt7_r <= #1 {slt7_r[18:0], slt8_r[19]};`
157
158			`always @(posedge clk)`
159			`if(so_ld) slt8_r <= #1 slt8;`
160			`else slt8_r <= #1 {slt8_r[18:0], slt9_r[19]};`
161
162			`always @(posedge clk)`
163			`if(so_ld) slt9_r <= #1 slt9;`
164			`else slt9_r <= #1 {slt9_r[18:0], slt10_r[19]};`
165
166			`always @(posedge clk)`
167			`if(so_ld) slt10_r <= #1 20'h0;`
168			`else slt10_r <= #1 {slt10_r[18:0], slt11_r[19]};`
169
170			`always @(posedge clk)`
171			`if(so_ld) slt11_r <= #1 20'h0;`
172			`else slt11_r <= #1 {slt11_r[18:0], slt12_r[19]};`
173
174			`always @(posedge clk)`
175			`if(so_ld) slt12_r <= #1 20'h0;`
176			`else slt12_r <= #1 {slt12_r[18:0], 1'b0 };`
177
178			`endmodule`
179

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_sout.v] - Blame information for rev 20