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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller Top Level                        ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_top.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
//
//  $Date: 2002-03-05 04:44:05 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2001/08/10 08:09:42  rudi
//
//               - Removed RTY_O output.
//               - Added Clock and Reset Inputs to documentation.
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:14  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_top(clk_i, rst_i,
 
        wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
        wb_stb_i, wb_ack_o, wb_err_o,
 
        int_o, dma_req_o, dma_ack_i,
        suspended_o,
 
        bit_clk_pad_i, sync_pad_o, sdata_pad_o, sdata_pad_i,
        ac97_reset_pad_o_
        );
 
input           clk_i, rst_i;
 
// --------------------------------------
// WISHBONE SLAVE INTERFACE 
input   [31:0]   wb_data_i;
output  [31:0]   wb_data_o;
input   [31:0]   wb_addr_i;
input   [3:0]    wb_sel_i;
input           wb_we_i;
input           wb_cyc_i;
input           wb_stb_i;
output          wb_ack_o;
output          wb_err_o;
 
// --------------------------------------
// Misc Signals
output          int_o;
output  [8:0]    dma_req_o;
input   [8:0]    dma_ack_i;
 
// --------------------------------------
// Suspend Resume Interface
output          suspended_o;
 
// --------------------------------------
// AC97 Codec Interface
input           bit_clk_pad_i;
output          sync_pad_o;
output          sdata_pad_o;
input           sdata_pad_i;
output          ac97_reset_pad_o_;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
// Serial Output register interface
wire    [15:0]   out_slt0;
wire    [19:0]   out_slt1;
wire    [19:0]   out_slt2;
wire    [19:0]   out_slt3;
wire    [19:0]   out_slt4;
wire    [19:0]   out_slt6;
wire    [19:0]   out_slt7;
wire    [19:0]   out_slt8;
wire    [19:0]   out_slt9;
 
// Serial Input register interface
wire    [15:0]   in_slt0;
wire    [19:0]   in_slt1;
wire    [19:0]   in_slt2;
wire    [19:0]   in_slt3;
wire    [19:0]   in_slt4;
wire    [19:0]   in_slt6;
 
// Serial IO Controller Interface
wire            ld;
wire            valid;
wire    [5:0]    out_le;
wire    [2:0]    in_valid;
wire            ps_ce;
 
// Valid Sync
reg             valid_s1, valid_s;
reg     [2:0]    in_valid_s1, in_valid_s;
 
// Out FIFO interface
wire    [31:0]   wb_din;
wire    [1:0]    o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode;
wire            o3_re, o4_re, o6_re, o7_re, o8_re, o9_re;
wire            o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
wire    [1:0]    o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;
wire            o3_full, o4_full, o6_full, o7_full, o8_full, o9_full;
wire            o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;
 
// In FIFO interface
wire    [31:0]   i3_dout, i4_dout, i6_dout;
wire    [1:0]    i3_mode, i4_mode, i6_mode;
wire            i3_we, i4_we, i6_we;
wire            i3_re, i4_re, i6_re;
wire    [1:0]    i3_status, i4_status, i6_status;
wire            i3_full, i4_full, i6_full;
wire            i3_empty, i4_empty, i6_empty;
 
// Register File Interface
wire    [3:0]    adr;
wire    [31:0]   rf_dout;
wire    [31:0]   rf_din;
wire            rf_we;
wire            rf_re;
wire            ac97_rst_force;
wire            resume_req;
wire            crac_we;
wire    [15:0]   crac_din;
wire    [31:0]   crac_out;
wire    [7:0]    oc0_cfg;
wire    [7:0]    oc1_cfg;
wire    [7:0]    oc2_cfg;
wire    [7:0]    oc3_cfg;
wire    [7:0]    oc4_cfg;
wire    [7:0]    oc5_cfg;
wire    [7:0]    ic0_cfg;
wire    [7:0]    ic1_cfg;
wire    [7:0]    ic2_cfg;
wire    [2:0]    oc0_int_set;
wire    [2:0]    oc1_int_set;
wire    [2:0]    oc2_int_set;
wire    [2:0]    oc3_int_set;
wire    [2:0]    oc4_int_set;
wire    [2:0]    oc5_int_set;
wire    [2:0]    ic0_int_set;
wire    [2:0]    ic1_int_set;
wire    [2:0]    ic2_int_set;
 
// CRA Module interface
wire            crac_valid;
wire            crac_wr;
wire            crac_wr_done, crac_rd_done;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
// Sync Valid to WISHBONE Clock
always @(posedge clk_i)
        valid_s1 <= #1 valid;
 
always @(posedge clk_i)
        valid_s <= #1 valid_s1;
 
always @(posedge clk_i)
        in_valid_s1 <= #1 in_valid;
 
always @(posedge clk_i)
        in_valid_s <= #1 in_valid_s1;
 
// "valid_s" Indicates when any of the outputs to the output S/R may
// change or when outputs from input S/R may be sampled
assign o3_mode = oc0_cfg[3:2];
assign o4_mode = oc1_cfg[3:2];
assign o6_mode = oc2_cfg[3:2];
assign o7_mode = oc3_cfg[3:2];
assign o8_mode = oc4_cfg[3:2];
assign o9_mode = oc5_cfg[3:2];
assign i3_mode = ic0_cfg[3:2];
assign i4_mode = ic1_cfg[3:2];
assign i6_mode = ic2_cfg[3:2];
 
////////////////////////////////////////////////////////////////////
//
// Modules
//
 
ac97_sout       u0(
                .clk(           bit_clk_pad_i   ),
                .rst(           rst_i           ),
                .so_ld(         ld              ),
                .slt0(          out_slt0        ),
                .slt1(          out_slt1        ),
                .slt2(          out_slt2        ),
                .slt3(          out_slt3        ),
                .slt4(          out_slt4        ),
                .slt6(          out_slt6        ),
                .slt7(          out_slt7        ),
                .slt8(          out_slt8        ),
                .slt9(          out_slt9        ),
                .sdata_out(     sdata_pad_o     )
                );
 
ac97_sin        u1(
                .clk(           bit_clk_pad_i   ),
                .rst(           rst_i           ),
                .out_le(        out_le          ),
                .slt0(          in_slt0         ),
                .slt1(          in_slt1         ),
                .slt2(          in_slt2         ),
                .slt3(          in_slt3         ),
                .slt4(          in_slt4         ),
                .slt6(          in_slt6         ),
                .sdata_in(      sdata_pad_i     )
                );
 
ac97_soc        u2(
                .clk(           bit_clk_pad_i   ),
                .wclk(          clk_i           ),
                .rst(           rst_i           ),
                .ps_ce(         ps_ce           ),
                .resume(        resume_req      ),
                .suspended(     suspended_o     ),
                .sync(          sync_pad_o      ),
                .out_le(        out_le          ),
                .in_valid(      in_valid        ),
                .ld(            ld              ),
                .valid(         valid           )
                );
 
ac97_out_fifo   u3(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc0_cfg[0]       ),
                .mode(          o3_mode         ),
                .din(           wb_din          ),
                .we(            o3_we           ),
                .dout(          out_slt3        ),
                .re(            o3_re           ),
                .status(        o3_status       ),
                .full(          o3_full         ),
                .empty(         o3_empty        )
                );
 
ac97_out_fifo   u4(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc1_cfg[0]       ),
                .mode(          o4_mode         ),
                .din(           wb_din          ),
                .we(            o4_we           ),
                .dout(          out_slt4        ),
                .re(            o4_re           ),
                .status(        o4_status       ),
                .full(          o4_full         ),
                .empty(         o4_empty        )
                );
 
`ifdef AC97_CENTER
ac97_out_fifo   u5(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc2_cfg[0]       ),
                .mode(          o6_mode         ),
                .din(           wb_din          ),
                .we(            o6_we           ),
                .dout(          out_slt6        ),
                .re(            o6_re           ),
                .status(        o6_status       ),
                .full(          o6_full         ),
                .empty(         o6_empty        )
                );
`else
assign out_slt6 = 20'h0;
assign o6_status = 2'h0;
assign o6_full = 1'b0;
assign o6_empty = 1'b0;
`endif
 
`ifdef AC97_SURROUND
ac97_out_fifo   u6(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc3_cfg[0]       ),
                .mode(          o7_mode         ),
                .din(           wb_din          ),
                .we(            o7_we           ),
                .dout(          out_slt7        ),
                .re(            o7_re           ),
                .status(        o7_status       ),
                .full(          o7_full         ),
                .empty(         o7_empty        )
                );
 
ac97_out_fifo   u7(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc4_cfg[0]       ),
                .mode(          o8_mode         ),
                .din(           wb_din          ),
                .we(            o8_we           ),
                .dout(          out_slt8        ),
                .re(            o8_re           ),
                .status(        o8_status       ),
                .full(          o8_full         ),
                .empty(         o8_empty        )
                );
`else
assign out_slt7 = 20'h0;
assign o7_status = 2'h0;
assign o7_full = 1'b0;
assign o7_empty = 1'b0;
assign out_slt8 = 20'h0;
assign o8_status = 2'h0;
assign o8_full = 1'b0;
assign o8_empty = 1'b0;
`endif
 
`ifdef AC97_LFE
ac97_out_fifo   u8(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc5_cfg[0]       ),
                .mode(          o9_mode         ),
                .din(           wb_din          ),
                .we(            o9_we           ),
                .dout(          out_slt9        ),
                .re(            o9_re           ),
                .status(        o9_status       ),
                .full(          o9_full         ),
                .empty(         o9_empty        )
                );
`else
assign out_slt9 = 20'h0;
assign o9_status = 2'h0;
assign o9_full = 1'b0;
assign o9_empty = 1'b0;
`endif
 
`ifdef AC97_SIN
ac97_in_fifo    u9(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            ic0_cfg[0]       ),
                .mode(          i3_mode         ),
                .din(           in_slt3         ),
                .we(            i3_we           ),
                .dout(          i3_dout         ),
                .re(            i3_re           ),
                .status(        i3_status       ),
                .full(          i3_full         ),
                .empty(         i3_empty        )
                );
 
ac97_in_fifo    u10(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            ic1_cfg[0]       ),
                .mode(          i4_mode         ),
                .din(           in_slt4         ),
                .we(            i4_we           ),
                .dout(          i4_dout         ),
                .re(            i4_re           ),
                .status(        i4_status       ),
                .full(          i4_full         ),
                .empty(         i4_empty        )
                );
`else
assign i3_dout = 20'h0;
assign i3_status = 2'h0;
assign i3_full = 1'b0;
assign i3_empty = 1'b0;
assign i4_dout = 20'h0;
assign i4_status = 2'h0;
assign i4_full = 1'b0;
assign i4_empty = 1'b0;
`endif
 
`ifdef AC97_MICIN
ac97_in_fifo    u11(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            ic2_cfg[0]       ),
                .mode(          i6_mode         ),
                .din(           in_slt6         ),
                .we(            i6_we           ),
                .dout(          i6_dout         ),
                .re(            i6_re           ),
                .status(        i6_status       ),
                .full(          i6_full         ),
                .empty(         i6_empty        )
                );
`else
assign i6_dout = 20'h0;
assign i6_status = 2'h0;
assign i6_full = 1'b0;
assign i6_empty = 1'b0;
`endif
 
ac97_wb_if      u12(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .wb_data_i(     wb_data_i       ),
                .wb_data_o(     wb_data_o       ),
                .wb_addr_i(     wb_addr_i       ),
                .wb_sel_i(      wb_sel_i        ),
                .wb_we_i(       wb_we_i         ),
                .wb_cyc_i(      wb_cyc_i        ),
                .wb_stb_i(      wb_stb_i        ),
                .wb_ack_o(      wb_ack_o        ),
                .wb_err_o(      wb_err_o        ),
                .adr(           adr             ),
                .dout(          wb_din          ),
                .rf_din(        rf_dout         ),
                .i3_din(        i3_dout         ),
                .i4_din(        i4_dout         ),
                .i6_din(        i6_dout         ),
                .rf_we(         rf_we           ),
                .rf_re(         rf_re           ),
                .o3_we(         o3_we           ),
                .o4_we(         o4_we           ),
                .o6_we(         o6_we           ),
                .o7_we(         o7_we           ),
                .o8_we(         o8_we           ),
                .o9_we(         o9_we           ),
                .i3_re(         i3_re           ),
                .i4_re(         i4_re           ),
                .i6_re(         i6_re           )
                );
 
ac97_rf u13(    .clk(           clk_i           ),
                .rst(           rst_i           ),
                .adr(           adr             ),
                .rf_dout(       rf_dout         ),
                .rf_din(        wb_din          ),
                .rf_we(         rf_we           ),
                .rf_re(         rf_re           ),
                .int(           int_o           ),
                .ac97_rst_force(ac97_rst_force  ),
                .resume_req(    resume_req      ),
                .suspended(     suspended_o     ),
                .crac_we(       crac_we         ),
                .crac_din(      crac_din        ),
                .crac_out(      crac_out        ),
                .crac_wr_done(  crac_wr_done    ),
                .crac_rd_done(  crac_rd_done    ),
                .oc0_cfg(       oc0_cfg         ),
                .oc1_cfg(       oc1_cfg         ),
                .oc2_cfg(       oc2_cfg         ),
                .oc3_cfg(       oc3_cfg         ),
                .oc4_cfg(       oc4_cfg         ),
                .oc5_cfg(       oc5_cfg         ),
                .ic0_cfg(       ic0_cfg         ),
                .ic1_cfg(       ic1_cfg         ),
                .ic2_cfg(       ic2_cfg         ),
                .oc0_int_set(   oc0_int_set     ),
                .oc1_int_set(   oc1_int_set     ),
                .oc2_int_set(   oc2_int_set     ),
                .oc3_int_set(   oc3_int_set     ),
                .oc4_int_set(   oc4_int_set     ),
                .oc5_int_set(   oc5_int_set     ),
                .ic0_int_set(   ic0_int_set     ),
                .ic1_int_set(   ic1_int_set     ),
                .ic2_int_set(   ic2_int_set     )
                );
 
ac97_prc u14(   .clk(           clk_i           ),
                .rst(           rst_i           ),
                .valid(         valid_s         ),
                .in_valid(      in_valid_s      ),
                .out_slt0(      out_slt0        ),
                .in_slt0(       in_slt0         ),
                .in_slt1(       in_slt1         ),
                .crac_valid(    crac_valid      ),
                .crac_wr(       crac_wr         ),
                .oc0_cfg(       oc0_cfg         ),
                .oc1_cfg(       oc1_cfg         ),
                .oc2_cfg(       oc2_cfg         ),
                .oc3_cfg(       oc3_cfg         ),
                .oc4_cfg(       oc4_cfg         ),
                .oc5_cfg(       oc5_cfg         ),
                .ic0_cfg(       ic0_cfg         ),
                .ic1_cfg(       ic1_cfg         ),
                .ic2_cfg(       ic2_cfg         ),
                .o3_empty(      o3_empty        ),
                .o4_empty(      o4_empty        ),
                .o6_empty(      o6_empty        ),
                .o7_empty(      o7_empty        ),
                .o8_empty(      o8_empty        ),
                .o9_empty(      o9_empty        ),
                .i3_full(       i3_full         ),
                .i4_full(       i4_full         ),
                .i6_full(       i6_full         ),
                .o3_re(         o3_re           ),
                .o4_re(         o4_re           ),
                .o6_re(         o6_re           ),
                .o7_re(         o7_re           ),
                .o8_re(         o8_re           ),
                .o9_re(         o9_re           ),
                .i3_we(         i3_we           ),
                .i4_we(         i4_we           ),
                .i6_we(         i6_we           )
                );
 
ac97_cra u15(   .clk(           clk_i           ),
                .rst(           rst_i           ),
                .crac_we(       crac_we         ),
                .crac_din(      crac_din        ),
                .crac_out(      crac_out        ),
                .crac_wr_done(  crac_wr_done    ),
                .crac_rd_done(  crac_rd_done    ),
                .valid(         valid_s         ),
                .out_slt1(      out_slt1        ),
                .out_slt2(      out_slt2        ),
                .in_slt2(       in_slt2         ),
                .crac_valid(    crac_valid      ),
                .crac_wr(       crac_wr         )
                );
 
ac97_dma_if u16(.clk(           clk_i           ),
                .rst(           rst_i           ),
                .o3_status(     o3_status       ),
                .o4_status(     o4_status       ),
                .o6_status(     o6_status       ),
                .o7_status(     o7_status       ),
                .o8_status(     o8_status       ),
                .o9_status(     o9_status       ),
                .o3_empty(      o3_empty        ),
                .o4_empty(      o4_empty        ),
                .o6_empty(      o6_empty        ),
                .o7_empty(      o7_empty        ),
                .o8_empty(      o8_empty        ),
                .o9_empty(      o9_empty        ),
                .i3_status(     i3_status       ),
                .i4_status(     i4_status       ),
                .i6_status(     i6_status       ),
                .i3_full(       i3_full         ),
                .i4_full(       i4_full         ),
                .i6_full(       i6_full         ),
                .oc0_cfg(       oc0_cfg         ),
                .oc1_cfg(       oc1_cfg         ),
                .oc2_cfg(       oc2_cfg         ),
                .oc3_cfg(       oc3_cfg         ),
                .oc4_cfg(       oc4_cfg         ),
                .oc5_cfg(       oc5_cfg         ),
                .ic0_cfg(       ic0_cfg         ),
                .ic1_cfg(       ic1_cfg         ),
                .ic2_cfg(       ic2_cfg         ),
                .dma_req(       dma_req_o       ),
                .dma_ack(       dma_ack_i       )
                );
 
ac97_int        u17(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc0_int_set     ),
                .cfg(           oc0_cfg         ),
                .status(        o3_status       ),
                .full_empty(    o3_empty        ),
                .full(          o3_full         ),
                .empty(         o3_empty        ),
                .re(            o3_re           ),
                .we(            o3_we           )
                );
 
ac97_int        u18(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc1_int_set     ),
                .cfg(           oc1_cfg         ),
                .status(        o4_status       ),
                .full_empty(    o4_empty        ),
                .full(          o4_full         ),
                .empty(         o4_empty        ),
                .re(            o4_re           ),
                .we(            o4_we           )
                );
 
`ifdef AC97_CENTER
ac97_int        u19(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc2_int_set     ),
                .cfg(           oc2_cfg         ),
                .status(        o6_status       ),
                .full_empty(    o6_empty        ),
                .full(          o6_full         ),
                .empty(         o6_empty        ),
                .re(            o6_re           ),
                .we(            o6_we           )
                );
`else
assign oc2_int_set = 1'b0;
`endif
 
`ifdef AC97_SURROUND
ac97_int        u20(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc3_int_set     ),
                .cfg(           oc3_cfg         ),
                .status(        o7_status       ),
                .full_empty(    o7_empty        ),
                .full(          o7_full         ),
                .empty(         o7_empty        ),
                .re(            o7_re           ),
                .we(            o7_we           )
                );
 
ac97_int        u21(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc4_int_set     ),
                .cfg(           oc4_cfg         ),
                .status(        o8_status       ),
                .full_empty(    o8_empty        ),
                .full(          o8_full         ),
                .empty(         o8_empty        ),
                .re(            o8_re           ),
                .we(            o8_we           )
                );
`else
assign oc3_int_set = 1'b0;
assign oc4_int_set = 1'b0;
`endif
 
`ifdef AC97_LFE
ac97_int        u22(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc5_int_set     ),
                .cfg(           oc5_cfg         ),
                .status(        o9_status       ),
                .full_empty(    o9_empty        ),
                .full(          o9_full         ),
                .empty(         o9_empty        ),
                .re(            o9_re           ),
                .we(            o9_we           )
                );
`else
assign oc5_int_set = 1'b0;
`endif
 
`ifdef AC97_SIN
ac97_int        u23(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       ic0_int_set     ),
                .cfg(           ic0_cfg         ),
                .status(        i3_status       ),
                .full_empty(    i3_full         ),
                .full(          i3_full         ),
                .empty(         i3_empty        ),
                .re(            i3_re           ),
                .we(            i3_we           )
                );
 
ac97_int        u24(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       ic1_int_set     ),
                .cfg(           ic1_cfg         ),
                .status(        i4_status       ),
                .full_empty(    i4_full         ),
                .full(          i4_full         ),
                .empty(         i4_empty        ),
                .re(            i4_re           ),
                .we(            i4_we           )
                );
`else
assign ic0_int_set = 1'b0;
assign ic1_int_set = 1'b0;
`endif
 
`ifdef AC97_MICIN
ac97_int        u25(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       ic2_int_set     ),
                .cfg(           ic2_cfg         ),
                .status(        i6_status       ),
                .full_empty(    i6_full         ),
                .full(          i6_full         ),
                .empty(         i6_empty        ),
                .re(            i6_re           ),
                .we(            i6_we           )
                );
`else
assign ic2_int_set = 1'b0;
`endif
 
ac97_rst        u26(
                .clk(           clk_i                           ),
                .rst(           rst_i                           ),
                .rst_force(     ac97_rst_force                  ),
                .ps_ce(         ps_ce                           ),
                .ac97_rst_(     ac97_reset_pad_o_               )
                );
 
endmodule
 

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller Top Level ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	10	rudi	`// $Id: ac97_top.v,v 1.3 2002-03-05 04:44:05 rudi Exp $`
41	4	rudi	`//`
42	10	rudi	`// $Date: 2002-03-05 04:44:05 $`
43			`// $Revision: 1.3 $`
44	4	rudi	`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	10	rudi	`// Revision 1.2 2001/08/10 08:09:42 rudi`
51			`//`
52			`// - Removed RTY_O output.`
53			`// - Added Clock and Reset Inputs to documentation.`
54			`// - Changed IO names to be more clear.`
55			`// - Uniquifyed define names to be core specific.`
56			`//`
57	6	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
58			`//`
59			`//`
60			`// - Changed to new directory structure`
61			`//`
62	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:14 rudi`
63			`// Initial Checkin`
64			`//`
65			`//`
66			`//`
67			`//`
68
69			`include "ac97_defines.v"
70
71	6	rudi	`module ac97_top(clk_i, rst_i,`
72	4	rudi
73			`wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
74			`wb_stb_i, wb_ack_o, wb_err_o,`
75
76	6	rudi	`int_o, dma_req_o, dma_ack_i,`
77			`suspended_o,`
78	4	rudi
79	6	rudi	`bit_clk_pad_i, sync_pad_o, sdata_pad_o, sdata_pad_i,`
80			`ac97_reset_pad_o_`
81	4	rudi	`);`
82
83	6	rudi	`input clk_i, rst_i;`
84	4	rudi
85			`// --------------------------------------`
86			`// WISHBONE SLAVE INTERFACE`
87			`input [31:0] wb_data_i;`
88			`output [31:0] wb_data_o;`
89			`input [31:0] wb_addr_i;`
90			`input [3:0] wb_sel_i;`
91			`input wb_we_i;`
92			`input wb_cyc_i;`
93			`input wb_stb_i;`
94			`output wb_ack_o;`
95			`output wb_err_o;`
96
97			`// --------------------------------------`
98			`// Misc Signals`
99	6	rudi	`output int_o;`
100			`output [8:0] dma_req_o;`
101			`input [8:0] dma_ack_i;`
102	4	rudi
103			`// --------------------------------------`
104			`// Suspend Resume Interface`
105	6	rudi	`output suspended_o;`
106	4	rudi
107			`// --------------------------------------`
108			`// AC97 Codec Interface`
109	6	rudi	`input bit_clk_pad_i;`
110			`output sync_pad_o;`
111			`output sdata_pad_o;`
112			`input sdata_pad_i;`
113			`output ac97_reset_pad_o_;`
114	4	rudi
115			`////////////////////////////////////////////////////////////////////`
116			`//`
117			`// Local Wires`
118			`//`
119
120			`// Serial Output register interface`
121			`wire [15:0] out_slt0;`
122			`wire [19:0] out_slt1;`
123			`wire [19:0] out_slt2;`
124			`wire [19:0] out_slt3;`
125			`wire [19:0] out_slt4;`
126			`wire [19:0] out_slt6;`
127			`wire [19:0] out_slt7;`
128			`wire [19:0] out_slt8;`
129			`wire [19:0] out_slt9;`
130
131			`// Serial Input register interface`
132			`wire [15:0] in_slt0;`
133			`wire [19:0] in_slt1;`
134			`wire [19:0] in_slt2;`
135			`wire [19:0] in_slt3;`
136			`wire [19:0] in_slt4;`
137			`wire [19:0] in_slt6;`
138
139			`// Serial IO Controller Interface`
140			`wire ld;`
141			`wire valid;`
142			`wire [5:0] out_le;`
143			`wire [2:0] in_valid;`
144			`wire ps_ce;`
145
146			`// Valid Sync`
147			`reg valid_s1, valid_s;`
148			`reg [2:0] in_valid_s1, in_valid_s;`
149
150			`// Out FIFO interface`
151			`wire [31:0] wb_din;`
152			`wire [1:0] o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode;`
153			`wire o3_re, o4_re, o6_re, o7_re, o8_re, o9_re;`
154			`wire o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;`
155			`wire [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;`
156			`wire o3_full, o4_full, o6_full, o7_full, o8_full, o9_full;`
157			`wire o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;`
158
159			`// In FIFO interface`
160			`wire [31:0] i3_dout, i4_dout, i6_dout;`
161			`wire [1:0] i3_mode, i4_mode, i6_mode;`
162			`wire i3_we, i4_we, i6_we;`
163			`wire i3_re, i4_re, i6_re;`
164			`wire [1:0] i3_status, i4_status, i6_status;`
165			`wire i3_full, i4_full, i6_full;`
166			`wire i3_empty, i4_empty, i6_empty;`
167
168			`// Register File Interface`
169			`wire [3:0] adr;`
170			`wire [31:0] rf_dout;`
171			`wire [31:0] rf_din;`
172			`wire rf_we;`
173			`wire rf_re;`
174			`wire ac97_rst_force;`
175			`wire resume_req;`
176			`wire crac_we;`
177			`wire [15:0] crac_din;`
178			`wire [31:0] crac_out;`
179			`wire [7:0] oc0_cfg;`
180			`wire [7:0] oc1_cfg;`
181			`wire [7:0] oc2_cfg;`
182			`wire [7:0] oc3_cfg;`
183			`wire [7:0] oc4_cfg;`
184			`wire [7:0] oc5_cfg;`
185			`wire [7:0] ic0_cfg;`
186			`wire [7:0] ic1_cfg;`
187			`wire [7:0] ic2_cfg;`
188			`wire [2:0] oc0_int_set;`
189			`wire [2:0] oc1_int_set;`
190			`wire [2:0] oc2_int_set;`
191			`wire [2:0] oc3_int_set;`
192			`wire [2:0] oc4_int_set;`
193			`wire [2:0] oc5_int_set;`
194			`wire [2:0] ic0_int_set;`
195			`wire [2:0] ic1_int_set;`
196			`wire [2:0] ic2_int_set;`
197
198			`// CRA Module interface`
199			`wire crac_valid;`
200			`wire crac_wr;`
201			`wire crac_wr_done, crac_rd_done;`
202
203			`////////////////////////////////////////////////////////////////////`
204			`//`
205			`// Misc Logic`
206			`//`
207
208			`// Sync Valid to WISHBONE Clock`
209	6	rudi	`always @(posedge clk_i)`
210	4	rudi	`valid_s1 <= #1 valid;`
211
212	6	rudi	`always @(posedge clk_i)`
213	4	rudi	`valid_s <= #1 valid_s1;`
214
215	6	rudi	`always @(posedge clk_i)`
216	4	rudi	`in_valid_s1 <= #1 in_valid;`
217
218	6	rudi	`always @(posedge clk_i)`
219	4	rudi	`in_valid_s <= #1 in_valid_s1;`
220
221			`// "valid_s" Indicates when any of the outputs to the output S/R may`
222			`// change or when outputs from input S/R may be sampled`
223			`assign o3_mode = oc0_cfg[3:2];`
224			`assign o4_mode = oc1_cfg[3:2];`
225			`assign o6_mode = oc2_cfg[3:2];`
226			`assign o7_mode = oc3_cfg[3:2];`
227			`assign o8_mode = oc4_cfg[3:2];`
228			`assign o9_mode = oc5_cfg[3:2];`
229			`assign i3_mode = ic0_cfg[3:2];`
230			`assign i4_mode = ic1_cfg[3:2];`
231			`assign i6_mode = ic2_cfg[3:2];`
232
233			`////////////////////////////////////////////////////////////////////`
234			`//`
235			`// Modules`
236			`//`
237
238			`ac97_sout u0(`
239	6	rudi	`.clk( bit_clk_pad_i ),`
240			`.rst( rst_i ),`
241	4	rudi	`.so_ld( ld ),`
242			`.slt0( out_slt0 ),`
243			`.slt1( out_slt1 ),`
244			`.slt2( out_slt2 ),`
245			`.slt3( out_slt3 ),`
246			`.slt4( out_slt4 ),`
247			`.slt6( out_slt6 ),`
248			`.slt7( out_slt7 ),`
249			`.slt8( out_slt8 ),`
250			`.slt9( out_slt9 ),`
251	6	rudi	`.sdata_out( sdata_pad_o )`
252	4	rudi	`);`
253
254			`ac97_sin u1(`
255	6	rudi	`.clk( bit_clk_pad_i ),`
256			`.rst( rst_i ),`
257	4	rudi	`.out_le( out_le ),`
258			`.slt0( in_slt0 ),`
259			`.slt1( in_slt1 ),`
260			`.slt2( in_slt2 ),`
261			`.slt3( in_slt3 ),`
262			`.slt4( in_slt4 ),`
263			`.slt6( in_slt6 ),`
264	6	rudi	`.sdata_in( sdata_pad_i )`
265	4	rudi	`);`
266
267			`ac97_soc u2(`
268	6	rudi	`.clk( bit_clk_pad_i ),`
269			`.wclk( clk_i ),`
270			`.rst( rst_i ),`
271	4	rudi	`.ps_ce( ps_ce ),`
272			`.resume( resume_req ),`
273	6	rudi	`.suspended( suspended_o ),`
274			`.sync( sync_pad_o ),`
275	4	rudi	`.out_le( out_le ),`
276			`.in_valid( in_valid ),`
277			`.ld( ld ),`
278			`.valid( valid )`
279			`);`
280
281			`ac97_out_fifo u3(`
282	6	rudi	`.clk( clk_i ),`
283			`.rst( rst_i ),`
284	4	rudi	`.en( oc0_cfg[0] ),`
285			`.mode( o3_mode ),`
286			`.din( wb_din ),`
287			`.we( o3_we ),`
288			`.dout( out_slt3 ),`
289			`.re( o3_re ),`
290			`.status( o3_status ),`
291			`.full( o3_full ),`
292			`.empty( o3_empty )`
293			`);`
294
295			`ac97_out_fifo u4(`
296	6	rudi	`.clk( clk_i ),`
297			`.rst( rst_i ),`
298	4	rudi	`.en( oc1_cfg[0] ),`
299			`.mode( o4_mode ),`
300			`.din( wb_din ),`
301			`.we( o4_we ),`
302			`.dout( out_slt4 ),`
303			`.re( o4_re ),`
304			`.status( o4_status ),`
305			`.full( o4_full ),`
306			`.empty( o4_empty )`
307			`);`
308
309	6	rudi	`ifdef AC97_CENTER
310	4	rudi	`ac97_out_fifo u5(`
311	6	rudi	`.clk( clk_i ),`
312			`.rst( rst_i ),`
313	4	rudi	`.en( oc2_cfg[0] ),`
314			`.mode( o6_mode ),`
315			`.din( wb_din ),`
316			`.we( o6_we ),`
317			`.dout( out_slt6 ),`
318			`.re( o6_re ),`
319			`.status( o6_status ),`
320			`.full( o6_full ),`
321			`.empty( o6_empty )`
322			`);`
323			`else
324	10	rudi	`assign out_slt6 = 20'h0;`
325			`assign o6_status = 2'h0;`
326			`assign o6_full = 1'b0;`
327			`assign o6_empty = 1'b0;`
328	4	rudi	`endif
329
330	6	rudi	`ifdef AC97_SURROUND
331	4	rudi	`ac97_out_fifo u6(`
332	6	rudi	`.clk( clk_i ),`
333			`.rst( rst_i ),`
334	4	rudi	`.en( oc3_cfg[0] ),`
335			`.mode( o7_mode ),`
336			`.din( wb_din ),`
337			`.we( o7_we ),`
338			`.dout( out_slt7 ),`
339			`.re( o7_re ),`
340			`.status( o7_status ),`
341			`.full( o7_full ),`
342			`.empty( o7_empty )`
343			`);`
344
345			`ac97_out_fifo u7(`
346	6	rudi	`.clk( clk_i ),`
347			`.rst( rst_i ),`
348	4	rudi	`.en( oc4_cfg[0] ),`
349			`.mode( o8_mode ),`
350			`.din( wb_din ),`
351			`.we( o8_we ),`
352			`.dout( out_slt8 ),`
353			`.re( o8_re ),`
354			`.status( o8_status ),`
355			`.full( o8_full ),`
356			`.empty( o8_empty )`
357			`);`
358			`else
359	10	rudi	`assign out_slt7 = 20'h0;`
360			`assign o7_status = 2'h0;`
361			`assign o7_full = 1'b0;`
362			`assign o7_empty = 1'b0;`
363			`assign out_slt8 = 20'h0;`
364			`assign o8_status = 2'h0;`
365			`assign o8_full = 1'b0;`
366			`assign o8_empty = 1'b0;`
367	4	rudi	`endif
368
369	6	rudi	`ifdef AC97_LFE
370	4	rudi	`ac97_out_fifo u8(`
371	6	rudi	`.clk( clk_i ),`
372			`.rst( rst_i ),`
373	4	rudi	`.en( oc5_cfg[0] ),`
374			`.mode( o9_mode ),`
375			`.din( wb_din ),`
376			`.we( o9_we ),`
377			`.dout( out_slt9 ),`
378			`.re( o9_re ),`
379			`.status( o9_status ),`
380			`.full( o9_full ),`
381			`.empty( o9_empty )`
382			`);`
383			`else
384	10	rudi	`assign out_slt9 = 20'h0;`
385			`assign o9_status = 2'h0;`
386			`assign o9_full = 1'b0;`
387			`assign o9_empty = 1'b0;`
388	4	rudi	`endif
389
390	6	rudi	`ifdef AC97_SIN
391	4	rudi	`ac97_in_fifo u9(`
392	6	rudi	`.clk( clk_i ),`
393			`.rst( rst_i ),`
394	4	rudi	`.en( ic0_cfg[0] ),`
395			`.mode( i3_mode ),`
396			`.din( in_slt3 ),`
397			`.we( i3_we ),`
398			`.dout( i3_dout ),`
399			`.re( i3_re ),`
400			`.status( i3_status ),`
401			`.full( i3_full ),`
402			`.empty( i3_empty )`
403			`);`
404
405			`ac97_in_fifo u10(`
406	6	rudi	`.clk( clk_i ),`
407			`.rst( rst_i ),`
408	4	rudi	`.en( ic1_cfg[0] ),`
409			`.mode( i4_mode ),`
410			`.din( in_slt4 ),`
411			`.we( i4_we ),`
412			`.dout( i4_dout ),`
413			`.re( i4_re ),`
414			`.status( i4_status ),`
415			`.full( i4_full ),`
416			`.empty( i4_empty )`
417			`);`
418			`else
419	10	rudi	`assign i3_dout = 20'h0;`
420			`assign i3_status = 2'h0;`
421			`assign i3_full = 1'b0;`
422			`assign i3_empty = 1'b0;`
423			`assign i4_dout = 20'h0;`
424			`assign i4_status = 2'h0;`
425			`assign i4_full = 1'b0;`
426			`assign i4_empty = 1'b0;`
427	4	rudi	`endif
428
429	6	rudi	`ifdef AC97_MICIN
430	4	rudi	`ac97_in_fifo u11(`
431	6	rudi	`.clk( clk_i ),`
432			`.rst( rst_i ),`
433	4	rudi	`.en( ic2_cfg[0] ),`
434			`.mode( i6_mode ),`
435			`.din( in_slt6 ),`
436			`.we( i6_we ),`
437			`.dout( i6_dout ),`
438			`.re( i6_re ),`
439			`.status( i6_status ),`
440			`.full( i6_full ),`
441			`.empty( i6_empty )`
442			`);`
443			`else
444	10	rudi	`assign i6_dout = 20'h0;`
445			`assign i6_status = 2'h0;`
446			`assign i6_full = 1'b0;`
447			`assign i6_empty = 1'b0;`
448	4	rudi	`endif
449
450			`ac97_wb_if u12(`
451	6	rudi	`.clk( clk_i ),`
452			`.rst( rst_i ),`
453	4	rudi	`.wb_data_i( wb_data_i ),`
454			`.wb_data_o( wb_data_o ),`
455			`.wb_addr_i( wb_addr_i ),`
456			`.wb_sel_i( wb_sel_i ),`
457			`.wb_we_i( wb_we_i ),`
458			`.wb_cyc_i( wb_cyc_i ),`
459			`.wb_stb_i( wb_stb_i ),`
460			`.wb_ack_o( wb_ack_o ),`
461			`.wb_err_o( wb_err_o ),`
462			`.adr( adr ),`
463			`.dout( wb_din ),`
464			`.rf_din( rf_dout ),`
465			`.i3_din( i3_dout ),`
466			`.i4_din( i4_dout ),`
467			`.i6_din( i6_dout ),`
468			`.rf_we( rf_we ),`
469			`.rf_re( rf_re ),`
470			`.o3_we( o3_we ),`
471			`.o4_we( o4_we ),`
472			`.o6_we( o6_we ),`
473			`.o7_we( o7_we ),`
474			`.o8_we( o8_we ),`
475			`.o9_we( o9_we ),`
476			`.i3_re( i3_re ),`
477			`.i4_re( i4_re ),`
478			`.i6_re( i6_re )`
479			`);`
480
481	6	rudi	`ac97_rf u13( .clk( clk_i ),`
482			`.rst( rst_i ),`
483	4	rudi	`.adr( adr ),`
484			`.rf_dout( rf_dout ),`
485			`.rf_din( wb_din ),`
486			`.rf_we( rf_we ),`
487			`.rf_re( rf_re ),`
488	6	rudi	`.int( int_o ),`
489	4	rudi	`.ac97_rst_force(ac97_rst_force ),`
490			`.resume_req( resume_req ),`
491	6	rudi	`.suspended( suspended_o ),`
492	4	rudi	`.crac_we( crac_we ),`
493			`.crac_din( crac_din ),`
494			`.crac_out( crac_out ),`
495			`.crac_wr_done( crac_wr_done ),`
496			`.crac_rd_done( crac_rd_done ),`
497			`.oc0_cfg( oc0_cfg ),`
498			`.oc1_cfg( oc1_cfg ),`
499			`.oc2_cfg( oc2_cfg ),`
500			`.oc3_cfg( oc3_cfg ),`

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_top.v] - Blame information for rev 10