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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller Top Level                        ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_top.v,v 1.4 2002-09-19 06:30:56 rudi Exp $
//
//  $Date: 2002-09-19 06:30:56 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2002/03/05 04:44:05  rudi
//
//               - Fixed the order of the thrash hold bits to match the spec.
//               - Many minor synthesis cleanup items ...
//
//               Revision 1.2  2001/08/10 08:09:42  rudi
//
//               - Removed RTY_O output.
//               - Added Clock and Reset Inputs to documentation.
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:14  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_top(clk_i, rst_i,
 
        wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
        wb_stb_i, wb_ack_o, wb_err_o,
 
        int_o, dma_req_o, dma_ack_i,
        suspended_o,
 
        bit_clk_pad_i, sync_pad_o, sdata_pad_o, sdata_pad_i,
        ac97_reset_pad_o_
        );
 
input           clk_i, rst_i;
 
// --------------------------------------
// WISHBONE SLAVE INTERFACE 
input   [31:0]   wb_data_i;
output  [31:0]   wb_data_o;
input   [31:0]   wb_addr_i;
input   [3:0]    wb_sel_i;
input           wb_we_i;
input           wb_cyc_i;
input           wb_stb_i;
output          wb_ack_o;
output          wb_err_o;
 
// --------------------------------------
// Misc Signals
output          int_o;
output  [8:0]    dma_req_o;
input   [8:0]    dma_ack_i;
 
// --------------------------------------
// Suspend Resume Interface
output          suspended_o;
 
// --------------------------------------
// AC97 Codec Interface
input           bit_clk_pad_i;
output          sync_pad_o;
output          sdata_pad_o;
input           sdata_pad_i;
output          ac97_reset_pad_o_;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
// Serial Output register interface
wire    [15:0]   out_slt0;
wire    [19:0]   out_slt1;
wire    [19:0]   out_slt2;
wire    [19:0]   out_slt3;
wire    [19:0]   out_slt4;
wire    [19:0]   out_slt6;
wire    [19:0]   out_slt7;
wire    [19:0]   out_slt8;
wire    [19:0]   out_slt9;
 
// Serial Input register interface
wire    [15:0]   in_slt0;
wire    [19:0]   in_slt1;
wire    [19:0]   in_slt2;
wire    [19:0]   in_slt3;
wire    [19:0]   in_slt4;
wire    [19:0]   in_slt6;
 
// Serial IO Controller Interface
wire            ld;
wire            valid;
wire    [5:0]    out_le;
wire    [2:0]    in_valid;
wire            ps_ce;
 
// Valid Sync
reg             valid_s1, valid_s;
reg     [2:0]    in_valid_s1, in_valid_s;
 
// Out FIFO interface
wire    [31:0]   wb_din;
wire    [1:0]    o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode;
wire            o3_re, o4_re, o6_re, o7_re, o8_re, o9_re;
wire            o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
wire    [1:0]    o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;
wire            o3_full, o4_full, o6_full, o7_full, o8_full, o9_full;
wire            o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;
 
// In FIFO interface
wire    [31:0]   i3_dout, i4_dout, i6_dout;
wire    [1:0]    i3_mode, i4_mode, i6_mode;
wire            i3_we, i4_we, i6_we;
wire            i3_re, i4_re, i6_re;
wire    [1:0]    i3_status, i4_status, i6_status;
wire            i3_full, i4_full, i6_full;
wire            i3_empty, i4_empty, i6_empty;
 
// Register File Interface
wire    [3:0]    adr;
wire    [31:0]   rf_dout;
wire    [31:0]   rf_din;
wire            rf_we;
wire            rf_re;
wire            ac97_rst_force;
wire            resume_req;
wire            crac_we;
wire    [15:0]   crac_din;
wire    [31:0]   crac_out;
wire    [7:0]    oc0_cfg;
wire    [7:0]    oc1_cfg;
wire    [7:0]    oc2_cfg;
wire    [7:0]    oc3_cfg;
wire    [7:0]    oc4_cfg;
wire    [7:0]    oc5_cfg;
wire    [7:0]    ic0_cfg;
wire    [7:0]    ic1_cfg;
wire    [7:0]    ic2_cfg;
wire    [2:0]    oc0_int_set;
wire    [2:0]    oc1_int_set;
wire    [2:0]    oc2_int_set;
wire    [2:0]    oc3_int_set;
wire    [2:0]    oc4_int_set;
wire    [2:0]    oc5_int_set;
wire    [2:0]    ic0_int_set;
wire    [2:0]    ic1_int_set;
wire    [2:0]    ic2_int_set;
 
// CRA Module interface
wire            crac_valid;
wire            crac_wr;
wire            crac_wr_done, crac_rd_done;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
// Sync Valid to WISHBONE Clock
always @(posedge clk_i)
        valid_s1 <= #1 valid;
 
always @(posedge clk_i)
        valid_s <= #1 valid_s1;
 
always @(posedge clk_i)
        in_valid_s1 <= #1 in_valid;
 
always @(posedge clk_i)
        in_valid_s <= #1 in_valid_s1;
 
// "valid_s" Indicates when any of the outputs to the output S/R may
// change or when outputs from input S/R may be sampled
assign o3_mode = oc0_cfg[3:2];
assign o4_mode = oc1_cfg[3:2];
assign o6_mode = oc2_cfg[3:2];
assign o7_mode = oc3_cfg[3:2];
assign o8_mode = oc4_cfg[3:2];
assign o9_mode = oc5_cfg[3:2];
assign i3_mode = ic0_cfg[3:2];
assign i4_mode = ic1_cfg[3:2];
assign i6_mode = ic2_cfg[3:2];
 
////////////////////////////////////////////////////////////////////
//
// Modules
//
 
ac97_sout       u0(
                .clk(           bit_clk_pad_i   ),
                .rst(           rst_i           ),
                .so_ld(         ld              ),
                .slt0(          out_slt0        ),
                .slt1(          out_slt1        ),
                .slt2(          out_slt2        ),
                .slt3(          out_slt3        ),
                .slt4(          out_slt4        ),
                .slt6(          out_slt6        ),
                .slt7(          out_slt7        ),
                .slt8(          out_slt8        ),
                .slt9(          out_slt9        ),
                .sdata_out(     sdata_pad_o     )
                );
 
ac97_sin        u1(
                .clk(           bit_clk_pad_i   ),
                .rst(           rst_i           ),
                .out_le(        out_le          ),
                .slt0(          in_slt0         ),
                .slt1(          in_slt1         ),
                .slt2(          in_slt2         ),
                .slt3(          in_slt3         ),
                .slt4(          in_slt4         ),
                .slt6(          in_slt6         ),
                .sdata_in(      sdata_pad_i     )
                );
 
ac97_soc        u2(
                .clk(           bit_clk_pad_i   ),
                .wclk(          clk_i           ),
                .rst(           rst_i           ),
                .ps_ce(         ps_ce           ),
                .resume(        resume_req      ),
                .suspended(     suspended_o     ),
                .sync(          sync_pad_o      ),
                .out_le(        out_le          ),
                .in_valid(      in_valid        ),
                .ld(            ld              ),
                .valid(         valid           )
                );
 
ac97_out_fifo   u3(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc0_cfg[0]       ),
                .mode(          o3_mode         ),
                .din(           wb_din          ),
                .we(            o3_we           ),
                .dout(          out_slt3        ),
                .re(            o3_re           ),
                .status(        o3_status       ),
                .full(          o3_full         ),
                .empty(         o3_empty        )
                );
 
ac97_out_fifo   u4(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc1_cfg[0]       ),
                .mode(          o4_mode         ),
                .din(           wb_din          ),
                .we(            o4_we           ),
                .dout(          out_slt4        ),
                .re(            o4_re           ),
                .status(        o4_status       ),
                .full(          o4_full         ),
                .empty(         o4_empty        )
                );
 
`ifdef AC97_CENTER
ac97_out_fifo   u5(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc2_cfg[0]       ),
                .mode(          o6_mode         ),
                .din(           wb_din          ),
                .we(            o6_we           ),
                .dout(          out_slt6        ),
                .re(            o6_re           ),
                .status(        o6_status       ),
                .full(          o6_full         ),
                .empty(         o6_empty        )
                );
`else
assign out_slt6 = 20'h0;
assign o6_status = 2'h0;
assign o6_full = 1'b0;
assign o6_empty = 1'b0;
`endif
 
`ifdef AC97_SURROUND
ac97_out_fifo   u6(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc3_cfg[0]       ),
                .mode(          o7_mode         ),
                .din(           wb_din          ),
                .we(            o7_we           ),
                .dout(          out_slt7        ),
                .re(            o7_re           ),
                .status(        o7_status       ),
                .full(          o7_full         ),
                .empty(         o7_empty        )
                );
 
ac97_out_fifo   u7(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc4_cfg[0]       ),
                .mode(          o8_mode         ),
                .din(           wb_din          ),
                .we(            o8_we           ),
                .dout(          out_slt8        ),
                .re(            o8_re           ),
                .status(        o8_status       ),
                .full(          o8_full         ),
                .empty(         o8_empty        )
                );
`else
assign out_slt7 = 20'h0;
assign o7_status = 2'h0;
assign o7_full = 1'b0;
assign o7_empty = 1'b0;
assign out_slt8 = 20'h0;
assign o8_status = 2'h0;
assign o8_full = 1'b0;
assign o8_empty = 1'b0;
`endif
 
`ifdef AC97_LFE
ac97_out_fifo   u8(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            oc5_cfg[0]       ),
                .mode(          o9_mode         ),
                .din(           wb_din          ),
                .we(            o9_we           ),
                .dout(          out_slt9        ),
                .re(            o9_re           ),
                .status(        o9_status       ),
                .full(          o9_full         ),
                .empty(         o9_empty        )
                );
`else
assign out_slt9 = 20'h0;
assign o9_status = 2'h0;
assign o9_full = 1'b0;
assign o9_empty = 1'b0;
`endif
 
`ifdef AC97_SIN
ac97_in_fifo    u9(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            ic0_cfg[0]       ),
                .mode(          i3_mode         ),
                .din(           in_slt3         ),
                .we(            i3_we           ),
                .dout(          i3_dout         ),
                .re(            i3_re           ),
                .status(        i3_status       ),
                .full(          i3_full         ),
                .empty(         i3_empty        )
                );
 
ac97_in_fifo    u10(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            ic1_cfg[0]       ),
                .mode(          i4_mode         ),
                .din(           in_slt4         ),
                .we(            i4_we           ),
                .dout(          i4_dout         ),
                .re(            i4_re           ),
                .status(        i4_status       ),
                .full(          i4_full         ),
                .empty(         i4_empty        )
                );
`else
assign i3_dout = 20'h0;
assign i3_status = 2'h0;
assign i3_full = 1'b0;
assign i3_empty = 1'b0;
assign i4_dout = 20'h0;
assign i4_status = 2'h0;
assign i4_full = 1'b0;
assign i4_empty = 1'b0;
`endif
 
`ifdef AC97_MICIN
ac97_in_fifo    u11(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .en(            ic2_cfg[0]       ),
                .mode(          i6_mode         ),
                .din(           in_slt6         ),
                .we(            i6_we           ),
                .dout(          i6_dout         ),
                .re(            i6_re           ),
                .status(        i6_status       ),
                .full(          i6_full         ),
                .empty(         i6_empty        )
                );
`else
assign i6_dout = 20'h0;
assign i6_status = 2'h0;
assign i6_full = 1'b0;
assign i6_empty = 1'b0;
`endif
 
ac97_wb_if      u12(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .wb_data_i(     wb_data_i       ),
                .wb_data_o(     wb_data_o       ),
                .wb_addr_i(     wb_addr_i       ),
                .wb_sel_i(      wb_sel_i        ),
                .wb_we_i(       wb_we_i         ),
                .wb_cyc_i(      wb_cyc_i        ),
                .wb_stb_i(      wb_stb_i        ),
                .wb_ack_o(      wb_ack_o        ),
                .wb_err_o(      wb_err_o        ),
                .adr(           adr             ),
                .dout(          wb_din          ),
                .rf_din(        rf_dout         ),
                .i3_din(        i3_dout         ),
                .i4_din(        i4_dout         ),
                .i6_din(        i6_dout         ),
                .rf_we(         rf_we           ),
                .rf_re(         rf_re           ),
                .o3_we(         o3_we           ),
                .o4_we(         o4_we           ),
                .o6_we(         o6_we           ),
                .o7_we(         o7_we           ),
                .o8_we(         o8_we           ),
                .o9_we(         o9_we           ),
                .i3_re(         i3_re           ),
                .i4_re(         i4_re           ),
                .i6_re(         i6_re           )
                );
 
ac97_rf u13(    .clk(           clk_i           ),
                .rst(           rst_i           ),
                .adr(           adr             ),
                .rf_dout(       rf_dout         ),
                .rf_din(        wb_din          ),
                .rf_we(         rf_we           ),
                .rf_re(         rf_re           ),
                .int(           int_o           ),
                .ac97_rst_force(ac97_rst_force  ),
                .resume_req(    resume_req      ),
                .suspended(     suspended_o     ),
                .crac_we(       crac_we         ),
                .crac_din(      crac_din        ),
                .crac_out(      crac_out        ),
                .crac_wr_done(  crac_wr_done    ),
                .crac_rd_done(  crac_rd_done    ),
                .oc0_cfg(       oc0_cfg         ),
                .oc1_cfg(       oc1_cfg         ),
                .oc2_cfg(       oc2_cfg         ),
                .oc3_cfg(       oc3_cfg         ),
                .oc4_cfg(       oc4_cfg         ),
                .oc5_cfg(       oc5_cfg         ),
                .ic0_cfg(       ic0_cfg         ),
                .ic1_cfg(       ic1_cfg         ),
                .ic2_cfg(       ic2_cfg         ),
                .oc0_int_set(   oc0_int_set     ),
                .oc1_int_set(   oc1_int_set     ),
                .oc2_int_set(   oc2_int_set     ),
                .oc3_int_set(   oc3_int_set     ),
                .oc4_int_set(   oc4_int_set     ),
                .oc5_int_set(   oc5_int_set     ),
                .ic0_int_set(   ic0_int_set     ),
                .ic1_int_set(   ic1_int_set     ),
                .ic2_int_set(   ic2_int_set     )
                );
 
ac97_prc u14(   .clk(           clk_i           ),
                .rst(           rst_i           ),
                .valid(         valid_s         ),
                .in_valid(      in_valid_s      ),
                .out_slt0(      out_slt0        ),
                .in_slt0(       in_slt0         ),
                .in_slt1(       in_slt1         ),
                .crac_valid(    crac_valid      ),
                .crac_wr(       crac_wr         ),
                .oc0_cfg(       oc0_cfg         ),
                .oc1_cfg(       oc1_cfg         ),
                .oc2_cfg(       oc2_cfg         ),
                .oc3_cfg(       oc3_cfg         ),
                .oc4_cfg(       oc4_cfg         ),
                .oc5_cfg(       oc5_cfg         ),
                .ic0_cfg(       ic0_cfg         ),
                .ic1_cfg(       ic1_cfg         ),
                .ic2_cfg(       ic2_cfg         ),
                .o3_empty(      o3_empty        ),
                .o4_empty(      o4_empty        ),
                .o6_empty(      o6_empty        ),
                .o7_empty(      o7_empty        ),
                .o8_empty(      o8_empty        ),
                .o9_empty(      o9_empty        ),
                .i3_full(       i3_full         ),
                .i4_full(       i4_full         ),
                .i6_full(       i6_full         ),
                .o3_re(         o3_re           ),
                .o4_re(         o4_re           ),
                .o6_re(         o6_re           ),
                .o7_re(         o7_re           ),
                .o8_re(         o8_re           ),
                .o9_re(         o9_re           ),
                .i3_we(         i3_we           ),
                .i4_we(         i4_we           ),
                .i6_we(         i6_we           )
                );
 
ac97_cra u15(   .clk(           clk_i           ),
                .rst(           rst_i           ),
                .crac_we(       crac_we         ),
                .crac_din(      crac_din        ),
                .crac_out(      crac_out        ),
                .crac_wr_done(  crac_wr_done    ),
                .crac_rd_done(  crac_rd_done    ),
                .valid(         valid_s         ),
                .out_slt1(      out_slt1        ),
                .out_slt2(      out_slt2        ),
                .in_slt2(       in_slt2         ),
                .crac_valid(    crac_valid      ),
                .crac_wr(       crac_wr         )
                );
 
ac97_dma_if u16(.clk(           clk_i           ),
                .rst(           rst_i           ),
                .o3_status(     o3_status       ),
                .o4_status(     o4_status       ),
                .o6_status(     o6_status       ),
                .o7_status(     o7_status       ),
                .o8_status(     o8_status       ),
                .o9_status(     o9_status       ),
                .o3_empty(      o3_empty        ),
                .o4_empty(      o4_empty        ),
                .o6_empty(      o6_empty        ),
                .o7_empty(      o7_empty        ),
                .o8_empty(      o8_empty        ),
                .o9_empty(      o9_empty        ),
                .i3_status(     i3_status       ),
                .i4_status(     i4_status       ),
                .i6_status(     i6_status       ),
                .i3_full(       i3_full         ),
                .i4_full(       i4_full         ),
                .i6_full(       i6_full         ),
                .oc0_cfg(       oc0_cfg         ),
                .oc1_cfg(       oc1_cfg         ),
                .oc2_cfg(       oc2_cfg         ),
                .oc3_cfg(       oc3_cfg         ),
                .oc4_cfg(       oc4_cfg         ),
                .oc5_cfg(       oc5_cfg         ),
                .ic0_cfg(       ic0_cfg         ),
                .ic1_cfg(       ic1_cfg         ),
                .ic2_cfg(       ic2_cfg         ),
                .dma_req(       dma_req_o       ),
                .dma_ack(       dma_ack_i       )
                );
 
ac97_int        u17(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc0_int_set     ),
                .cfg(           oc0_cfg         ),
                .status(        o3_status       ),
                .full_empty(    o3_empty        ),
                .full(          o3_full         ),
                .empty(         o3_empty        ),
                .re(            o3_re           ),
                .we(            o3_we           )
                );
 
ac97_int        u18(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc1_int_set     ),
                .cfg(           oc1_cfg         ),
                .status(        o4_status       ),
                .full_empty(    o4_empty        ),
                .full(          o4_full         ),
                .empty(         o4_empty        ),
                .re(            o4_re           ),
                .we(            o4_we           )
                );
 
`ifdef AC97_CENTER
ac97_int        u19(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc2_int_set     ),
                .cfg(           oc2_cfg         ),
                .status(        o6_status       ),
                .full_empty(    o6_empty        ),
                .full(          o6_full         ),
                .empty(         o6_empty        ),
                .re(            o6_re           ),
                .we(            o6_we           )
                );
`else
assign oc2_int_set = 1'b0;
`endif
 
`ifdef AC97_SURROUND
ac97_int        u20(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc3_int_set     ),
                .cfg(           oc3_cfg         ),
                .status(        o7_status       ),
                .full_empty(    o7_empty        ),
                .full(          o7_full         ),
                .empty(         o7_empty        ),
                .re(            o7_re           ),
                .we(            o7_we           )
                );
 
ac97_int        u21(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc4_int_set     ),
                .cfg(           oc4_cfg         ),
                .status(        o8_status       ),
                .full_empty(    o8_empty        ),
                .full(          o8_full         ),
                .empty(         o8_empty        ),
                .re(            o8_re           ),
                .we(            o8_we           )
                );
`else
assign oc3_int_set = 1'b0;
assign oc4_int_set = 1'b0;
`endif
 
`ifdef AC97_LFE
ac97_int        u22(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       oc5_int_set     ),
                .cfg(           oc5_cfg         ),
                .status(        o9_status       ),
                .full_empty(    o9_empty        ),
                .full(          o9_full         ),
                .empty(         o9_empty        ),
                .re(            o9_re           ),
                .we(            o9_we           )
                );
`else
assign oc5_int_set = 1'b0;
`endif
 
`ifdef AC97_SIN
ac97_int        u23(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       ic0_int_set     ),
                .cfg(           ic0_cfg         ),
                .status(        i3_status       ),
                .full_empty(    i3_full         ),
                .full(          i3_full         ),
                .empty(         i3_empty        ),
                .re(            i3_re           ),
                .we(            i3_we           )
                );
 
ac97_int        u24(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       ic1_int_set     ),
                .cfg(           ic1_cfg         ),
                .status(        i4_status       ),
                .full_empty(    i4_full         ),
                .full(          i4_full         ),
                .empty(         i4_empty        ),
                .re(            i4_re           ),
                .we(            i4_we           )
                );
`else
assign ic0_int_set = 1'b0;
assign ic1_int_set = 1'b0;
`endif
 
`ifdef AC97_MICIN
ac97_int        u25(
                .clk(           clk_i           ),
                .rst(           rst_i           ),
                .int_set(       ic2_int_set     ),
                .cfg(           ic2_cfg         ),
                .status(        i6_status       ),
                .full_empty(    i6_full         ),
                .full(          i6_full         ),
                .empty(         i6_empty        ),
                .re(            i6_re           ),
                .we(            i6_we           )
                );
`else
assign ic2_int_set = 1'b0;
`endif
 
ac97_rst        u26(
                .clk(           clk_i                           ),
                .rst(           rst_i                           ),
                .rst_force(     ac97_rst_force                  ),
                .ps_ce(         ps_ce                           ),
                .ac97_rst_(     ac97_reset_pad_o_               )
                );
 
endmodule
 

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller Top Level ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws ////`
17	4	rudi	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	14	rudi	`// $Id: ac97_top.v,v 1.4 2002-09-19 06:30:56 rudi Exp $`
42	4	rudi	`//`
43	14	rudi	`// $Date: 2002-09-19 06:30:56 $`
44			`// $Revision: 1.4 $`
45	4	rudi	`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	14	rudi	`// Revision 1.3 2002/03/05 04:44:05 rudi`
52			`//`
53			`// - Fixed the order of the thrash hold bits to match the spec.`
54			`// - Many minor synthesis cleanup items ...`
55			`//`
56	10	rudi	`// Revision 1.2 2001/08/10 08:09:42 rudi`
57			`//`
58			`// - Removed RTY_O output.`
59			`// - Added Clock and Reset Inputs to documentation.`
60			`// - Changed IO names to be more clear.`
61			`// - Uniquifyed define names to be core specific.`
62			`//`
63	6	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
64			`//`
65			`//`
66			`// - Changed to new directory structure`
67			`//`
68	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:14 rudi`
69			`// Initial Checkin`
70			`//`
71			`//`
72			`//`
73			`//`
74
75			`include "ac97_defines.v"
76
77	6	rudi	`module ac97_top(clk_i, rst_i,`
78	4	rudi
79			`wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
80			`wb_stb_i, wb_ack_o, wb_err_o,`
81
82	6	rudi	`int_o, dma_req_o, dma_ack_i,`
83			`suspended_o,`
84	4	rudi
85	6	rudi	`bit_clk_pad_i, sync_pad_o, sdata_pad_o, sdata_pad_i,`
86			`ac97_reset_pad_o_`
87	4	rudi	`);`
88
89	6	rudi	`input clk_i, rst_i;`
90	4	rudi
91			`// --------------------------------------`
92			`// WISHBONE SLAVE INTERFACE`
93			`input [31:0] wb_data_i;`
94			`output [31:0] wb_data_o;`
95			`input [31:0] wb_addr_i;`
96			`input [3:0] wb_sel_i;`
97			`input wb_we_i;`
98			`input wb_cyc_i;`
99			`input wb_stb_i;`
100			`output wb_ack_o;`
101			`output wb_err_o;`
102
103			`// --------------------------------------`
104			`// Misc Signals`
105	6	rudi	`output int_o;`
106			`output [8:0] dma_req_o;`
107			`input [8:0] dma_ack_i;`
108	4	rudi
109			`// --------------------------------------`
110			`// Suspend Resume Interface`
111	6	rudi	`output suspended_o;`
112	4	rudi
113			`// --------------------------------------`
114			`// AC97 Codec Interface`
115	6	rudi	`input bit_clk_pad_i;`
116			`output sync_pad_o;`
117			`output sdata_pad_o;`
118			`input sdata_pad_i;`
119			`output ac97_reset_pad_o_;`
120	4	rudi
121			`////////////////////////////////////////////////////////////////////`
122			`//`
123			`// Local Wires`
124			`//`
125
126			`// Serial Output register interface`
127			`wire [15:0] out_slt0;`
128			`wire [19:0] out_slt1;`
129			`wire [19:0] out_slt2;`
130			`wire [19:0] out_slt3;`
131			`wire [19:0] out_slt4;`
132			`wire [19:0] out_slt6;`
133			`wire [19:0] out_slt7;`
134			`wire [19:0] out_slt8;`
135			`wire [19:0] out_slt9;`
136
137			`// Serial Input register interface`
138			`wire [15:0] in_slt0;`
139			`wire [19:0] in_slt1;`
140			`wire [19:0] in_slt2;`
141			`wire [19:0] in_slt3;`
142			`wire [19:0] in_slt4;`
143			`wire [19:0] in_slt6;`
144
145			`// Serial IO Controller Interface`
146			`wire ld;`
147			`wire valid;`
148			`wire [5:0] out_le;`
149			`wire [2:0] in_valid;`
150			`wire ps_ce;`
151
152			`// Valid Sync`
153			`reg valid_s1, valid_s;`
154			`reg [2:0] in_valid_s1, in_valid_s;`
155
156			`// Out FIFO interface`
157			`wire [31:0] wb_din;`
158			`wire [1:0] o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode;`
159			`wire o3_re, o4_re, o6_re, o7_re, o8_re, o9_re;`
160			`wire o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;`
161			`wire [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;`
162			`wire o3_full, o4_full, o6_full, o7_full, o8_full, o9_full;`
163			`wire o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;`
164
165			`// In FIFO interface`
166			`wire [31:0] i3_dout, i4_dout, i6_dout;`
167			`wire [1:0] i3_mode, i4_mode, i6_mode;`
168			`wire i3_we, i4_we, i6_we;`
169			`wire i3_re, i4_re, i6_re;`
170			`wire [1:0] i3_status, i4_status, i6_status;`
171			`wire i3_full, i4_full, i6_full;`
172			`wire i3_empty, i4_empty, i6_empty;`
173
174			`// Register File Interface`
175			`wire [3:0] adr;`
176			`wire [31:0] rf_dout;`
177			`wire [31:0] rf_din;`
178			`wire rf_we;`
179			`wire rf_re;`
180			`wire ac97_rst_force;`
181			`wire resume_req;`
182			`wire crac_we;`
183			`wire [15:0] crac_din;`
184			`wire [31:0] crac_out;`
185			`wire [7:0] oc0_cfg;`
186			`wire [7:0] oc1_cfg;`
187			`wire [7:0] oc2_cfg;`
188			`wire [7:0] oc3_cfg;`
189			`wire [7:0] oc4_cfg;`
190			`wire [7:0] oc5_cfg;`
191			`wire [7:0] ic0_cfg;`
192			`wire [7:0] ic1_cfg;`
193			`wire [7:0] ic2_cfg;`
194			`wire [2:0] oc0_int_set;`
195			`wire [2:0] oc1_int_set;`
196			`wire [2:0] oc2_int_set;`
197			`wire [2:0] oc3_int_set;`
198			`wire [2:0] oc4_int_set;`
199			`wire [2:0] oc5_int_set;`
200			`wire [2:0] ic0_int_set;`
201			`wire [2:0] ic1_int_set;`
202			`wire [2:0] ic2_int_set;`
203
204			`// CRA Module interface`
205			`wire crac_valid;`
206			`wire crac_wr;`
207			`wire crac_wr_done, crac_rd_done;`
208
209			`////////////////////////////////////////////////////////////////////`
210			`//`
211			`// Misc Logic`
212			`//`
213
214			`// Sync Valid to WISHBONE Clock`
215	6	rudi	`always @(posedge clk_i)`
216	4	rudi	`valid_s1 <= #1 valid;`
217
218	6	rudi	`always @(posedge clk_i)`
219	4	rudi	`valid_s <= #1 valid_s1;`
220
221	6	rudi	`always @(posedge clk_i)`
222	4	rudi	`in_valid_s1 <= #1 in_valid;`
223
224	6	rudi	`always @(posedge clk_i)`
225	4	rudi	`in_valid_s <= #1 in_valid_s1;`
226
227			`// "valid_s" Indicates when any of the outputs to the output S/R may`
228			`// change or when outputs from input S/R may be sampled`
229			`assign o3_mode = oc0_cfg[3:2];`
230			`assign o4_mode = oc1_cfg[3:2];`
231			`assign o6_mode = oc2_cfg[3:2];`
232			`assign o7_mode = oc3_cfg[3:2];`
233			`assign o8_mode = oc4_cfg[3:2];`
234			`assign o9_mode = oc5_cfg[3:2];`
235			`assign i3_mode = ic0_cfg[3:2];`
236			`assign i4_mode = ic1_cfg[3:2];`
237			`assign i6_mode = ic2_cfg[3:2];`
238
239			`////////////////////////////////////////////////////////////////////`
240			`//`
241			`// Modules`
242			`//`
243
244			`ac97_sout u0(`
245	6	rudi	`.clk( bit_clk_pad_i ),`
246			`.rst( rst_i ),`
247	4	rudi	`.so_ld( ld ),`
248			`.slt0( out_slt0 ),`
249			`.slt1( out_slt1 ),`
250			`.slt2( out_slt2 ),`
251			`.slt3( out_slt3 ),`
252			`.slt4( out_slt4 ),`
253			`.slt6( out_slt6 ),`
254			`.slt7( out_slt7 ),`
255			`.slt8( out_slt8 ),`
256			`.slt9( out_slt9 ),`
257	6	rudi	`.sdata_out( sdata_pad_o )`
258	4	rudi	`);`
259
260			`ac97_sin u1(`
261	6	rudi	`.clk( bit_clk_pad_i ),`
262			`.rst( rst_i ),`
263	4	rudi	`.out_le( out_le ),`
264			`.slt0( in_slt0 ),`
265			`.slt1( in_slt1 ),`
266			`.slt2( in_slt2 ),`
267			`.slt3( in_slt3 ),`
268			`.slt4( in_slt4 ),`
269			`.slt6( in_slt6 ),`
270	6	rudi	`.sdata_in( sdata_pad_i )`
271	4	rudi	`);`
272
273			`ac97_soc u2(`
274	6	rudi	`.clk( bit_clk_pad_i ),`
275			`.wclk( clk_i ),`
276			`.rst( rst_i ),`
277	4	rudi	`.ps_ce( ps_ce ),`
278			`.resume( resume_req ),`
279	6	rudi	`.suspended( suspended_o ),`
280			`.sync( sync_pad_o ),`
281	4	rudi	`.out_le( out_le ),`
282			`.in_valid( in_valid ),`
283			`.ld( ld ),`
284			`.valid( valid )`
285			`);`
286
287			`ac97_out_fifo u3(`
288	6	rudi	`.clk( clk_i ),`
289			`.rst( rst_i ),`
290	4	rudi	`.en( oc0_cfg[0] ),`
291			`.mode( o3_mode ),`
292			`.din( wb_din ),`
293			`.we( o3_we ),`
294			`.dout( out_slt3 ),`
295			`.re( o3_re ),`
296			`.status( o3_status ),`
297			`.full( o3_full ),`
298			`.empty( o3_empty )`
299			`);`
300
301			`ac97_out_fifo u4(`
302	6	rudi	`.clk( clk_i ),`
303			`.rst( rst_i ),`
304	4	rudi	`.en( oc1_cfg[0] ),`
305			`.mode( o4_mode ),`
306			`.din( wb_din ),`
307			`.we( o4_we ),`
308			`.dout( out_slt4 ),`
309			`.re( o4_re ),`
310			`.status( o4_status ),`
311			`.full( o4_full ),`
312			`.empty( o4_empty )`
313			`);`
314
315	6	rudi	`ifdef AC97_CENTER
316	4	rudi	`ac97_out_fifo u5(`
317	6	rudi	`.clk( clk_i ),`
318			`.rst( rst_i ),`
319	4	rudi	`.en( oc2_cfg[0] ),`
320			`.mode( o6_mode ),`
321			`.din( wb_din ),`
322			`.we( o6_we ),`
323			`.dout( out_slt6 ),`
324			`.re( o6_re ),`
325			`.status( o6_status ),`
326			`.full( o6_full ),`
327			`.empty( o6_empty )`
328			`);`
329			`else
330	10	rudi	`assign out_slt6 = 20'h0;`
331			`assign o6_status = 2'h0;`
332			`assign o6_full = 1'b0;`
333			`assign o6_empty = 1'b0;`
334	4	rudi	`endif
335
336	6	rudi	`ifdef AC97_SURROUND
337	4	rudi	`ac97_out_fifo u6(`
338	6	rudi	`.clk( clk_i ),`
339			`.rst( rst_i ),`
340	4	rudi	`.en( oc3_cfg[0] ),`
341			`.mode( o7_mode ),`
342			`.din( wb_din ),`
343			`.we( o7_we ),`
344			`.dout( out_slt7 ),`
345			`.re( o7_re ),`
346			`.status( o7_status ),`
347			`.full( o7_full ),`
348			`.empty( o7_empty )`
349			`);`
350
351			`ac97_out_fifo u7(`
352	6	rudi	`.clk( clk_i ),`
353			`.rst( rst_i ),`
354	4	rudi	`.en( oc4_cfg[0] ),`
355			`.mode( o8_mode ),`
356			`.din( wb_din ),`
357			`.we( o8_we ),`
358			`.dout( out_slt8 ),`
359			`.re( o8_re ),`
360			`.status( o8_status ),`
361			`.full( o8_full ),`
362			`.empty( o8_empty )`
363			`);`
364			`else
365	10	rudi	`assign out_slt7 = 20'h0;`
366			`assign o7_status = 2'h0;`
367			`assign o7_full = 1'b0;`
368			`assign o7_empty = 1'b0;`
369			`assign out_slt8 = 20'h0;`
370			`assign o8_status = 2'h0;`
371			`assign o8_full = 1'b0;`
372			`assign o8_empty = 1'b0;`
373	4	rudi	`endif
374
375	6	rudi	`ifdef AC97_LFE
376	4	rudi	`ac97_out_fifo u8(`
377	6	rudi	`.clk( clk_i ),`
378			`.rst( rst_i ),`
379	4	rudi	`.en( oc5_cfg[0] ),`
380			`.mode( o9_mode ),`
381			`.din( wb_din ),`
382			`.we( o9_we ),`
383			`.dout( out_slt9 ),`
384			`.re( o9_re ),`
385			`.status( o9_status ),`
386			`.full( o9_full ),`
387			`.empty( o9_empty )`
388			`);`
389			`else
390	10	rudi	`assign out_slt9 = 20'h0;`
391			`assign o9_status = 2'h0;`
392			`assign o9_full = 1'b0;`
393			`assign o9_empty = 1'b0;`
394	4	rudi	`endif
395
396	6	rudi	`ifdef AC97_SIN
397	4	rudi	`ac97_in_fifo u9(`
398	6	rudi	`.clk( clk_i ),`
399			`.rst( rst_i ),`
400	4	rudi	`.en( ic0_cfg[0] ),`
401			`.mode( i3_mode ),`
402			`.din( in_slt3 ),`
403			`.we( i3_we ),`
404			`.dout( i3_dout ),`
405			`.re( i3_re ),`
406			`.status( i3_status ),`
407			`.full( i3_full ),`
408			`.empty( i3_empty )`
409			`);`
410
411			`ac97_in_fifo u10(`
412	6	rudi	`.clk( clk_i ),`
413			`.rst( rst_i ),`
414	4	rudi	`.en( ic1_cfg[0] ),`
415			`.mode( i4_mode ),`
416			`.din( in_slt4 ),`
417			`.we( i4_we ),`
418			`.dout( i4_dout ),`
419			`.re( i4_re ),`
420			`.status( i4_status ),`
421			`.full( i4_full ),`
422			`.empty( i4_empty )`
423			`);`
424			`else
425	10	rudi	`assign i3_dout = 20'h0;`
426			`assign i3_status = 2'h0;`
427			`assign i3_full = 1'b0;`
428			`assign i3_empty = 1'b0;`
429			`assign i4_dout = 20'h0;`
430			`assign i4_status = 2'h0;`
431			`assign i4_full = 1'b0;`
432			`assign i4_empty = 1'b0;`
433	4	rudi	`endif
434
435	6	rudi	`ifdef AC97_MICIN
436	4	rudi	`ac97_in_fifo u11(`
437	6	rudi	`.clk( clk_i ),`
438			`.rst( rst_i ),`
439	4	rudi	`.en( ic2_cfg[0] ),`
440			`.mode( i6_mode ),`
441			`.din( in_slt6 ),`
442			`.we( i6_we ),`
443			`.dout( i6_dout ),`
444			`.re( i6_re ),`
445			`.status( i6_status ),`
446			`.full( i6_full ),`
447			`.empty( i6_empty )`
448			`);`
449			`else
450	10	rudi	`assign i6_dout = 20'h0;`
451			`assign i6_status = 2'h0;`
452			`assign i6_full = 1'b0;`
453			`assign i6_empty = 1'b0;`
454	4	rudi	`endif
455
456			`ac97_wb_if u12(`
457	6	rudi	`.clk( clk_i ),`
458			`.rst( rst_i ),`
459	4	rudi	`.wb_data_i( wb_data_i ),`
460			`.wb_data_o( wb_data_o ),`
461			`.wb_addr_i( wb_addr_i ),`
462			`.wb_sel_i( wb_sel_i ),`
463			`.wb_we_i( wb_we_i ),`
464			`.wb_cyc_i( wb_cyc_i ),`
465			`.wb_stb_i( wb_stb_i ),`
466			`.wb_ack_o( wb_ack_o ),`
467			`.wb_err_o( wb_err_o ),`
468			`.adr( adr ),`
469			`.dout( wb_din ),`
470			`.rf_din( rf_dout ),`
471			`.i3_din( i3_dout ),`
472			`.i4_din( i4_dout ),`
473			`.i6_din( i6_dout ),`
474			`.rf_we( rf_we ),`
475			`.rf_re( rf_re ),`
476			`.o3_we( o3_we ),`
477			`.o4_we( o4_we ),`
478			`.o6_we( o6_we ),`
479			`.o7_we( o7_we ),`
480			`.o8_we( o8_we ),`
481			`.o9_we( o9_we ),`
482			`.i3_re( i3_re ),`
483			`.i4_re( i4_re ),`
484			`.i6_re( i6_re )`
485			`);`
486
487	6	rudi	`ac97_rf u13( .clk( clk_i ),`
488			`.rst( rst_i ),`
489	4	rudi	`.adr( adr ),`
490			`.rf_dout( rf_dout ),`
491			`.rf_din( wb_din ),`
492			`.rf_we( rf_we ),`
493			`.rf_re( rf_re ),`
494	6	rudi	`.int( int_o ),`
495	4	rudi	`.ac97_rst_force(ac97_rst_force ),`
496			`.resume_req( resume_req ),`
497	6	rudi	`.suspended( suspended_o ),`
498	4	rudi	`.crac_we( crac_we ),`
499			`.crac_din( crac_din ),`
500			`.crac_out( crac_out ),`

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