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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller Top Level                        ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_top.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
//
//  $Date: 2001-08-03 06:54:50 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1.1.1  2001/05/19 02:29:14  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_top(clk, rst,
 
        wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
        wb_stb_i, wb_ack_o, wb_err_o,
 
        int, dma_req, dma_ack,
        suspended,
 
        bit_clk, sync, sdata_out, sdata_in, ac97_reset_
        );
 
input           clk, rst;
 
// --------------------------------------
// WISHBONE SLAVE INTERFACE 
input   [31:0]   wb_data_i;
output  [31:0]   wb_data_o;
input   [31:0]   wb_addr_i;
input   [3:0]    wb_sel_i;
input           wb_we_i;
input           wb_cyc_i;
input           wb_stb_i;
output          wb_ack_o;
output          wb_err_o;
 
// --------------------------------------
// Misc Signals
output          int;
output  [8:0]    dma_req;
input   [8:0]    dma_ack;
 
// --------------------------------------
// Suspend Resume Interface
output          suspended;
 
// --------------------------------------
// AC97 Codec Interface
input           bit_clk;
output          sync;
output          sdata_out;
input           sdata_in;
output          ac97_reset_;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
// Serial Output register interface
wire    [15:0]   out_slt0;
wire    [19:0]   out_slt1;
wire    [19:0]   out_slt2;
wire    [19:0]   out_slt3;
wire    [19:0]   out_slt4;
wire    [19:0]   out_slt6;
wire    [19:0]   out_slt7;
wire    [19:0]   out_slt8;
wire    [19:0]   out_slt9;
 
// Serial Input register interface
wire    [15:0]   in_slt0;
wire    [19:0]   in_slt1;
wire    [19:0]   in_slt2;
wire    [19:0]   in_slt3;
wire    [19:0]   in_slt4;
wire    [19:0]   in_slt6;
 
// Serial IO Controller Interface
wire            sync;
wire            ld;
wire            valid;
wire    [5:0]    out_le;
wire    [2:0]    in_valid;
wire            ps_ce;
 
// Valid Sync
reg             valid_s1, valid_s;
reg     [2:0]    in_valid_s1, in_valid_s;
 
// Out FIFO interface
wire    [31:0]   wb_din;
wire    [1:0]    o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode;
wire            o3_re, o4_re, o6_re, o7_re, o8_re, o9_re;
wire            o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
wire    [1:0]    o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;
wire            o3_full, o4_full, o6_full, o7_full, o8_full, o9_full;
wire            o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;
 
// In FIFO interface
wire    [31:0]   i3_dout, i4_dout, i6_dout;
wire    [1:0]    i3_mode, i4_mode, i6_mode;
wire            i3_we, i4_we, i6_we;
wire            i3_re, i4_re, i6_re;
wire    [1:0]    i3_status, i4_status, i6_status;
wire            i3_full, i4_full, i6_full;
wire            i3_empty, i4_empty, i6_empty;
 
// Register File Interface
wire    [3:0]    adr;
wire    [31:0]   rf_dout;
wire    [31:0]   rf_din;
wire            rf_we;
wire            rf_re;
wire            int;
wire            ac97_rst_force;
wire            resume_req;
wire            crac_we;
wire    [15:0]   crac_din;
wire    [31:0]   crac_out;
wire    [7:0]    oc0_cfg;
wire    [7:0]    oc1_cfg;
wire    [7:0]    oc2_cfg;
wire    [7:0]    oc3_cfg;
wire    [7:0]    oc4_cfg;
wire    [7:0]    oc5_cfg;
wire    [7:0]    ic0_cfg;
wire    [7:0]    ic1_cfg;
wire    [7:0]    ic2_cfg;
wire    [2:0]    oc0_int_set;
wire    [2:0]    oc1_int_set;
wire    [2:0]    oc2_int_set;
wire    [2:0]    oc3_int_set;
wire    [2:0]    oc4_int_set;
wire    [2:0]    oc5_int_set;
wire    [2:0]    ic0_int_set;
wire    [2:0]    ic1_int_set;
wire    [2:0]    ic2_int_set;
 
// CRA Module interface
wire            crac_valid;
wire            crac_wr;
wire            crac_wr_done, crac_rd_done;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
// Sync Valid to WISHBONE Clock
always @(posedge clk)
        valid_s1 <= #1 valid;
 
always @(posedge clk)
        valid_s <= #1 valid_s1;
 
always @(posedge clk)
        in_valid_s1 <= #1 in_valid;
 
always @(posedge clk)
        in_valid_s <= #1 in_valid_s1;
 
// "valid_s" Indicates when any of the outputs to the output S/R may
// change or when outputs from input S/R may be sampled
assign o3_mode = oc0_cfg[3:2];
assign o4_mode = oc1_cfg[3:2];
assign o6_mode = oc2_cfg[3:2];
assign o7_mode = oc3_cfg[3:2];
assign o8_mode = oc4_cfg[3:2];
assign o9_mode = oc5_cfg[3:2];
assign i3_mode = ic0_cfg[3:2];
assign i4_mode = ic1_cfg[3:2];
assign i6_mode = ic2_cfg[3:2];
 
////////////////////////////////////////////////////////////////////
//
// Modules
//
 
ac97_sout       u0(
                .clk(           bit_clk         ),
                .rst(           rst             ),
                .so_ld(         ld              ),
                .slt0(          out_slt0        ),
                .slt1(          out_slt1        ),
                .slt2(          out_slt2        ),
                .slt3(          out_slt3        ),
                .slt4(          out_slt4        ),
                .slt6(          out_slt6        ),
                .slt7(          out_slt7        ),
                .slt8(          out_slt8        ),
                .slt9(          out_slt9        ),
                .sdata_out(     sdata_out       )
                );
 
ac97_sin        u1(
                .clk(           bit_clk         ),
                .rst(           rst             ),
                .out_le(        out_le          ),
                .slt0(          in_slt0         ),
                .slt1(          in_slt1         ),
                .slt2(          in_slt2         ),
                .slt3(          in_slt3         ),
                .slt4(          in_slt4         ),
                .slt6(          in_slt6         ),
                .sdata_in(      sdata_in        )
                );
 
ac97_soc        u2(
                .clk(           bit_clk         ),
                .wclk(          clk             ),
                .rst(           rst             ),
                .ps_ce(         ps_ce           ),
                .resume(        resume_req      ),
                .suspended(     suspended       ),
                .sync(          sync            ),
                .out_le(        out_le          ),
                .in_valid(      in_valid        ),
                .ld(            ld              ),
                .valid(         valid           )
                );
 
ac97_out_fifo   u3(
                .clk(           clk             ),
                .rst(           rst             ),
                .en(            oc0_cfg[0]       ),
                .mode(          o3_mode         ),
                .din(           wb_din          ),
                .we(            o3_we           ),
                .dout(          out_slt3        ),
                .re(            o3_re           ),
                .status(        o3_status       ),
                .full(          o3_full         ),
                .empty(         o3_empty        )
                );
 
ac97_out_fifo   u4(
                .clk(           clk             ),
                .rst(           rst             ),
                .en(            oc1_cfg[0]       ),
                .mode(          o4_mode         ),
                .din(           wb_din          ),
                .we(            o4_we           ),
                .dout(          out_slt4        ),
                .re(            o4_re           ),
                .status(        o4_status       ),
                .full(          o4_full         ),
                .empty(         o4_empty        )
                );
 
`ifdef CENTER
ac97_out_fifo   u5(
                .clk(           clk             ),
                .rst(           rst             ),
                .en(            oc2_cfg[0]       ),
                .mode(          o6_mode         ),
                .din(           wb_din          ),
                .we(            o6_we           ),
                .dout(          out_slt6        ),
                .re(            o6_re           ),
                .status(        o6_status       ),
                .full(          o6_full         ),
                .empty(         o6_empty        )
                );
`else
assign out_slt6 = 0;
assign o6_status = 0;
assign o6_full = 0;
assign o6_empty = 0;
`endif
 
`ifdef SURROUND
ac97_out_fifo   u6(
                .clk(           clk             ),
                .rst(           rst             ),
                .en(            oc3_cfg[0]       ),
                .mode(          o7_mode         ),
                .din(           wb_din          ),
                .we(            o7_we           ),
                .dout(          out_slt7        ),
                .re(            o7_re           ),
                .status(        o7_status       ),
                .full(          o7_full         ),
                .empty(         o7_empty        )
                );
 
ac97_out_fifo   u7(
                .clk(           clk             ),
                .rst(           rst             ),
                .en(            oc4_cfg[0]       ),
                .mode(          o8_mode         ),
                .din(           wb_din          ),
                .we(            o8_we           ),
                .dout(          out_slt8        ),
                .re(            o8_re           ),
                .status(        o8_status       ),
                .full(          o8_full         ),
                .empty(         o8_empty        )
                );
`else
assign out_slt7 = 0;
assign o7_status = 0;
assign o7_full = 0;
assign o7_empty = 0;
assign out_slt8 = 0;
assign o8_status = 0;
assign o8_full = 0;
assign o8_empty = 0;
`endif
 
`ifdef LFE
ac97_out_fifo   u8(
                .clk(           clk             ),
                .rst(           rst             ),
                .en(            oc5_cfg[0]       ),
                .mode(          o9_mode         ),
                .din(           wb_din          ),
                .we(            o9_we           ),
                .dout(          out_slt9        ),
                .re(            o9_re           ),
                .status(        o9_status       ),
                .full(          o9_full         ),
                .empty(         o9_empty        )
                );
`else
assign out_slt9 = 0;
assign o9_status = 0;
assign o9_full = 0;
assign o9_empty = 0;
`endif
 
`ifdef SIN
ac97_in_fifo    u9(
                .clk(           clk             ),
                .rst(           rst             ),
                .en(            ic0_cfg[0]       ),
                .mode(          i3_mode         ),
                .din(           in_slt3         ),
                .we(            i3_we           ),
                .dout(          i3_dout         ),
                .re(            i3_re           ),
                .status(        i3_status       ),
                .full(          i3_full         ),
                .empty(         i3_empty        )
                );
 
ac97_in_fifo    u10(
                .clk(           clk             ),
                .rst(           rst             ),
                .en(            ic1_cfg[0]       ),
                .mode(          i4_mode         ),
                .din(           in_slt4         ),
                .we(            i4_we           ),
                .dout(          i4_dout         ),
                .re(            i4_re           ),
                .status(        i4_status       ),
                .full(          i4_full         ),
                .empty(         i4_empty        )
                );
`else
assign i3_dout = 0;
assign i3_status = 0;
assign i3_full = 0;
assign i3_empty = 0;
assign i4_dout = 0;
assign i4_status = 0;
assign i4_full = 0;
assign i4_empty = 0;
`endif
 
`ifdef MICIN
ac97_in_fifo    u11(
                .clk(           clk             ),
                .rst(           rst             ),
                .en(            ic2_cfg[0]       ),
                .mode(          i6_mode         ),
                .din(           in_slt6         ),
                .we(            i6_we           ),
                .dout(          i6_dout         ),
                .re(            i6_re           ),
                .status(        i6_status       ),
                .full(          i6_full         ),
                .empty(         i6_empty        )
                );
`else
assign i6_dout = 0;
assign i6_status = 0;
assign i6_full = 0;
assign i6_empty = 0;
`endif
 
ac97_wb_if      u12(
                .clk(           clk             ),
                .rst(           rst             ),
                .wb_data_i(     wb_data_i       ),
                .wb_data_o(     wb_data_o       ),
                .wb_addr_i(     wb_addr_i       ),
                .wb_sel_i(      wb_sel_i        ),
                .wb_we_i(       wb_we_i         ),
                .wb_cyc_i(      wb_cyc_i        ),
                .wb_stb_i(      wb_stb_i        ),
                .wb_ack_o(      wb_ack_o        ),
                .wb_err_o(      wb_err_o        ),
                .adr(           adr             ),
                .dout(          wb_din          ),
                .rf_din(        rf_dout         ),
                .i3_din(        i3_dout         ),
                .i4_din(        i4_dout         ),
                .i6_din(        i6_dout         ),
                .rf_we(         rf_we           ),
                .rf_re(         rf_re           ),
                .o3_we(         o3_we           ),
                .o4_we(         o4_we           ),
                .o6_we(         o6_we           ),
                .o7_we(         o7_we           ),
                .o8_we(         o8_we           ),
                .o9_we(         o9_we           ),
                .i3_re(         i3_re           ),
                .i4_re(         i4_re           ),
                .i6_re(         i6_re           )
                );
 
ac97_rf u13(    .clk(           clk             ),
                .rst(           rst             ),
                .adr(           adr             ),
                .rf_dout(       rf_dout         ),
                .rf_din(        wb_din          ),
                .rf_we(         rf_we           ),
                .rf_re(         rf_re           ),
                .int(           int             ),
                .ac97_rst_force(ac97_rst_force  ),
                .resume_req(    resume_req      ),
                .suspended(     suspended       ),
                .crac_we(       crac_we         ),
                .crac_din(      crac_din        ),
                .crac_out(      crac_out        ),
                .crac_wr_done(  crac_wr_done    ),
                .crac_rd_done(  crac_rd_done    ),
                .oc0_cfg(       oc0_cfg         ),
                .oc1_cfg(       oc1_cfg         ),
                .oc2_cfg(       oc2_cfg         ),
                .oc3_cfg(       oc3_cfg         ),
                .oc4_cfg(       oc4_cfg         ),
                .oc5_cfg(       oc5_cfg         ),
                .ic0_cfg(       ic0_cfg         ),
                .ic1_cfg(       ic1_cfg         ),
                .ic2_cfg(       ic2_cfg         ),
                .oc0_int_set(   oc0_int_set     ),
                .oc1_int_set(   oc1_int_set     ),
                .oc2_int_set(   oc2_int_set     ),
                .oc3_int_set(   oc3_int_set     ),
                .oc4_int_set(   oc4_int_set     ),
                .oc5_int_set(   oc5_int_set     ),
                .ic0_int_set(   ic0_int_set     ),
                .ic1_int_set(   ic1_int_set     ),
                .ic2_int_set(   ic2_int_set     )
                );
 
ac97_prc u14(   .clk(           clk             ),
                .rst(           rst             ),
                .valid(         valid_s         ),
                .in_valid(      in_valid_s      ),
                .out_slt0(      out_slt0        ),
                .in_slt0(       in_slt0         ),
                .in_slt1(       in_slt1         ),
                .crac_valid(    crac_valid      ),
                .crac_wr(       crac_wr         ),
                .oc0_cfg(       oc0_cfg         ),
                .oc1_cfg(       oc1_cfg         ),
                .oc2_cfg(       oc2_cfg         ),
                .oc3_cfg(       oc3_cfg         ),
                .oc4_cfg(       oc4_cfg         ),
                .oc5_cfg(       oc5_cfg         ),
                .ic0_cfg(       ic0_cfg         ),
                .ic1_cfg(       ic1_cfg         ),
                .ic2_cfg(       ic2_cfg         ),
                .o3_empty(      o3_empty        ),
                .o4_empty(      o4_empty        ),
                .o6_empty(      o6_empty        ),
                .o7_empty(      o7_empty        ),
                .o8_empty(      o8_empty        ),
                .o9_empty(      o9_empty        ),
                .i3_full(       i3_full         ),
                .i4_full(       i4_full         ),
                .i6_full(       i6_full         ),
                .o3_re(         o3_re           ),
                .o4_re(         o4_re           ),
                .o6_re(         o6_re           ),
                .o7_re(         o7_re           ),
                .o8_re(         o8_re           ),
                .o9_re(         o9_re           ),
                .i3_we(         i3_we           ),
                .i4_we(         i4_we           ),
                .i6_we(         i6_we           )
                );
 
ac97_cra u15(   .clk(           clk             ),
                .rst(           rst             ),
                .crac_we(       crac_we         ),
                .crac_din(      crac_din        ),
                .crac_out(      crac_out        ),
                .crac_wr_done(  crac_wr_done    ),
                .crac_rd_done(  crac_rd_done    ),
                .valid(         valid_s         ),
                .out_slt1(      out_slt1        ),
                .out_slt2(      out_slt2        ),
                .in_slt2(       in_slt2         ),
                .crac_valid(    crac_valid      ),
                .crac_wr(       crac_wr         )
                );
 
ac97_dma_if u16(.clk(           clk             ),
                .rst(           rst             ),
                .o3_status(     o3_status       ),
                .o4_status(     o4_status       ),
                .o6_status(     o6_status       ),
                .o7_status(     o7_status       ),
                .o8_status(     o8_status       ),
                .o9_status(     o9_status       ),
                .o3_empty(      o3_empty        ),
                .o4_empty(      o4_empty        ),
                .o6_empty(      o6_empty        ),
                .o7_empty(      o7_empty        ),
                .o8_empty(      o8_empty        ),
                .o9_empty(      o9_empty        ),
                .i3_status(     i3_status       ),
                .i4_status(     i4_status       ),
                .i6_status(     i6_status       ),
                .i3_full(       i3_full         ),
                .i4_full(       i4_full         ),
                .i6_full(       i6_full         ),
                .oc0_cfg(       oc0_cfg         ),
                .oc1_cfg(       oc1_cfg         ),
                .oc2_cfg(       oc2_cfg         ),
                .oc3_cfg(       oc3_cfg         ),
                .oc4_cfg(       oc4_cfg         ),
                .oc5_cfg(       oc5_cfg         ),
                .ic0_cfg(       ic0_cfg         ),
                .ic1_cfg(       ic1_cfg         ),
                .ic2_cfg(       ic2_cfg         ),
                .dma_req(       dma_req         ),
                .dma_ack(       dma_ack         )
                );
 
ac97_int        u17(
                .clk(           clk             ),
                .rst(           rst             ),
                .int_set(       oc0_int_set     ),
                .cfg(           oc0_cfg         ),
                .status(        o3_status       ),
                .full_empty(    o3_empty        ),
                .full(          o3_full         ),
                .empty(         o3_empty        ),
                .re(            o3_re           ),
                .we(            o3_we           )
                );
 
ac97_int        u18(
                .clk(           clk             ),
                .rst(           rst             ),
                .int_set(       oc1_int_set     ),
                .cfg(           oc1_cfg         ),
                .status(        o4_status       ),
                .full_empty(    o4_empty        ),
                .full(          o4_full         ),
                .empty(         o4_empty        ),
                .re(            o4_re           ),
                .we(            o4_we           )
                );
 
`ifdef CENTER
ac97_int        u19(
                .clk(           clk             ),
                .rst(           rst             ),
                .int_set(       oc2_int_set     ),
                .cfg(           oc2_cfg         ),
                .status(        o6_status       ),
                .full_empty(    o6_empty        ),
                .full(          o6_full         ),
                .empty(         o6_empty        ),
                .re(            o6_re           ),
                .we(            o6_we           )
                );
`else
assign oc2_int_set = 0;
`endif
 
`ifdef SURROUND
ac97_int        u20(
                .clk(           clk             ),
                .rst(           rst             ),
                .int_set(       oc3_int_set     ),
                .cfg(           oc3_cfg         ),
                .status(        o7_status       ),
                .full_empty(    o7_empty        ),
                .full(          o7_full         ),
                .empty(         o7_empty        ),
                .re(            o7_re           ),
                .we(            o7_we           )
                );
 
ac97_int        u21(
                .clk(           clk             ),
                .rst(           rst             ),
                .int_set(       oc4_int_set     ),
                .cfg(           oc4_cfg         ),
                .status(        o8_status       ),
                .full_empty(    o8_empty        ),
                .full(          o8_full         ),
                .empty(         o8_empty        ),
                .re(            o8_re           ),
                .we(            o8_we           )
                );
`else
assign oc3_int_set = 0;
assign oc4_int_set = 0;
`endif
 
`ifdef LFE
ac97_int        u22(
                .clk(           clk             ),
                .rst(           rst             ),
                .int_set(       oc5_int_set     ),
                .cfg(           oc5_cfg         ),
                .status(        o9_status       ),
                .full_empty(    o9_empty        ),
                .full(          o9_full         ),
                .empty(         o9_empty        ),
                .re(            o9_re           ),
                .we(            o9_we           )
                );
`else
assign oc5_int_set = 0;
`endif
 
`ifdef SIN
ac97_int        u23(
                .clk(           clk             ),
                .rst(           rst             ),
                .int_set(       ic0_int_set     ),
                .cfg(           ic0_cfg         ),
                .status(        i3_status       ),
                .full_empty(    i3_full         ),
                .full(          i3_full         ),
                .empty(         i3_empty        ),
                .re(            i3_re           ),
                .we(            i3_we           )
                );
 
ac97_int        u24(
                .clk(           clk             ),
                .rst(           rst             ),
                .int_set(       ic1_int_set     ),
                .cfg(           ic1_cfg         ),
                .status(        i4_status       ),
                .full_empty(    i4_full         ),
                .full(          i4_full         ),
                .empty(         i4_empty        ),
                .re(            i4_re           ),
                .we(            i4_we           )
                );
`else
assign ic0_int_set = 0;
assign ic1_int_set = 0;
`endif
 
`ifdef MICIN
ac97_int        u25(
                .clk(           clk             ),
                .rst(           rst             ),
                .int_set(       ic2_int_set     ),
                .cfg(           ic2_cfg         ),
                .status(        i6_status       ),
                .full_empty(    i6_full         ),
                .full(          i6_full         ),
                .empty(         i6_empty        ),
                .re(            i6_re           ),
                .we(            i6_we           )
                );
`else
assign ic2_int_set = 0;
`endif
 
ac97_rst        u26(
                .clk(           clk                             ),
                .rst(           rst                             ),
                .rst_force(     ac97_rst_force                  ),
                .ps_ce(         ps_ce                           ),
                .ac97_rst_(     ac97_reset_                     )
                );
 
endmodule
 

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_top.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller Top Level ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: ac97_top.v,v 1.1 2001-08-03 06:54:50 rudi Exp $`
41			`//`
42			`// $Date: 2001-08-03 06:54:50 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`// Revision 1.1.1.1 2001/05/19 02:29:14 rudi`
51			`// Initial Checkin`
52			`//`
53			`//`
54			`//`
55			`//`
56
57			`include "ac97_defines.v"
58
59			`module ac97_top(clk, rst,`
60
61			`wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
62			`wb_stb_i, wb_ack_o, wb_err_o,`
63
64			`int, dma_req, dma_ack,`
65			`suspended,`
66
67			`bit_clk, sync, sdata_out, sdata_in, ac97_reset_`
68			`);`
69
70			`input clk, rst;`
71
72			`// --------------------------------------`
73			`// WISHBONE SLAVE INTERFACE`
74			`input [31:0] wb_data_i;`
75			`output [31:0] wb_data_o;`
76			`input [31:0] wb_addr_i;`
77			`input [3:0] wb_sel_i;`
78			`input wb_we_i;`
79			`input wb_cyc_i;`
80			`input wb_stb_i;`
81			`output wb_ack_o;`
82			`output wb_err_o;`
83
84			`// --------------------------------------`
85			`// Misc Signals`
86			`output int;`
87			`output [8:0] dma_req;`
88			`input [8:0] dma_ack;`
89
90			`// --------------------------------------`
91			`// Suspend Resume Interface`
92			`output suspended;`
93
94			`// --------------------------------------`
95			`// AC97 Codec Interface`
96			`input bit_clk;`
97			`output sync;`
98			`output sdata_out;`
99			`input sdata_in;`
100			`output ac97_reset_;`
101
102			`////////////////////////////////////////////////////////////////////`
103			`//`
104			`// Local Wires`
105			`//`
106
107			`// Serial Output register interface`
108			`wire [15:0] out_slt0;`
109			`wire [19:0] out_slt1;`
110			`wire [19:0] out_slt2;`
111			`wire [19:0] out_slt3;`
112			`wire [19:0] out_slt4;`
113			`wire [19:0] out_slt6;`
114			`wire [19:0] out_slt7;`
115			`wire [19:0] out_slt8;`
116			`wire [19:0] out_slt9;`
117
118			`// Serial Input register interface`
119			`wire [15:0] in_slt0;`
120			`wire [19:0] in_slt1;`
121			`wire [19:0] in_slt2;`
122			`wire [19:0] in_slt3;`
123			`wire [19:0] in_slt4;`
124			`wire [19:0] in_slt6;`
125
126			`// Serial IO Controller Interface`
127			`wire sync;`
128			`wire ld;`
129			`wire valid;`
130			`wire [5:0] out_le;`
131			`wire [2:0] in_valid;`
132			`wire ps_ce;`
133
134			`// Valid Sync`
135			`reg valid_s1, valid_s;`
136			`reg [2:0] in_valid_s1, in_valid_s;`
137
138			`// Out FIFO interface`
139			`wire [31:0] wb_din;`
140			`wire [1:0] o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode;`
141			`wire o3_re, o4_re, o6_re, o7_re, o8_re, o9_re;`
142			`wire o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;`
143			`wire [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;`
144			`wire o3_full, o4_full, o6_full, o7_full, o8_full, o9_full;`
145			`wire o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;`
146
147			`// In FIFO interface`
148			`wire [31:0] i3_dout, i4_dout, i6_dout;`
149			`wire [1:0] i3_mode, i4_mode, i6_mode;`
150			`wire i3_we, i4_we, i6_we;`
151			`wire i3_re, i4_re, i6_re;`
152			`wire [1:0] i3_status, i4_status, i6_status;`
153			`wire i3_full, i4_full, i6_full;`
154			`wire i3_empty, i4_empty, i6_empty;`
155
156			`// Register File Interface`
157			`wire [3:0] adr;`
158			`wire [31:0] rf_dout;`
159			`wire [31:0] rf_din;`
160			`wire rf_we;`
161			`wire rf_re;`
162			`wire int;`
163			`wire ac97_rst_force;`
164			`wire resume_req;`
165			`wire crac_we;`
166			`wire [15:0] crac_din;`
167			`wire [31:0] crac_out;`
168			`wire [7:0] oc0_cfg;`
169			`wire [7:0] oc1_cfg;`
170			`wire [7:0] oc2_cfg;`
171			`wire [7:0] oc3_cfg;`
172			`wire [7:0] oc4_cfg;`
173			`wire [7:0] oc5_cfg;`
174			`wire [7:0] ic0_cfg;`
175			`wire [7:0] ic1_cfg;`
176			`wire [7:0] ic2_cfg;`
177			`wire [2:0] oc0_int_set;`
178			`wire [2:0] oc1_int_set;`
179			`wire [2:0] oc2_int_set;`
180			`wire [2:0] oc3_int_set;`
181			`wire [2:0] oc4_int_set;`
182			`wire [2:0] oc5_int_set;`
183			`wire [2:0] ic0_int_set;`
184			`wire [2:0] ic1_int_set;`
185			`wire [2:0] ic2_int_set;`
186
187			`// CRA Module interface`
188			`wire crac_valid;`
189			`wire crac_wr;`
190			`wire crac_wr_done, crac_rd_done;`
191
192			`////////////////////////////////////////////////////////////////////`
193			`//`
194			`// Misc Logic`
195			`//`
196
197			`// Sync Valid to WISHBONE Clock`
198			`always @(posedge clk)`
199			`valid_s1 <= #1 valid;`
200
201			`always @(posedge clk)`
202			`valid_s <= #1 valid_s1;`
203
204			`always @(posedge clk)`
205			`in_valid_s1 <= #1 in_valid;`
206
207			`always @(posedge clk)`
208			`in_valid_s <= #1 in_valid_s1;`
209
210			`// "valid_s" Indicates when any of the outputs to the output S/R may`
211			`// change or when outputs from input S/R may be sampled`
212			`assign o3_mode = oc0_cfg[3:2];`
213			`assign o4_mode = oc1_cfg[3:2];`
214			`assign o6_mode = oc2_cfg[3:2];`
215			`assign o7_mode = oc3_cfg[3:2];`
216			`assign o8_mode = oc4_cfg[3:2];`
217			`assign o9_mode = oc5_cfg[3:2];`
218			`assign i3_mode = ic0_cfg[3:2];`
219			`assign i4_mode = ic1_cfg[3:2];`
220			`assign i6_mode = ic2_cfg[3:2];`
221
222			`////////////////////////////////////////////////////////////////////`
223			`//`
224			`// Modules`
225			`//`
226
227			`ac97_sout u0(`
228			`.clk( bit_clk ),`
229			`.rst( rst ),`
230			`.so_ld( ld ),`
231			`.slt0( out_slt0 ),`
232			`.slt1( out_slt1 ),`
233			`.slt2( out_slt2 ),`
234			`.slt3( out_slt3 ),`
235			`.slt4( out_slt4 ),`
236			`.slt6( out_slt6 ),`
237			`.slt7( out_slt7 ),`
238			`.slt8( out_slt8 ),`
239			`.slt9( out_slt9 ),`
240			`.sdata_out( sdata_out )`
241			`);`
242
243			`ac97_sin u1(`
244			`.clk( bit_clk ),`
245			`.rst( rst ),`
246			`.out_le( out_le ),`
247			`.slt0( in_slt0 ),`
248			`.slt1( in_slt1 ),`
249			`.slt2( in_slt2 ),`
250			`.slt3( in_slt3 ),`
251			`.slt4( in_slt4 ),`
252			`.slt6( in_slt6 ),`
253			`.sdata_in( sdata_in )`
254			`);`
255
256			`ac97_soc u2(`
257			`.clk( bit_clk ),`
258			`.wclk( clk ),`
259			`.rst( rst ),`
260			`.ps_ce( ps_ce ),`
261			`.resume( resume_req ),`
262			`.suspended( suspended ),`
263			`.sync( sync ),`
264			`.out_le( out_le ),`
265			`.in_valid( in_valid ),`
266			`.ld( ld ),`
267			`.valid( valid )`
268			`);`
269
270			`ac97_out_fifo u3(`
271			`.clk( clk ),`
272			`.rst( rst ),`
273			`.en( oc0_cfg[0] ),`
274			`.mode( o3_mode ),`
275			`.din( wb_din ),`
276			`.we( o3_we ),`
277			`.dout( out_slt3 ),`
278			`.re( o3_re ),`
279			`.status( o3_status ),`
280			`.full( o3_full ),`
281			`.empty( o3_empty )`
282			`);`
283
284			`ac97_out_fifo u4(`
285			`.clk( clk ),`
286			`.rst( rst ),`
287			`.en( oc1_cfg[0] ),`
288			`.mode( o4_mode ),`
289			`.din( wb_din ),`
290			`.we( o4_we ),`
291			`.dout( out_slt4 ),`
292			`.re( o4_re ),`
293			`.status( o4_status ),`
294			`.full( o4_full ),`
295			`.empty( o4_empty )`
296			`);`
297
298			`ifdef CENTER
299			`ac97_out_fifo u5(`
300			`.clk( clk ),`
301			`.rst( rst ),`
302			`.en( oc2_cfg[0] ),`
303			`.mode( o6_mode ),`
304			`.din( wb_din ),`
305			`.we( o6_we ),`
306			`.dout( out_slt6 ),`
307			`.re( o6_re ),`
308			`.status( o6_status ),`
309			`.full( o6_full ),`
310			`.empty( o6_empty )`
311			`);`
312			`else
313			`assign out_slt6 = 0;`
314			`assign o6_status = 0;`
315			`assign o6_full = 0;`
316			`assign o6_empty = 0;`
317			`endif
318
319			`ifdef SURROUND
320			`ac97_out_fifo u6(`
321			`.clk( clk ),`
322			`.rst( rst ),`
323			`.en( oc3_cfg[0] ),`
324			`.mode( o7_mode ),`
325			`.din( wb_din ),`
326			`.we( o7_we ),`
327			`.dout( out_slt7 ),`
328			`.re( o7_re ),`
329			`.status( o7_status ),`
330			`.full( o7_full ),`
331			`.empty( o7_empty )`
332			`);`
333
334			`ac97_out_fifo u7(`
335			`.clk( clk ),`
336			`.rst( rst ),`
337			`.en( oc4_cfg[0] ),`
338			`.mode( o8_mode ),`
339			`.din( wb_din ),`
340			`.we( o8_we ),`
341			`.dout( out_slt8 ),`
342			`.re( o8_re ),`
343			`.status( o8_status ),`
344			`.full( o8_full ),`
345			`.empty( o8_empty )`
346			`);`
347			`else
348			`assign out_slt7 = 0;`
349			`assign o7_status = 0;`
350			`assign o7_full = 0;`
351			`assign o7_empty = 0;`
352			`assign out_slt8 = 0;`
353			`assign o8_status = 0;`
354			`assign o8_full = 0;`
355			`assign o8_empty = 0;`
356			`endif
357
358			`ifdef LFE
359			`ac97_out_fifo u8(`
360			`.clk( clk ),`
361			`.rst( rst ),`
362			`.en( oc5_cfg[0] ),`
363			`.mode( o9_mode ),`
364			`.din( wb_din ),`
365			`.we( o9_we ),`
366			`.dout( out_slt9 ),`
367			`.re( o9_re ),`
368			`.status( o9_status ),`
369			`.full( o9_full ),`
370			`.empty( o9_empty )`
371			`);`
372			`else
373			`assign out_slt9 = 0;`
374			`assign o9_status = 0;`
375			`assign o9_full = 0;`
376			`assign o9_empty = 0;`
377			`endif
378
379			`ifdef SIN
380			`ac97_in_fifo u9(`
381			`.clk( clk ),`
382			`.rst( rst ),`
383			`.en( ic0_cfg[0] ),`
384			`.mode( i3_mode ),`
385			`.din( in_slt3 ),`
386			`.we( i3_we ),`
387			`.dout( i3_dout ),`
388			`.re( i3_re ),`
389			`.status( i3_status ),`
390			`.full( i3_full ),`
391			`.empty( i3_empty )`
392			`);`
393
394			`ac97_in_fifo u10(`
395			`.clk( clk ),`
396			`.rst( rst ),`
397			`.en( ic1_cfg[0] ),`
398			`.mode( i4_mode ),`
399			`.din( in_slt4 ),`
400			`.we( i4_we ),`
401			`.dout( i4_dout ),`
402			`.re( i4_re ),`
403			`.status( i4_status ),`
404			`.full( i4_full ),`
405			`.empty( i4_empty )`
406			`);`
407			`else
408			`assign i3_dout = 0;`
409			`assign i3_status = 0;`
410			`assign i3_full = 0;`
411			`assign i3_empty = 0;`
412			`assign i4_dout = 0;`
413			`assign i4_status = 0;`
414			`assign i4_full = 0;`
415			`assign i4_empty = 0;`
416			`endif
417
418			`ifdef MICIN
419			`ac97_in_fifo u11(`
420			`.clk( clk ),`
421			`.rst( rst ),`
422			`.en( ic2_cfg[0] ),`
423			`.mode( i6_mode ),`
424			`.din( in_slt6 ),`
425			`.we( i6_we ),`
426			`.dout( i6_dout ),`
427			`.re( i6_re ),`
428			`.status( i6_status ),`
429			`.full( i6_full ),`
430			`.empty( i6_empty )`
431			`);`
432			`else
433			`assign i6_dout = 0;`
434			`assign i6_status = 0;`
435			`assign i6_full = 0;`
436			`assign i6_empty = 0;`
437			`endif
438
439			`ac97_wb_if u12(`
440			`.clk( clk ),`
441			`.rst( rst ),`
442			`.wb_data_i( wb_data_i ),`
443			`.wb_data_o( wb_data_o ),`
444			`.wb_addr_i( wb_addr_i ),`
445			`.wb_sel_i( wb_sel_i ),`
446			`.wb_we_i( wb_we_i ),`
447			`.wb_cyc_i( wb_cyc_i ),`
448			`.wb_stb_i( wb_stb_i ),`
449			`.wb_ack_o( wb_ack_o ),`
450			`.wb_err_o( wb_err_o ),`
451			`.adr( adr ),`
452			`.dout( wb_din ),`
453			`.rf_din( rf_dout ),`
454			`.i3_din( i3_dout ),`
455			`.i4_din( i4_dout ),`
456			`.i6_din( i6_dout ),`
457			`.rf_we( rf_we ),`
458			`.rf_re( rf_re ),`
459			`.o3_we( o3_we ),`
460			`.o4_we( o4_we ),`
461			`.o6_we( o6_we ),`
462			`.o7_we( o7_we ),`
463			`.o8_we( o8_we ),`
464			`.o9_we( o9_we ),`
465			`.i3_re( i3_re ),`
466			`.i4_re( i4_re ),`
467			`.i6_re( i6_re )`
468			`);`
469
470			`ac97_rf u13( .clk( clk ),`
471			`.rst( rst ),`
472			`.adr( adr ),`
473			`.rf_dout( rf_dout ),`
474			`.rf_din( wb_din ),`
475			`.rf_we( rf_we ),`
476			`.rf_re( rf_re ),`
477			`.int( int ),`
478			`.ac97_rst_force(ac97_rst_force ),`
479			`.resume_req( resume_req ),`
480			`.suspended( suspended ),`
481			`.crac_we( crac_we ),`
482			`.crac_din( crac_din ),`
483			`.crac_out( crac_out ),`
484			`.crac_wr_done( crac_wr_done ),`
485			`.crac_rd_done( crac_rd_done ),`
486			`.oc0_cfg( oc0_cfg ),`
487			`.oc1_cfg( oc1_cfg ),`
488			`.oc2_cfg( oc2_cfg ),`
489			`.oc3_cfg( oc3_cfg ),`
490			`.oc4_cfg( oc4_cfg ),`
491			`.oc5_cfg( oc5_cfg ),`
492			`.ic0_cfg( ic0_cfg ),`
493			`.ic1_cfg( ic1_cfg ),`
494			`.ic2_cfg( ic2_cfg ),`
495			`.oc0_int_set( oc0_int_set ),`
496			`.oc1_int_set( oc1_int_set ),`
497			`.oc2_int_set( oc2_int_set ),`
498			`.oc3_int_set( oc3_int_set ),`
499			`.oc4_int_set( oc4_int_set ),`
500			`.oc5_int_set( oc5_int_set ),`
501			`.ic0_int_set( ic0_int_set ),`
502			`.ic1_int_set( ic1_int_set ),`
503			`.ic2_int_set( ic2_int_set )`
504			`);`
505
506			`ac97_prc u14( .clk( clk ),`
507			`.rst( rst ),`
508			`.valid( valid_s ),`
509			`.in_valid( in_valid_s ),`
510			`.out_slt0( out_slt0 ),`
511			`.in_slt0( in_slt0 ),`
512			`.in_slt1( in_slt1 ),`
513			`.crac_valid( crac_valid ),`
514			`.crac_wr( crac_wr ),`
515			`.oc0_cfg( oc0_cfg ),`
516			`.oc1_cfg( oc1_cfg ),`
517			`.oc2_cfg( oc2_cfg ),`
518			`.oc3_cfg( oc3_cfg ),`
519			`.oc4_cfg( oc4_cfg ),`
520			`.oc5_cfg( oc5_cfg ),`
521			`.ic0_cfg( ic0_cfg ),`
522			`.ic1_cfg( ic1_cfg ),`
523			`.ic2_cfg( ic2_cfg ),`
524			`.o3_empty( o3_empty ),`
525			`.o4_empty( o4_empty ),`
526			`.o6_empty( o6_empty ),`
527			`.o7_empty( o7_empty ),`
528			`.o8_empty( o8_empty ),`
529			`.o9_empty( o9_empty ),`
530			`.i3_full( i3_full ),`
531			`.i4_full( i4_full ),`
532			`.i6_full( i6_full ),`
533			`.o3_re( o3_re ),`
534			`.o4_re( o4_re ),`
535			`.o6_re( o6_re ),`
536			`.o7_re( o7_re ),`
537			`.o8_re( o8_re ),`
538			`.o9_re( o9_re ),`
539			`.i3_we( i3_we ),`
540			`.i4_we( i4_we ),`
541			`.i6_we( i6_we )`
542			`);`
543
544			`ac97_cra u15( .clk( clk ),`
545			`.rst( rst ),`
546			`.crac_we( crac_we ),`
547			`.crac_din( crac_din ),`
548			`.crac_out( crac_out ),`
549			`.crac_wr_done( crac_wr_done ),`
550			`.crac_rd_done( crac_rd_done ),`
551			`.valid( valid_s ),`
552			`.out_slt1( out_slt1 ),`
553			`.out_slt2( out_slt2 ),`
554			`.in_slt2( in_slt2 ),`
555			`.crac_valid( crac_valid ),`
556			`.crac_wr( crac_wr )`
557			`);`
558
559			`ac97_dma_if u16(.clk( clk ),`
560			`.rst( rst ),`
561			`.o3_status( o3_status ),`
562			`.o4_status( o4_status ),`
563			`.o6_status( o6_status ),`
564			`.o7_status( o7_status ),`
565			`.o8_status( o8_status ),`
566			`.o9_status( o9_status ),`
567			`.o3_empty( o3_empty ),`
568			`.o4_empty( o4_empty ),`
569			`.o6_empty( o6_empty ),`
570			`.o7_empty( o7_empty ),`
571			`.o8_empty( o8_empty ),`
572			`.o9_empty( o9_empty ),`
573			`.i3_status( i3_status ),`
574			`.i4_status( i4_status ),`
575			`.i6_status( i6_status ),`
576			`.i3_full( i3_full ),`
577			`.i4_full( i4_full ),`
578			`.i6_full( i6_full ),`
579			`.oc0_cfg( oc0_cfg ),`
580			`.oc1_cfg( oc1_cfg ),`
581			`.oc2_cfg( oc2_cfg ),`
582			`.oc3_cfg( oc3_cfg ),`
583			`.oc4_cfg( oc4_cfg ),`
584			`.oc5_cfg( oc5_cfg ),`
585			`.ic0_cfg( ic0_cfg ),`
586			`.ic1_cfg( ic1_cfg ),`
587			`.ic2_cfg( ic2_cfg ),`
588			`.dma_req( dma_req ),`
589			`.dma_ack( dma_ack )`
590			`);`
591
592			`ac97_int u17(`
593			`.clk( clk ),`
594			`.rst( rst ),`
595			`.int_set( oc0_int_set ),`
596			`.cfg( oc0_cfg ),`
597			`.status( o3_status ),`
598			`.full_empty( o3_empty ),`
599			`.full( o3_full ),`
600			`.empty( o3_empty ),`
601			`.re( o3_re ),`
602			`.we( o3_we )`
603			`);`
604
605			`ac97_int u18(`
606			`.clk( clk ),`
607			`.rst( rst ),`
608			`.int_set( oc1_int_set ),`
609			`.cfg( oc1_cfg ),`
610			`.status( o4_status ),`
611			`.full_empty( o4_empty ),`
612			`.full( o4_full ),`
613			`.empty( o4_empty ),`
614			`.re( o4_re ),`
615			`.we( o4_we )`
616			`);`
617
618			`ifdef CENTER
619			`ac97_int u19(`
620			`.clk( clk ),`
621			`.rst( rst ),`
622			`.int_set( oc2_int_set ),`
623			`.cfg( oc2_cfg ),`
624			`.status( o6_status ),`
625			`.full_empty( o6_empty ),`
626			`.full( o6_full ),`
627			`.empty( o6_empty ),`
628			`.re( o6_re ),`
629			`.we( o6_we )`
630			`);`
631			`else
632			`assign oc2_int_set = 0;`
633			`endif
634
635			`ifdef SURROUND
636			`ac97_int u20(`
637			`.clk( clk ),`
638			`.rst( rst ),`
639			`.int_set( oc3_int_set ),`
640			`.cfg( oc3_cfg ),`
641			`.status( o7_status ),`
642			`.full_empty( o7_empty ),`
643			`.full( o7_full ),`
644			`.empty( o7_empty ),`
645			`.re( o7_re ),`
646			`.we( o7_we )`
647			`);`
648
649			`ac97_int u21(`
650			`.clk( clk ),`
651			`.rst( rst ),`
652			`.int_set( oc4_int_set ),`
653			`.cfg( oc4_cfg ),`
654			`.status( o8_status ),`
655			`.full_empty( o8_empty ),`
656			`.full( o8_full ),`
657			`.empty( o8_empty ),`
658			`.re( o8_re ),`
659			`.we( o8_we )`
660			`);`
661			`else
662			`assign oc3_int_set = 0;`
663			`assign oc4_int_set = 0;`
664			`endif
665
666			`ifdef LFE
667			`ac97_int u22(`
668			`.clk( clk ),`
669			`.rst( rst ),`
670			`.int_set( oc5_int_set ),`
671			`.cfg( oc5_cfg ),`
672			`.status( o9_status ),`
673			`.full_empty( o9_empty ),`
674			`.full( o9_full ),`
675			`.empty( o9_empty ),`
676			`.re( o9_re ),`
677			`.we( o9_we )`
678			`);`
679			`else
680			`assign oc5_int_set = 0;`
681			`endif
682
683			`ifdef SIN
684			`ac97_int u23(`
685			`.clk( clk ),`
686			`.rst( rst ),`
687			`.int_set( ic0_int_set ),`
688			`.cfg( ic0_cfg ),`
689			`.status( i3_status ),`
690			`.full_empty( i3_full ),`
691			`.full( i3_full ),`
692			`.empty( i3_empty ),`
693			`.re( i3_re ),`
694			`.we( i3_we )`
695			`);`
696
697			`ac97_int u24(`
698			`.clk( clk ),`
699			`.rst( rst ),`
700			`.int_set( ic1_int_set ),`
701			`.cfg( ic1_cfg ),`
702			`.status( i4_status ),`
703			`.full_empty( i4_full ),`
704			`.full( i4_full ),`
705			`.empty( i4_empty ),`
706			`.re( i4_re ),`
707			`.we( i4_we )`
708			`);`
709			`else
710			`assign ic0_int_set = 0;`
711			`assign ic1_int_set = 0;`
712			`endif
713
714			`ifdef MICIN
715			`ac97_int u25(`
716			`.clk( clk ),`
717			`.rst( rst ),`
718			`.int_set( ic2_int_set ),`
719			`.cfg( ic2_cfg ),`
720			`.status( i6_status ),`
721			`.full_empty( i6_full ),`
722			`.full( i6_full ),`
723			`.empty( i6_empty ),`
724			`.re( i6_re ),`
725			`.we( i6_we )`
726			`);`
727			`else
728			`assign ic2_int_set = 0;`
729			`endif
730
731			`ac97_rst u26(`
732			`.clk( clk ),`
733			`.rst( rst ),`
734			`.rst_force( ac97_rst_force ),`
735			`.ps_ce( ps_ce ),`
736			`.ac97_rst_( ac97_reset_ )`
737			`);`
738
739			`endmodule`
740