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8 |
rudi |
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all: sim
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SHELL = /bin/sh
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MS="-s"
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##########################################################################
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#
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# DUT Sources
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#
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##########################################################################
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DUT_SRC_DIR=../../../rtl/verilog
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_TARGETS_= $(DUT_SRC_DIR)/ac97_top.v \
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$(DUT_SRC_DIR)/ac97_sout.v \
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$(DUT_SRC_DIR)/ac97_sin.v \
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$(DUT_SRC_DIR)/ac97_soc.v \
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$(DUT_SRC_DIR)/ac97_out_fifo.v \
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$(DUT_SRC_DIR)/ac97_in_fifo.v \
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$(DUT_SRC_DIR)/ac97_wb_if.v \
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$(DUT_SRC_DIR)/ac97_rf.v \
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$(DUT_SRC_DIR)/ac97_prc.v \
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$(DUT_SRC_DIR)/ac97_fifo_ctrl.v \
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| 22 |
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$(DUT_SRC_DIR)/ac97_cra.v \
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$(DUT_SRC_DIR)/ac97_dma_if.v \
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$(DUT_SRC_DIR)/ac97_dma_req.v \
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$(DUT_SRC_DIR)/ac97_int.v \
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$(DUT_SRC_DIR)/ac97_rst.v
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| 28 |
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##########################################################################
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#
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# Test Bench Sources
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#
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##########################################################################
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_TOP_=test
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TB_SRC_DIR=../../../bench/verilog
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_TB_= $(TB_SRC_DIR)/ac97_codec_sout.v \
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$(TB_SRC_DIR)/ac97_codec_sin.v \
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| 37 |
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$(TB_SRC_DIR)/ac97_codec_top.v \
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$(TB_SRC_DIR)/test_bench_top.v \
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| 39 |
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$(TB_SRC_DIR)/wb_mast_model.v
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| 40 |
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##########################################################################
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#
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# Misc Variables
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| 44 |
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#
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| 45 |
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##########################################################################
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| 46 |
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| 47 |
10 |
rudi |
INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
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| 48 |
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LOGF=-l .nclog
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| 49 |
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#NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
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UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
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GATE_NETLIST = ../../../syn/out/mc_top_ps.v
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| 52 |
8 |
rudi |
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| 53 |
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##########################################################################
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#
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# Make Targets
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| 56 |
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#
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| 57 |
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##########################################################################
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| 58 |
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ss:
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signalscan -do waves/waves.do -waves waves/waves.trn &
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| 61 |
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| 62 |
10 |
rudi |
simw:
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@$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
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| 64 |
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| 65 |
8 |
rudi |
simxl:
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| 66 |
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verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \
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| 67 |
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$(_TARGETS_) $(_TB_)
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| 68 |
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| 69 |
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sim:
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| 70 |
10 |
rudi |
ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
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| 71 |
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$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
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| 72 |
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+ncuid+`hostname`
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| 73 |
8 |
rudi |
|
| 74 |
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hal:
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| 75 |
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@echo ""
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| 76 |
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@echo "----- Running HAL ... ----------"
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| 77 |
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@hal +incdir+$(DUT_SRC_DIR) \
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| 78 |
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-NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \
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| 79 |
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$(_TARGETS_)
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| 80 |
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@echo "----- DONE ... ----------"
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| 81 |
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| 82 |
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clean:
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| 83 |
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rm -rf ./waves/*.dsn ./waves/*.trn \
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| 84 |
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ncwork/.inc* ncwork/inc* \
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| 85 |
10 |
rudi |
./verilog.* .nclog hal.log \
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| 86 |
|
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INCA_libs/
|
| 87 |
8 |
rudi |
|
| 88 |
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##########################################################################
|
| 89 |
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