OpenCores
URL https://opencores.org/ocsvn/acxbrd/acxbrd/trunk

Subversion Repositories acxbrd

[/] [acxbrd/] [trunk/] [confppa.vhd] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 martin
--
2
--      confppa.vhd
3
--
4
--      configuration ACEX from ROM in PPA mode
5
--      Pinout for BB KFL board
6
--      
7
--      resources on MAX7032
8
--
9
--              32 LCs !!!
10
--
11
--      timing for ACEX:
12
--              nConfig low                                                     min 2 us
13
--              nConfig high to nStatus high            max 4 us
14
--              nConfig high to nWS rising edge         max 5 us
15
--              nWS pulse width                                         min 200 ns
16
--              nStatus high to first rising DCLK       min 1 us
17
--              DCLK clk                                                        max 33.3 MHz
18
--
19
--      for simpler config wait tbusy+trdy2ws+tws2b befor next byte
20
--              1.6 us + 50 ns + 50 ns
21
--
22
--
23
--      todo:
24
--
25
--
26
--      2001-10-26      creation
27
--      2002-01-11      changed clock div to 32 for 7.3 MHz
28
--
29
 
30
 
31
library ieee ;
32
use ieee.std_logic_1164.all ;
33
use ieee.std_logic_unsigned.all;
34
 
35
entity confppa is
36
 
37
port (
38
        clk             : in std_logic;
39
        nreset  : in std_logic;
40
 
41
        a               : out std_logic_vector(16 downto 0);     -- FLASH adr
42
        noe_in  : in std_logic;                                                 -- input from ACEX
43
        nce_in  : in std_logic;                                                 -- input from ACEX
44
        noe             : out std_logic;                                                -- output to FLASH
45
        nce             : out std_logic;                                                -- output to FLASH
46
        d0in    : in std_logic;                                                 -- D0 from FLASH
47
        d0out   : out std_logic;                                                -- reseved DATA0 to ACEX
48
 
49
        nconf   : out std_logic;                                                -- ACEX nConfig
50
        nstatus : in std_logic;                                                 -- ACEX nStatus                 -- not used
51
        conf_done       : in std_logic;                                         -- ACEX conf_done
52
 
53
        csacx   : out std_logic;                                                -- ACEX CS ???
54
        nws             : out std_logic;                                                -- ACEX nWS
55
        nbsy    : in std_logic;                                                 -- ACEX RDYnBSY                 -- not used
56
 
57
        resacx  : out std_logic                                                 -- ACEX reset line
58
 
59
);
60
end confppa ;
61
 
62
architecture rtl of confppa is
63
 
64
        signal slowclk          : std_logic;
65
        signal div                      : std_logic_vector(6 downto 0);
66
 
67
        signal state            : std_logic_vector(4 downto 0);
68
 
69
        signal ar                       : std_logic_vector(16 downto 0); -- adress register
70
 
71
-- 
72
--      special encoding to use as output!
73
--
74
constant start                  :std_logic_vector(4 downto 0) := "00110";
75
constant wait_nCfg_2us  :std_logic_vector(4 downto 0) := "10110";
76
constant wait_5us               :std_logic_vector(4 downto 0) := "01111";
77
constant wslow                  :std_logic_vector(4 downto 0) := "01101";
78
constant wshigh                 :std_logic_vector(4 downto 0) := "11111";
79
constant resacex                :std_logic_vector(4 downto 0) := "00111";
80
constant running                :std_logic_vector(4 downto 0) := "00011";
81
 
82
begin
83
 
84
--
85
--      divide clock to max 250 kHz (4us for nstatus)
86
--
87
process(clk, nreset)
88
begin
89
 
90
        if nreset='0' then
91
                div <= (others => '0');
92
        else
93
                if rising_edge(clk) then
94
                        div <= div + 1;
95
                end if;
96
        end if;
97
end process;
98
 
99
--      slowclk <= div(6);              for 24 MHz
100
        slowclk <= div(4);              -- for 7.3 MHz
101
 
102
        nconf <= state(0);
103
        nws <= state(1);
104
        resacx <= state(2);
105
        csacx <= state(3);
106
 
107
 
108
--
109
--      state machine
110
--
111
process(slowclk, nreset)
112
 
113
begin
114
 
115
        if nreset='0' then
116
 
117
                state <= start;
118
                ar <= (others => '0');
119
 
120
        else
121
                if rising_edge(slowclk) then
122
 
123
                        case state is
124
 
125
                                when start =>
126
                                        ar <= (others => '0');
127
                                        state <= wait_nCfg_2us;
128
 
129
                                when wait_nCfg_2us =>
130
                                        state <= wait_5us;
131
 
132
                                when wait_5us =>
133
                                        state <= wslow;
134
 
135
                                when wslow =>
136
                                        state <= wshigh;
137
 
138
                                when wshigh =>
139
                                        ar <= ar + 1;
140
                                        if conf_done='1' then
141
                                                state <= resacex;
142
                                        else
143
                                                state <= wslow;
144
                                        end if;
145
 
146
                                when resacex =>
147
                                        state <= running;
148
 
149
                                when running =>
150
 
151
                                when others =>
152
 
153
                        end case;
154
                end if;
155
        end if;
156
 
157
end process;
158
 
159
process (state(2), ar, d0in, noe_in, nce_in)
160
begin
161
 
162
        if state(2)='0' then             -- is resacx
163
                a <= (others => 'Z');
164
                d0out <= '1';
165
                noe <= noe_in;
166
                nce <= nce_in;
167
        else
168
                a <= ar;
169
                d0out <= d0in;
170
                noe <= '0';
171
                nce <= '0';
172
        end if;
173
 
174
end process;
175
 
176
 
177
end rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.