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[/] [adaptive_lms_equalizer/] [tags/] [V10/] [code/] [core_filt.vhd] - Blame information for rev 2

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1 2 digish 
--  Copyright (C) 2004-2005 Digish Pandya <digish.pandya@gmail.com>
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--  This program is free software; you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation; either version 2 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program; if not, write to the Free Software
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--  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
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-- A.7
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-- Filter core for adaptive equalizer
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-- Five tap filter
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-- structuaral description
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity core_filt is
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    Port (
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                 x_in : in std_logic_vector(7 downto 0);
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           x_N_in : in std_logic_vector(7 downto 0);
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           ue_in : in std_logic_vector(7 downto 0);
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           clock : in std_logic;
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           y_out : out std_logic_vector(7 downto 0));
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end core_filt;
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architecture pm_chain of core_filt is
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                -- basic tap processing element
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                component unit_calc
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             Port ( x_in : in std_logic_vector(7 downto 0);
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                   x_N_in : in std_logic_vector(7 downto 0);
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                   ue_in : in std_logic_vector(7 downto 0);
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                   y_in : in std_logic_vector(7 downto 0);
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                   x_out : out std_logic_vector(7 downto 0);
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                   x_N_out : out std_logic_vector(7 downto 0);
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                   ue_out : out std_logic_vector(7 downto 0);
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                         y_out: out std_logic_vector(7 downto 0);
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                   clock : in std_logic);
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                end component ;
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        signal x_out_t1  :std_logic_vector(7 downto 0);
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        signal x_out_t2  :std_logic_vector(7 downto 0);
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        signal x_out_t3  :std_logic_vector(7 downto 0);
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        signal x_out_t4  :std_logic_vector(7 downto 0);
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        signal x_N_out_t1  :std_logic_vector(7 downto 0);
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        signal x_N_out_t2  :std_logic_vector(7 downto 0);
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        signal x_N_out_t3  :std_logic_vector(7 downto 0);
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        signal x_N_out_t4  :std_logic_vector(7 downto 0);
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        signal ue_out_t1  :std_logic_vector(7 downto 0);
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        signal ue_out_t2  :std_logic_vector(7 downto 0);
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        signal ue_out_t3  :std_logic_vector(7 downto 0);
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        signal ue_out_t4  :std_logic_vector(7 downto 0);
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        signal y_out_t1  :std_logic_vector(7 downto 0);
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        signal y_out_t2  :std_logic_vector(7 downto 0);
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        signal y_out_t3  :std_logic_vector(7 downto 0);
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        signal y_out_t4  :std_logic_vector(7 downto 0);
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begin
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   tap1: unit_calc
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   port map (
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                      x_in      => x_in,
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                 x_N_in         => x_N_in,
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                         ue_in          => ue_in,
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                         y_in   => "00000000",
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                         x_out  => x_out_t1,
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                         x_N_out        => x_N_out_t1,
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                         ue_out         => ue_out_t1,
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                         y_out  => y_out_t1,
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                         clock  => clock
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           );
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   tap2: unit_calc
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   port map (
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                      x_in      => x_out_t1,
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                 x_N_in         => x_N_out_t1,
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                         ue_in          => ue_out_t1,
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                         y_in   => y_out_t1,
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                         x_out  => x_out_t2,
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                         x_N_out        => x_N_out_t2,
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                         ue_out         => ue_out_t2,
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                         y_out  => y_out_t2,
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                         clock  => clock
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           );
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   tap3: unit_calc
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   port map (
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                      x_in      => x_out_t2,
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                 x_N_in         => x_N_out_t2,
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                         ue_in          => ue_out_t2,
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                         y_in   => y_out_t2,
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                         x_out  => x_out_t3,
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                         x_N_out        => x_N_out_t3,
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                         ue_out         => ue_out_t3,
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                         y_out  => y_out_t3,
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                         clock  => clock
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           );
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   tap4: unit_calc
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   port map (
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                      x_in      => x_out_t3,
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                 x_N_in         => x_N_out_t3,
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                         ue_in          => ue_out_t3,
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                         y_in   => y_out_t3,
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                         x_out  => x_out_t4,
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                         x_N_out        => x_N_out_t4,
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                         ue_out         => ue_out_t4,
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                         y_out  => y_out_t4,
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                         clock  => clock
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         );
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   tap5: unit_calc
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   port map (
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                      x_in      => x_out_t4,
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                 x_N_in         => x_N_out_t4,
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                         ue_in          => ue_out_t4,
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                         y_in   => y_out_t4,
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                         x_out  => open,
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                         x_N_out        => open,
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                         ue_out         => open,
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                         y_out  => y_out,
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                         clock  => clock
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           );
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end pm_chain;

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