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[/] [adaptive_lms_equalizer/] [trunk/] [code/] [data_gen_translate.vhd] - Blame information for rev 4

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1 2 digish 
-- Xilinx Vhdl produced by program ngd2vhdl F.28
2 
-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log data_gen.ngd data_gen_translate.vhd
3 
-- Input file: data_gen.ngd
4 
-- Output file: data_gen_translate.vhd
5 
-- Design name: data_gen
6 
-- Xilinx: E:/xilinx
7 
-- # of Entities: 1
8 
-- Device: 2s100tq144-6
9 
 
10 
-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
11 
-- or used in any other manner other than simulation. This netlist uses simulation
12 
-- primitives which may not represent the true implementation of the device, however
13 
-- the netlist is functionally correct. Do not modify this file.
14 
 
15 
-- Model for  ROC (Reset-On-Configuration) Cell
16 
library IEEE;
17 
use IEEE.std_logic_1164.all;
18 
use IEEE.VITAL_Timing.all;
19 
entity ROC is
20 
  generic (InstancePath: STRING := "*";
21 
           WIDTH : Time := 100 ns);
22 
  port(O : out std_ulogic := '1') ;
23 
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
24 
end ROC;
25 
 
26 
architecture ROC_V of ROC is
27 
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
28 
begin
29 
  ONE_SHOT : process
30 
  begin
31 
    if (WIDTH <= 0 ns) then
32 
       assert FALSE report
33 
       "*** Error: a positive value of WIDTH must be specified ***"
34 
       severity failure;
35 
    else
36 
       wait for WIDTH;
37 
       O <= '0';
38 
    end if;
39 
    wait;
40 
  end process ONE_SHOT;
41 
end ROC_V;
42 
 
43 
-- Model for  TOC (Tristate-On-Configuration) Cell
44 
library IEEE;
45 
use IEEE.std_logic_1164.all;
46 
use IEEE.VITAL_Timing.all;
47 
entity TOC is
48 
  generic (InstancePath: STRING := "*";
49 
           WIDTH : Time := 0 ns);
50 
  port(O : out std_ulogic := '0');
51 
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
52 
end TOC;
53 
 
54 
architecture TOC_V of TOC is
55 
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
56 
begin
57 
  ONE_SHOT : process
58 
  begin
59 
    O <= '1';
60 
    if (WIDTH <= 0 ns) then
61 
       O <= '0';
62 
    else
63 
       wait for WIDTH;
64 
       O <= '0';
65 
    end if;
66 
    wait;
67 
  end process ONE_SHOT;
68 
end TOC_V;
69 
 
70 
library IEEE;
71 
use IEEE.STD_LOGIC_1164.ALL;
72 
library SIMPRIM;
73 
use SIMPRIM.VCOMPONENTS.ALL;
74 
use SIMPRIM.VPACKAGE.ALL;
75 
entity data_gen is
76 
  port (
77 
    reset : in STD_LOGIC := 'X';
78 
    clock : in STD_LOGIC := 'X';
79 
    dxout : out STD_LOGIC_VECTOR ( 7 downto 0 );
80 
    xout : out STD_LOGIC_VECTOR ( 7 downto 0 )
81 
  );
82 
end data_gen;
83 
 
84 
architecture Structure of data_gen is
85 
  component ROC
86 
    generic (InstancePath: STRING := "*";
87 
             WIDTH : Time := 100 ns);
88 
    port (O : out STD_ULOGIC := '1');
89 
  end component;
90 
  component TOC
91 
    generic (InstancePath: STRING := "*";
92 
             WIDTH : Time := 0 ns);
93 
    port (O : out STD_ULOGIC := '1');
94 
  end component;
95 
  signal data_0_Q : STD_LOGIC;
96 
  signal reset_ibuf : STD_LOGIC;
97 
  signal clock_bufgp : STD_LOGIC;
98 
  signal Q_n0003 : STD_LOGIC;
99 
  signal xout_1_obuf : STD_LOGIC;
100 
  signal n2175 : STD_LOGIC;
101 
  signal channel_tap2_madd_add_out_inst_lut2_5 : STD_LOGIC;
102 
  signal xout_2_obuf : STD_LOGIC;
103 
  signal channel_tap2_madd_add_out_inst_lut2_4 : STD_LOGIC;
104 
  signal data_7_Q : STD_LOGIC;
105 
  signal channel_tap2_madd_add_out_inst_cy_3 : STD_LOGIC;
106 
  signal channel_tap3_madd_add_out_inst_lut2_3 : STD_LOGIC;
107 
  signal channel_tap1_madd_add_out_inst_cy_6 : STD_LOGIC;
108 
  signal channel_tap2_madd_add_out_inst_cy_5 : STD_LOGIC;
109 
  signal xout_7_obuf : STD_LOGIC;
110 
  signal xout_6_obuf : STD_LOGIC;
111 
  signal xout_5_obuf : STD_LOGIC;
112 
  signal xout_4_obuf : STD_LOGIC;
113 
  signal xout_3_obuf : STD_LOGIC;
114 
  signal channel_tap2_madd_add_out_inst_lut2_3 : STD_LOGIC;
115 
  signal channel_tap3_madd_add_out_inst_cy_1 : STD_LOGIC;
116 
  signal channel_tap2_madd_add_out_inst_lut2_6 : STD_LOGIC;
117 
  signal channel_tap3_madd_add_out_inst_lut2_7 : STD_LOGIC;
118 
  signal channel_tap2_madd_add_out_inst_cy_6 : STD_LOGIC;
119 
  signal channel_tap2_madd_add_out_inst_cy_1 : STD_LOGIC;
120 
  signal channel_tap3_madd_add_out_inst_cy_4 : STD_LOGIC;
121 
  signal channel_tap3_madd_add_out_inst_cy_3 : STD_LOGIC;
122 
  signal channel_tap2_madd_add_out_inst_lut2_1 : STD_LOGIC;
123 
  signal channel_tap3_madd_add_out_inst_lut2_5 : STD_LOGIC;
124 
  signal channel_tap3_madd_add_out_inst_lut2_2 : STD_LOGIC;
125 
  signal channel_tap2_madd_add_out_inst_lut2_2 : STD_LOGIC;
126 
  signal channel_tap3_madd_add_out_inst_lut2_1 : STD_LOGIC;
127 
  signal channel_tap2_madd_add_out_inst_cy_2 : STD_LOGIC;
128 
  signal channel_tap3_madd_add_out_inst_cy_2 : STD_LOGIC;
129 
  signal channel_tap3_madd_add_out_inst_lut2_6 : STD_LOGIC;
130 
  signal channel_tap3_madd_add_out_inst_cy_5 : STD_LOGIC;
131 
  signal channel_tap3_madd_add_out_inst_cy_6 : STD_LOGIC;
132 
  signal channel_tap2_madd_add_out_inst_cy_4 : STD_LOGIC;
133 
  signal channel_tap3_madd_add_out_inst_lut2_4 : STD_LOGIC;
134 
  signal Q_n0003_O : STD_LOGIC;
135 
  signal clock_bufgp_IBUFG : STD_LOGIC;
136 
  signal GSR : STD_LOGIC;
137 
  signal dxout_7_obuf_GTS_TRI : STD_LOGIC;
138 
  signal GTS : STD_LOGIC;
139 
  signal dxout_6_obuf_GTS_TRI : STD_LOGIC;
140 
  signal dxout_5_obuf_GTS_TRI : STD_LOGIC;
141 
  signal dxout_4_obuf_GTS_TRI : STD_LOGIC;
142 
  signal dxout_3_obuf_GTS_TRI : STD_LOGIC;
143 
  signal dxout_2_obuf_GTS_TRI : STD_LOGIC;
144 
  signal dxout_1_obuf_GTS_TRI : STD_LOGIC;
145 
  signal dxout_0_obuf_GTS_TRI : STD_LOGIC;
146 
  signal xout_7_obuf_GTS_TRI : STD_LOGIC;
147 
  signal xout_6_obuf_GTS_TRI : STD_LOGIC;
148 
  signal xout_5_obuf_GTS_TRI : STD_LOGIC;
149 
  signal xout_4_obuf_GTS_TRI : STD_LOGIC;
150 
  signal xout_3_obuf_GTS_TRI : STD_LOGIC;
151 
  signal xout_2_obuf_GTS_TRI : STD_LOGIC;
152 
  signal xout_1_obuf_GTS_TRI : STD_LOGIC;
153 
  signal xout_0_obuf_GTS_TRI : STD_LOGIC;
154 
  signal VCC : STD_LOGIC;
155 
  signal GND : STD_LOGIC;
156 
  signal NlwInverterSignal_dxout_7_obuf_GTS_TRI_CTL : STD_LOGIC;
157 
  signal NlwInverterSignal_dxout_6_obuf_GTS_TRI_CTL : STD_LOGIC;
158 
  signal NlwInverterSignal_dxout_5_obuf_GTS_TRI_CTL : STD_LOGIC;
159 
  signal NlwInverterSignal_dxout_4_obuf_GTS_TRI_CTL : STD_LOGIC;
160 
  signal NlwInverterSignal_dxout_3_obuf_GTS_TRI_CTL : STD_LOGIC;
161 
  signal NlwInverterSignal_dxout_2_obuf_GTS_TRI_CTL : STD_LOGIC;
162 
  signal NlwInverterSignal_dxout_1_obuf_GTS_TRI_CTL : STD_LOGIC;
163 
  signal NlwInverterSignal_dxout_0_obuf_GTS_TRI_CTL : STD_LOGIC;
164 
  signal NlwInverterSignal_xout_7_obuf_GTS_TRI_CTL : STD_LOGIC;
165 
  signal NlwInverterSignal_xout_6_obuf_GTS_TRI_CTL : STD_LOGIC;
166 
  signal NlwInverterSignal_xout_5_obuf_GTS_TRI_CTL : STD_LOGIC;
167 
  signal NlwInverterSignal_xout_4_obuf_GTS_TRI_CTL : STD_LOGIC;
168 
  signal NlwInverterSignal_xout_3_obuf_GTS_TRI_CTL : STD_LOGIC;
169 
  signal NlwInverterSignal_xout_2_obuf_GTS_TRI_CTL : STD_LOGIC;
170 
  signal NlwInverterSignal_xout_1_obuf_GTS_TRI_CTL : STD_LOGIC;
171 
  signal NlwInverterSignal_xout_0_obuf_GTS_TRI_CTL : STD_LOGIC;
172 
  signal channel_tap3_dout : STD_LOGIC_VECTOR ( 7 downto 7 );
173 
  signal channel_tap1_dout : STD_LOGIC_VECTOR ( 7 downto 7 );
174 
  signal channel_t_res_out2 : STD_LOGIC_VECTOR ( 7 downto 2 );
175 
  signal channel_tap2_mul_res : STD_LOGIC_VECTOR ( 2 downto 2 );
176 
  signal channel_tap3_mul_res : STD_LOGIC_VECTOR ( 5 downto 5 );
177 
  signal channel_tap2_dout : STD_LOGIC_VECTOR ( 7 downto 7 );
178 
begin
179 
  channel_tap2_madd_add_out_inst_lut2_511 : X_LUT2
180 
    generic map(
181 
      INIT => X"6"
182 
    )
183 
    port map (
184 
      ADR0 => channel_tap2_mul_res(2),
185 
      ADR1 => data_7_Q,
186 
      O => n2175
187 
    );
188 
  channel_tap3_madd_add_out_inst_sum_1 : X_XOR2
189 
    port map (
190 
      I0 => data_0_Q,
191 
      I1 => channel_tap3_madd_add_out_inst_lut2_1,
192 
      O => xout_1_obuf
193 
    );
194 
  channel_tap2_madd_add_out_inst_lut2_41 : X_LUT2
195 
    generic map(
196 
      INIT => X"6"
197 
    )
198 
    port map (
199 
      ADR0 => channel_tap1_dout(7),
200 
      ADR1 => data_7_Q,
201 
      O => channel_tap2_madd_add_out_inst_lut2_4
202 
    );
203 
  channel_tap3_madd_add_out_inst_sum_6 : X_XOR2
204 
    port map (
205 
      I0 => channel_tap3_madd_add_out_inst_cy_5,
206 
      I1 => channel_tap3_madd_add_out_inst_lut2_6,
207 
      O => xout_6_obuf
208 
    );
209 
  data_7 : X_SFF
210 
    port map (
211 
      I => Q_n0003,
212 
      SRST => reset_ibuf,
213 
      CLK => clock_bufgp,
214 
      O => data_7_Q,
215 
      CE => VCC,
216 
      SET => GND,
217 
      RST => GSR,
218 
      SSET => GND
219 
    );
220 
  xout_0_obuf : X_BUF
221 
    port map (
222 
      I => channel_tap1_madd_add_out_inst_cy_6,
223 
      O => xout_0_obuf_GTS_TRI
224 
    );
225 
  channel_tap2_madd_add_out_inst_sum_6 : X_XOR2
226 
    port map (
227 
      I0 => channel_tap2_madd_add_out_inst_cy_5,
228 
      I1 => channel_tap2_madd_add_out_inst_lut2_6,
229 
      O => channel_t_res_out2(6)
230 
    );
231 
  dxout_0_obuf : X_BUF
232 
    port map (
233 
      I => data_0_Q,
234 
      O => dxout_0_obuf_GTS_TRI
235 
    );
236 
  channel_tap3_madd_add_out_inst_lut2_21 : X_LUT2
237 
    generic map(
238 
      INIT => X"6"
239 
    )
240 
    port map (
241 
      ADR0 => channel_t_res_out2(2),
242 
      ADR1 => channel_tap2_dout(7),
243 
      O => channel_tap3_madd_add_out_inst_lut2_2
244 
    );
245 
  channel_tap2_madd_add_out_inst_cy_1_0 : X_MUX2
246 
    port map (
247 
      IA => data_0_Q,
248 
      IB => channel_tap1_madd_add_out_inst_cy_6,
249 
      SEL => channel_tap2_madd_add_out_inst_lut2_1,
250 
      O => channel_tap2_madd_add_out_inst_cy_1
251 
    );
252 
  channel_tap2_madd_add_out_inst_lut2_111 : X_LUT2
253 
    generic map(
254 
      INIT => X"5"
255 
    )
256 
    port map (
257 
      ADR0 => data_7_Q,
258 
      O => channel_tap2_madd_add_out_inst_lut2_1,
259 
      ADR1 => GND
260 
    );
261 
  xst_vcc : X_ONE
262 
    port map (
263 
      O => data_0_Q
264 
    );
265 
  xst_gnd : X_ZERO
266 
    port map (
267 
      O => channel_tap1_madd_add_out_inst_cy_6
268 
    );
269 
  channel_tap3_madd_add_out_inst_cy_6_1 : X_MUX2
270 
    port map (
271 
      IA => channel_t_res_out2(6),
272 
      IB => channel_tap3_madd_add_out_inst_cy_5,
273 
      SEL => channel_tap3_madd_add_out_inst_lut2_6,
274 
      O => channel_tap3_madd_add_out_inst_cy_6
275 
    );
276 
  channel_tap2_madd_add_out_inst_cy_6_2 : X_MUX2
277 
    port map (
278 
      IA => channel_tap2_mul_res(2),
279 
      IB => channel_tap2_madd_add_out_inst_cy_5,
280 
      SEL => channel_tap2_madd_add_out_inst_lut2_6,
281 
      O => channel_tap2_madd_add_out_inst_cy_6
282 
    );
283 
  channel_tap3_madd_add_out_inst_lut2_61 : X_LUT2
284 
    generic map(
285 
      INIT => X"6"
286 
    )
287 
    port map (
288 
      ADR0 => channel_t_res_out2(6),
289 
      ADR1 => channel_tap2_dout(7),
290 
      O => channel_tap3_madd_add_out_inst_lut2_6
291 
    );
292 
  channel_tap2_madd_add_out_inst_lut2_31 : X_LUT2
293 
    generic map(
294 
      INIT => X"9"
295 
    )
296 
    port map (
297 
      ADR0 => channel_tap1_dout(7),
298 
      ADR1 => data_7_Q,
299 
      O => channel_tap2_madd_add_out_inst_lut2_3
300 
    );
301 
  channel_tap3_madd_add_out_inst_lut2_71 : X_LUT2
302 
    generic map(
303 
      INIT => X"6"
304 
    )
305 
    port map (
306 
      ADR0 => channel_tap2_dout(7),
307 
      ADR1 => channel_t_res_out2(7),
308 
      O => channel_tap3_madd_add_out_inst_lut2_7
309 
    );
310 
  channel_tap3_madd_add_out_inst_sum_5 : X_XOR2
311 
    port map (
312 
      I0 => channel_tap3_madd_add_out_inst_cy_4,
313 
      I1 => channel_tap3_madd_add_out_inst_lut2_5,
314 
      O => xout_5_obuf
315 
    );
316 
  channel_tap3_dout_7 : X_FF
317 
    port map (
318 
      I => channel_tap2_dout(7),
319 
      CLK => clock_bufgp,
320 
      O => channel_tap3_dout(7),
321 
      CE => VCC,
322 
      SET => GND,
323 
      RST => GSR
324 
    );
325 
  channel_tap2_madd_add_out_inst_cy_5_3 : X_MUX2
326 
    port map (
327 
      IA => channel_tap2_mul_res(2),
328 
      IB => channel_tap2_madd_add_out_inst_cy_4,
329 
      SEL => n2175,
330 
      O => channel_tap2_madd_add_out_inst_cy_5
331 
    );
332 
  dxout_5_obuf : X_BUF
333 
    port map (
334 
      I => channel_tap3_dout(7),
335 
      O => dxout_5_obuf_GTS_TRI
336 
    );
337 
  xout_7_obuf_4 : X_BUF
338 
    port map (
339 
      I => xout_7_obuf,
340 
      O => xout_7_obuf_GTS_TRI
341 
    );
342 
  xout_1_obuf_5 : X_BUF
343 
    port map (
344 
      I => xout_1_obuf,
345 
      O => xout_1_obuf_GTS_TRI
346 
    );
347 
  dxout_4_obuf : X_BUF
348 
    port map (
349 
      I => channel_tap3_dout(7),
350 
      O => dxout_4_obuf_GTS_TRI
351 
    );
352 
  reset_ibuf_6 : X_BUF
353 
    port map (
354 
      I => reset,
355 
      O => reset_ibuf
356 
    );
357 
  xout_5_obuf_7 : X_BUF
358 
    port map (
359 
      I => xout_5_obuf,
360 
      O => xout_5_obuf_GTS_TRI
361 
    );
362 
  channel_tap2_madd_add_out_inst_lut2_51 : X_LUT2
363 
    generic map(
364 
      INIT => X"6"
365 
    )
366 
    port map (
367 
      ADR0 => channel_tap2_mul_res(2),
368 
      ADR1 => data_7_Q,
369 
      O => channel_tap2_madd_add_out_inst_lut2_5
370 
    );
371 
  channel_tap3_madd_add_out_inst_cy_5_8 : X_MUX2
372 
    port map (
373 
      IA => channel_t_res_out2(5),
374 
      IB => channel_tap3_madd_add_out_inst_cy_4,
375 
      SEL => channel_tap3_madd_add_out_inst_lut2_5,
376 
      O => channel_tap3_madd_add_out_inst_cy_5
377 
    );
378 
  channel_tap3_madd_add_out_inst_lut2_41 : X_LUT2
379 
    generic map(
380 
      INIT => X"9"
381 
    )
382 
    port map (
383 
      ADR0 => channel_t_res_out2(4),
384 
      ADR1 => channel_tap2_dout(7),
385 
      O => channel_tap3_madd_add_out_inst_lut2_4
386 
    );
387 
  channel_tap3_madd_add_out_inst_cy_1_9 : X_MUX2
388 
    port map (
389 
      IA => channel_tap3_mul_res(5),
390 
      IB => data_0_Q,
391 
      SEL => channel_tap3_madd_add_out_inst_lut2_1,
392 
      O => channel_tap3_madd_add_out_inst_cy_1
393 
    );
394 
  channel_tap3_mmux_mul_res_i2_result1 : X_LUT2
395 
    generic map(
396 
      INIT => X"5"
397 
    )
398 
    port map (
399 
      ADR0 => channel_tap2_dout(7),
400 
      O => channel_tap3_mul_res(5),
401 
      ADR1 => GND
402 
    );
403 
  channel_tap2_madd_add_out_inst_sum_4 : X_XOR2
404 
    port map (
405 
      I0 => channel_tap2_madd_add_out_inst_cy_3,
406 
      I1 => channel_tap2_madd_add_out_inst_lut2_4,
407 
      O => channel_t_res_out2(4)
408 
    );
409 
  channel_tap2_madd_add_out_inst_cy_2_10 : X_MUX2
410 
    port map (
411 
      IA => channel_tap2_mul_res(2),
412 
      IB => channel_tap2_madd_add_out_inst_cy_1,
413 
      SEL => channel_tap2_madd_add_out_inst_lut2_2,
414 
      O => channel_tap2_madd_add_out_inst_cy_2
415 
    );
416 
  channel_tap2_madd_add_out_inst_cy_3_11 : X_MUX2
417 
    port map (
418 
      IA => channel_tap1_dout(7),
419 
      IB => channel_tap2_madd_add_out_inst_cy_2,
420 
      SEL => channel_tap2_madd_add_out_inst_lut2_3,
421 
      O => channel_tap2_madd_add_out_inst_cy_3
422 
    );
423 
  channel_tap2_dout_7 : X_FF
424 
    port map (
425 
      I => channel_tap1_dout(7),
426 
      CLK => clock_bufgp,
427 
      O => channel_tap2_dout(7),
428 
      CE => VCC,
429 
      SET => GND,
430 
      RST => GSR
431 
    );
432 
  channel_tap2_madd_add_out_inst_sum_5 : X_XOR2
433 
    port map (
434 
      I0 => channel_tap2_madd_add_out_inst_cy_4,
435 
      I1 => n2175,
436 
      O => channel_t_res_out2(5)
437 
    );
438 
  dxout_6_obuf : X_BUF
439 
    port map (
440 
      I => channel_tap3_dout(7),
441 
      O => dxout_6_obuf_GTS_TRI
442 
    );
443 
  dxout_3_obuf : X_BUF
444 
    port map (
445 
      I => channel_tap3_dout(7),
446 
      O => dxout_3_obuf_GTS_TRI
447 
    );
448 
  dxout_2_obuf : X_BUF
449 
    port map (
450 
      I => channel_tap3_dout(7),
451 
      O => dxout_2_obuf_GTS_TRI
452 
    );
453 
  xout_3_obuf_12 : X_BUF
454 
    port map (
455 
      I => xout_3_obuf,
456 
      O => xout_3_obuf_GTS_TRI
457 
    );
458 
  channel_tap3_madd_add_out_inst_sum_2 : X_XOR2
459 
    port map (
460 
      I0 => channel_tap3_madd_add_out_inst_cy_1,
461 
      I1 => channel_tap3_madd_add_out_inst_lut2_2,
462 
      O => xout_2_obuf
463 
    );
464 
  channel_tap3_madd_add_out_inst_cy_2_13 : X_MUX2
465 
    port map (
466 
      IA => channel_t_res_out2(2),
467 
      IB => channel_tap3_madd_add_out_inst_cy_1,
468 
      SEL => channel_tap3_madd_add_out_inst_lut2_2,
469 
      O => channel_tap3_madd_add_out_inst_cy_2
470 
    );
471 
  channel_tap3_madd_add_out_inst_sum_4 : X_XOR2
472 
    port map (
473 
      I0 => channel_tap3_madd_add_out_inst_cy_3,
474 
      I1 => channel_tap3_madd_add_out_inst_lut2_4,
475 
      O => xout_4_obuf
476 
    );
477 
  channel_tap2_madd_add_out_inst_lut2_21 : X_LUT2
478 
    generic map(
479 
      INIT => X"9"
480 
    )
481 
    port map (
482 
      ADR0 => channel_tap2_mul_res(2),
483 
      ADR1 => data_7_Q,
484 
      O => channel_tap2_madd_add_out_inst_lut2_2
485 
    );
486 
  channel_tap2_mmux_mul_res_i5_result1 : X_LUT2
487 
    generic map(
488 
      INIT => X"5"
489 
    )
490 
    port map (
491 
      ADR0 => channel_tap1_dout(7),
492 
      O => channel_tap2_mul_res(2),
493 
      ADR1 => GND
494 
    );
495 
  channel_tap3_madd_add_out_inst_cy_4_14 : X_MUX2
496 
    port map (
497 
      IA => channel_t_res_out2(4),
498 
      IB => channel_tap3_madd_add_out_inst_cy_3,
499 
      SEL => channel_tap3_madd_add_out_inst_lut2_4,
500 
      O => channel_tap3_madd_add_out_inst_cy_4
501 
    );
502 
  channel_tap3_madd_add_out_inst_lut2_31 : X_LUT2
503 
    generic map(
504 
      INIT => X"6"
505 
    )
506 
    port map (
507 
      ADR0 => channel_t_res_out2(3),
508 
      ADR1 => channel_tap2_dout(7),
509 
      O => channel_tap3_madd_add_out_inst_lut2_3
510 
    );
511 
  channel_tap2_madd_add_out_inst_sum_3 : X_XOR2
512 
    port map (
513 
      I0 => channel_tap2_madd_add_out_inst_cy_2,
514 
      I1 => channel_tap2_madd_add_out_inst_lut2_3,
515 
      O => channel_t_res_out2(3)
516 
    );
517 
  channel_tap3_madd_add_out_inst_lut2_51 : X_LUT2
518 
    generic map(
519 
      INIT => X"9"
520 
    )
521 
    port map (
522 
      ADR0 => channel_t_res_out2(5),
523 
      ADR1 => channel_tap2_dout(7),
524 
      O => channel_tap3_madd_add_out_inst_lut2_5
525 
    );
526 
  xout_6_obuf_15 : X_BUF
527 
    port map (
528 
      I => xout_6_obuf,
529 
      O => xout_6_obuf_GTS_TRI
530 
    );
531 
  channel_tap3_madd_add_out_inst_sum_3 : X_XOR2
532 
    port map (
533 
      I0 => channel_tap3_madd_add_out_inst_cy_2,
534 
      I1 => channel_tap3_madd_add_out_inst_lut2_3,
535 
      O => xout_3_obuf
536 
    );
537 
  channel_tap1_dout_7 : X_FF
538 
    port map (
539 
      I => data_7_Q,
540 
      CLK => clock_bufgp,
541 
      O => channel_tap1_dout(7),
542 
      CE => VCC,
543 
      SET => GND,
544 
      RST => GSR
545 
    );
546 
  channel_tap2_madd_add_out_inst_lut2_61 : X_LUT2
547 
    generic map(
548 
      INIT => X"6"
549 
    )
550 
    port map (
551 
      ADR0 => channel_tap2_mul_res(2),
552 
      ADR1 => data_7_Q,
553 
      O => channel_tap2_madd_add_out_inst_lut2_6
554 
    );
555 
  dxout_7_obuf : X_BUF
556 
    port map (
557 
      I => channel_tap3_dout(7),
558 
      O => dxout_7_obuf_GTS_TRI
559 
    );
560 
  xout_2_obuf_16 : X_BUF
561 
    port map (
562 
      I => xout_2_obuf,
563 
      O => xout_2_obuf_GTS_TRI
564 
    );
565 
  xout_4_obuf_17 : X_BUF
566 
    port map (
567 
      I => xout_4_obuf,
568 
      O => xout_4_obuf_GTS_TRI
569 
    );
570 
  channel_tap2_madd_add_out_inst_sum_7 : X_XOR2
571 
    port map (
572 
      I0 => channel_tap2_madd_add_out_inst_cy_6,
573 
      I1 => channel_tap2_madd_add_out_inst_lut2_5,
574 
      O => channel_t_res_out2(7)
575 
    );
576 
  channel_tap2_madd_add_out_inst_cy_4_18 : X_MUX2
577 
    port map (
578 
      IA => channel_tap1_dout(7),
579 
      IB => channel_tap2_madd_add_out_inst_cy_3,
580 
      SEL => channel_tap2_madd_add_out_inst_lut2_4,
581 
      O => channel_tap2_madd_add_out_inst_cy_4
582 
    );
583 
  channel_tap2_madd_add_out_inst_sum_2 : X_XOR2
584 
    port map (
585 
      I0 => channel_tap2_madd_add_out_inst_cy_1,
586 
      I1 => channel_tap2_madd_add_out_inst_lut2_2,
587 
      O => channel_t_res_out2(2)
588 
    );
589 
  channel_tap3_madd_add_out_inst_cy_3_19 : X_MUX2
590 
    port map (
591 
      IA => channel_t_res_out2(3),
592 
      IB => channel_tap3_madd_add_out_inst_cy_2,
593 
      SEL => channel_tap3_madd_add_out_inst_lut2_3,
594 
      O => channel_tap3_madd_add_out_inst_cy_3
595 
    );
596 
  dxout_1_obuf : X_BUF
597 
    port map (
598 
      I => channel_tap3_dout(7),
599 
      O => dxout_1_obuf_GTS_TRI
600 
    );
601 
  channel_tap3_madd_add_out_inst_sum_7 : X_XOR2
602 
    port map (
603 
      I0 => channel_tap3_madd_add_out_inst_cy_6,
604 
      I1 => channel_tap3_madd_add_out_inst_lut2_7,
605 
      O => xout_7_obuf
606 
    );
607 
  channel_tap3_madd_add_out_inst_lut2_11 : X_LUT2
608 
    generic map(
609 
      INIT => X"6"
610 
    )
611 
    port map (
612 
      ADR0 => channel_tap2_dout(7),
613 
      ADR1 => data_7_Q,
614 
      O => channel_tap3_madd_add_out_inst_lut2_1
615 
    );
616 
  Q_n0003_22 : X_LUT2
617 
    generic map(
618 
      INIT => X"5"
619 
    )
620 
    port map (
621 
      ADR0 => data_7_Q,
622 
      ADR1 => GND,
623 
      O => Q_n0003_O
624 
    );
625 
  Q_n0003_LUT1_L_BUF : X_BUF
626 
    port map (
627 
      I => Q_n0003_O,
628 
      O => Q_n0003
629 
    );
630 
  clock_bufgp_IBUFG_23 : X_CKBUF
631 
    port map (
632 
      I => clock,
633 
      O => clock_bufgp_IBUFG
634 
    );
635 
  clock_bufgp_BUFG : X_CKBUF
636 
    port map (
637 
      I => clock_bufgp_IBUFG,
638 
      O => clock_bufgp
639 
    );
640 
  dxout_7_obuf_GTS_TRI_24 : X_TRI
641 
    port map (
642 
      I => dxout_7_obuf_GTS_TRI,
643 
      CTL => NlwInverterSignal_dxout_7_obuf_GTS_TRI_CTL,
644 
      O => dxout(7)
645 
    );
646 
  dxout_6_obuf_GTS_TRI_25 : X_TRI
647 
    port map (
648 
      I => dxout_6_obuf_GTS_TRI,
649 
      CTL => NlwInverterSignal_dxout_6_obuf_GTS_TRI_CTL,
650 
      O => dxout(6)
651 
    );
652 
  dxout_5_obuf_GTS_TRI_26 : X_TRI
653 
    port map (
654 
      I => dxout_5_obuf_GTS_TRI,
655 
      CTL => NlwInverterSignal_dxout_5_obuf_GTS_TRI_CTL,
656 
      O => dxout(5)
657 
    );
658 
  dxout_4_obuf_GTS_TRI_27 : X_TRI
659 
    port map (
660 
      I => dxout_4_obuf_GTS_TRI,
661 
      CTL => NlwInverterSignal_dxout_4_obuf_GTS_TRI_CTL,
662 
      O => dxout(4)
663 
    );
664 
  dxout_3_obuf_GTS_TRI_28 : X_TRI
665 
    port map (
666 
      I => dxout_3_obuf_GTS_TRI,
667 
      CTL => NlwInverterSignal_dxout_3_obuf_GTS_TRI_CTL,
668 
      O => dxout(3)
669 
    );
670 
  dxout_2_obuf_GTS_TRI_29 : X_TRI
671 
    port map (
672 
      I => dxout_2_obuf_GTS_TRI,
673 
      CTL => NlwInverterSignal_dxout_2_obuf_GTS_TRI_CTL,
674 
      O => dxout(2)
675 
    );
676 
  dxout_1_obuf_GTS_TRI_30 : X_TRI
677 
    port map (
678 
      I => dxout_1_obuf_GTS_TRI,
679 
      CTL => NlwInverterSignal_dxout_1_obuf_GTS_TRI_CTL,
680 
      O => dxout(1)
681 
    );
682 
  dxout_0_obuf_GTS_TRI_31 : X_TRI
683 
    port map (
684 
      I => dxout_0_obuf_GTS_TRI,
685 
      CTL => NlwInverterSignal_dxout_0_obuf_GTS_TRI_CTL,
686 
      O => dxout(0)
687 
    );
688 
  xout_7_obuf_GTS_TRI_32 : X_TRI
689 
    port map (
690 
      I => xout_7_obuf_GTS_TRI,
691 
      CTL => NlwInverterSignal_xout_7_obuf_GTS_TRI_CTL,
692 
      O => xout(7)
693 
    );
694 
  xout_6_obuf_GTS_TRI_33 : X_TRI
695 
    port map (
696 
      I => xout_6_obuf_GTS_TRI,
697 
      CTL => NlwInverterSignal_xout_6_obuf_GTS_TRI_CTL,
698 
      O => xout(6)
699 
    );
700 
  xout_5_obuf_GTS_TRI_34 : X_TRI
701 
    port map (
702 
      I => xout_5_obuf_GTS_TRI,
703 
      CTL => NlwInverterSignal_xout_5_obuf_GTS_TRI_CTL,
704 
      O => xout(5)
705 
    );
706 
  xout_4_obuf_GTS_TRI_35 : X_TRI
707 
    port map (
708 
      I => xout_4_obuf_GTS_TRI,
709 
      CTL => NlwInverterSignal_xout_4_obuf_GTS_TRI_CTL,
710 
      O => xout(4)
711 
    );
712 
  xout_3_obuf_GTS_TRI_36 : X_TRI
713 
    port map (
714 
      I => xout_3_obuf_GTS_TRI,
715 
      CTL => NlwInverterSignal_xout_3_obuf_GTS_TRI_CTL,
716 
      O => xout(3)
717 
    );
718 
  xout_2_obuf_GTS_TRI_37 : X_TRI
719 
    port map (
720 
      I => xout_2_obuf_GTS_TRI,
721 
      CTL => NlwInverterSignal_xout_2_obuf_GTS_TRI_CTL,
722 
      O => xout(2)
723 
    );
724 
  xout_1_obuf_GTS_TRI_38 : X_TRI
725 
    port map (
726 
      I => xout_1_obuf_GTS_TRI,
727 
      CTL => NlwInverterSignal_xout_1_obuf_GTS_TRI_CTL,
728 
      O => xout(1)
729 
    );
730 
  xout_0_obuf_GTS_TRI_39 : X_TRI
731 
    port map (
732 
      I => xout_0_obuf_GTS_TRI,
733 
      CTL => NlwInverterSignal_xout_0_obuf_GTS_TRI_CTL,
734 
      O => xout(0)
735 
    );
736 
  NlwBlock_data_gen_VCC : X_ONE
737 
    port map (
738 
      O => VCC
739 
    );
740 
  NlwBlock_data_gen_GND : X_ZERO
741 
    port map (
742 
      O => GND
743 
    );
744 
  NlwInverterBlock_dxout_7_obuf_GTS_TRI_CTL : X_INV
745 
    port map (
746 
      I => GTS,
747 
      O => NlwInverterSignal_dxout_7_obuf_GTS_TRI_CTL
748 
    );
749 
  NlwInverterBlock_dxout_6_obuf_GTS_TRI_CTL : X_INV
750 
    port map (
751 
      I => GTS,
752 
      O => NlwInverterSignal_dxout_6_obuf_GTS_TRI_CTL
753 
    );
754 
  NlwInverterBlock_dxout_5_obuf_GTS_TRI_CTL : X_INV
755 
    port map (
756 
      I => GTS,
757 
      O => NlwInverterSignal_dxout_5_obuf_GTS_TRI_CTL
758 
    );
759 
  NlwInverterBlock_dxout_4_obuf_GTS_TRI_CTL : X_INV
760 
    port map (
761 
      I => GTS,
762 
      O => NlwInverterSignal_dxout_4_obuf_GTS_TRI_CTL
763 
    );
764 
  NlwInverterBlock_dxout_3_obuf_GTS_TRI_CTL : X_INV
765 
    port map (
766 
      I => GTS,
767 
      O => NlwInverterSignal_dxout_3_obuf_GTS_TRI_CTL
768 
    );
769 
  NlwInverterBlock_dxout_2_obuf_GTS_TRI_CTL : X_INV
770 
    port map (
771 
      I => GTS,
772 
      O => NlwInverterSignal_dxout_2_obuf_GTS_TRI_CTL
773 
    );
774 
  NlwInverterBlock_dxout_1_obuf_GTS_TRI_CTL : X_INV
775 
    port map (
776 
      I => GTS,
777 
      O => NlwInverterSignal_dxout_1_obuf_GTS_TRI_CTL
778 
    );
779 
  NlwInverterBlock_dxout_0_obuf_GTS_TRI_CTL : X_INV
780 
    port map (
781 
      I => GTS,
782 
      O => NlwInverterSignal_dxout_0_obuf_GTS_TRI_CTL
783 
    );
784 
  NlwInverterBlock_xout_7_obuf_GTS_TRI_CTL : X_INV
785 
    port map (
786 
      I => GTS,
787 
      O => NlwInverterSignal_xout_7_obuf_GTS_TRI_CTL
788 
    );
789 
  NlwInverterBlock_xout_6_obuf_GTS_TRI_CTL : X_INV
790 
    port map (
791 
      I => GTS,
792 
      O => NlwInverterSignal_xout_6_obuf_GTS_TRI_CTL
793 
    );
794 
  NlwInverterBlock_xout_5_obuf_GTS_TRI_CTL : X_INV
795 
    port map (
796 
      I => GTS,
797 
      O => NlwInverterSignal_xout_5_obuf_GTS_TRI_CTL
798 
    );
799 
  NlwInverterBlock_xout_4_obuf_GTS_TRI_CTL : X_INV
800 
    port map (
801 
      I => GTS,
802 
      O => NlwInverterSignal_xout_4_obuf_GTS_TRI_CTL
803 
    );
804 
  NlwInverterBlock_xout_3_obuf_GTS_TRI_CTL : X_INV
805 
    port map (
806 
      I => GTS,
807 
      O => NlwInverterSignal_xout_3_obuf_GTS_TRI_CTL
808 
    );
809 
  NlwInverterBlock_xout_2_obuf_GTS_TRI_CTL : X_INV
810 
    port map (
811 
      I => GTS,
812 
      O => NlwInverterSignal_xout_2_obuf_GTS_TRI_CTL
813 
    );
814 
  NlwInverterBlock_xout_1_obuf_GTS_TRI_CTL : X_INV
815 
    port map (
816 
      I => GTS,
817 
      O => NlwInverterSignal_xout_1_obuf_GTS_TRI_CTL
818 
    );
819 
  NlwInverterBlock_xout_0_obuf_GTS_TRI_CTL : X_INV
820 
    port map (
821 
      I => GTS,
822 
      O => NlwInverterSignal_xout_0_obuf_GTS_TRI_CTL
823 
    );
824 
  NlwBlockROC : ROC generic map ( WIDTH => 100 ns)
825 
     port map (O => GSR);
826 
  NlwBlockTOC : TOC     port map (O => GTS);
827 
end Structure;
828 
 

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