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[/] [adaptive_lms_equalizer/] [trunk/] [code/] [shift_1d_16.vhd] - Blame information for rev 2

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--  Copyright (C) 2004-2005 Digish Pandya <digish.pandya@gmail.com>
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--  This program is free software; you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation; either version 2 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program; if not, write to the Free Software
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--  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
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-- 16 vit shift regester
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity shift_1d_16 is
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    Port ( xin : in std_logic_vector(15 downto 0);
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           xout : out std_logic_vector(15 downto 0);
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           clock : in std_logic);
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end shift_1d_16;
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architecture Behavioral of shift_1d_16 is
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signal shift_reg: std_logic_vector (15 downto 0);
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begin
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   shift:
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   process(clock)
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   begin
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        if(clock'event and clock = '1') then
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                shift_reg <= xin ;
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        end if;
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  end process;
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  xout <= shift_reg;
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end Behavioral;

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