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[/] [adaptive_lms_equalizer/] [trunk/] [code/] [test_filt_test_sys.vhd] - Blame information for rev 4

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-- VHDL Test Bench Created from source file filt_test_system.vhd -- 13:41:17 03/25/2005
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--
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-- Notes: 
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
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-- that these types always be used for the top-level I/O of a design in order 
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-- to guarantee that the testbench will bind correctly to the post-implementation 
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-- simulation model.
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY testbench IS
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END testbench;
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ARCHITECTURE behavior OF testbench IS
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        COMPONENT filt_test_system
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        PORT(
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                clock : IN std_logic;
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                reset : IN std_logic;
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                adaption_enable : IN std_logic;
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                error_led_out : OUT std_logic_vector(7 downto 0);
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                seg_select : OUT std_logic_vector(3 downto 0);
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                error_freq_out : OUT std_logic;
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          reset_clk : in std_logic;
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                filt_data_out : OUT std_logic_vector(7 downto 0)
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                );
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        END COMPONENT;
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        SIGNAL clock :  std_logic;
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        SIGNAL error_led_out :  std_logic_vector(7 downto 0);
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        SIGNAL seg_select :  std_logic_vector(3 downto 0);
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        SIGNAL error_freq_out :  std_logic;
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        SIGNAL filt_data_out :  std_logic_vector(7 downto 0);
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        SIGNAL reset :  std_logic;
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     signal reset_clk : std_logic;
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        SIGNAL adaption_enable :  std_logic;
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        CONSTANT clk_high   : time := 10 ns;
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        CONSTANT clk_low    : time := 10 ns;
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        CONSTANT clk_period : time := 20 ns;
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        CONSTANT clk_hold   : time := 4 ns;
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BEGIN
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        uut: filt_test_system PORT MAP(
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                clock => clock,
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                error_led_out => error_led_out,
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                seg_select => seg_select,
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                error_freq_out => error_freq_out,
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                filt_data_out => filt_data_out,
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                reset => reset,
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                reset_clk => reset_clk,
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                adaption_enable => adaption_enable
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        );
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-- *** Test Bench - User Defined Section ***
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   clk_gen: PROCESS
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   BEGIN
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            clock <= '1';
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            WAIT FOR clk_high;
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            clock <= '0';
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            WAIT FOR clk_low;
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   END PROCESS clk_gen;
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   reset_gen: process
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   begin
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                reset <= '0';
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                reset_clk <= '0';
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                wait for clk_period*2;
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                reset_clk <= '1';
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                adaption_enable <= '1';
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                wait for clk_period*10;
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                reset <= '1';
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   wait;
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   end process reset_gen;
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-- *** End Test Bench - User Defined Section ***
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END;

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