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//////////////////////////////////////////////////////////////////////
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//// ////
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//// adbg_or1k_module.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Advanced Debug Interface. ////
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//// ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: adbg_or1k_module.v,v $
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// Revision 1.2 2009/05/17 20:54:56 Nathan
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// Changed email address to opencores.org
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//
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// Revision 1.1 2008/07/22 20:28:31 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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//
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// Revision 1.7 2008/07/11 08:13:29 Nathan
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// Latch opcode on posedge, like other signals. This fixes a problem
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// when the module is used with a Xilinx BSCAN TAP. Added signals to
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// allow modules to inhibit latching of a new active module by the top
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// module. This allows the sub-modules to force the top level module
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// to ignore the command present in the input shift register after e.g.
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// a burst read.
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//
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`include "adbg_or1k_defines.v"
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// Module interface
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module adbg_or1k_module (
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// JTAG signals
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tck_i,
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module_tdo_o,
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tdi_i,
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// TAP states
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capture_dr_i,
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shift_dr_i,
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update_dr_i,
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data_register_i, // the data register is at top level, shared between all modules
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module_select_i,
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top_inhibit_o,
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rst_i,
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// Interfate to the OR1K debug unit
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cpu_clk_i,
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cpu_addr_o,
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cpu_data_i,
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cpu_data_o,
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cpu_bp_i,
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cpu_stall_o,
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cpu_stb_o,
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cpu_we_o,
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cpu_ack_i,
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cpu_rst_o
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);
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// JTAG signals
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input tck_i;
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output module_tdo_o;
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input tdi_i; // This is only used by the CRC module - data_register_i[MSB] is delayed a cycle
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// TAP states
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input capture_dr_i;
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input shift_dr_i;
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input update_dr_i;
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input [52:0] data_register_i;
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input module_select_i;
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output top_inhibit_o;
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input rst_i;
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// WISHBONE master interface
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input cpu_clk_i; // 'bus' style interface to SPRs
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output [31:0] cpu_addr_o;
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input [31:0] cpu_data_i;
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output [31:0] cpu_data_o;
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output cpu_stb_o;
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output cpu_we_o;
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input cpu_ack_i;
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output cpu_rst_o; // control lines
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input cpu_bp_i;
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output cpu_stall_o;
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// Declare inputs / outputs as wires / registers
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reg module_tdo_o;
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reg top_inhibit_o;
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// Registers to hold state etc.
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reg [31:0] address_counter; // Holds address for next Wishbone access
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reg [5:0] bit_count; // How many bits have been shifted in/out
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reg [15:0] word_count; // bytes remaining in current burst command
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reg [3:0] operation; // holds the current command (rd/wr, word size)
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reg [31:0] data_out_shift_reg; // parallel-load output shift register
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reg [`DBG_OR1K_REGSELECT_SIZE-1:0] internal_register_select; // Holds index of currently selected register
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wire [1:0] internal_reg_status; // Holds CPU stall and reset status - signal is output of separate module
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// Control signals for the various counters / registers / state machines
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reg addr_sel; // Selects data for address_counter. 0 = data_register_i, 1 = incremented address count
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reg addr_ct_en; // Enable signal for address counter register
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reg op_reg_en; // Enable signal for 'operation' register
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reg bit_ct_en; // enable bit counter
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reg bit_ct_rst; // reset (zero) bit count register
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reg word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
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reg word_ct_en; // Enable byte counter register
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reg out_reg_ld_en; // Enable parallel load of data_out_shift_reg
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reg out_reg_shift_en; // Enable shift of data_out_shift_reg
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reg out_reg_data_sel; // 0 = BIU data, 1 = internal register data
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reg [1:0] tdo_output_sel; // Selects signal to send to TDO. 0 = ready bit, 1 = output register, 2 = CRC match, 3 = CRC shift reg.
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reg biu_strobe; // Indicates that the bus unit should latch data and start a transaction
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reg crc_clr; // resets CRC module
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reg crc_en; // does 1-bit iteration in CRC module
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reg crc_in_sel; // selects incoming write data (=0) or outgoing read data (=1)as input to CRC module
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reg crc_shift_en; // CRC reg is also it's own output shift register; this enables a shift
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reg regsel_ld_en; // Reg. select register load enable
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reg intreg_ld_en; // load enable for internal registers
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// Status signals
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wire word_count_zero; // true when byte counter is zero
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wire bit_count_max; // true when bit counter is equal to current word size
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wire module_cmd; // inverse of MSB of data_register_i. 1 means current cmd not for top level (but is for us)
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wire biu_ready; // indicates that the BIU has finished the last command
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wire burst_instruction; // True when the input_data_i reg has a valid burst instruction for this module
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wire intreg_instruction; // True when the input_data_i reg has a valid internal register instruction
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wire intreg_write; // True when the input_data_i reg has an internal register write op
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wire rd_op; // True when operation in the opcode reg is a read, false when a write
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wire crc_match; // indicates whether data_register_i matches computed CRC
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wire bit_count_32; // true when bit count register == 32, for CRC after burst writes
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// Intermediate signals
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wire [5:0] word_size_bits; // 8,16, or 32. Decoded from 'operation'
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wire [2:0] address_increment; // How much to add to the address counter each iteration
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wire [32:0] incremented_address; // value of address counter plus 'word_size'
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wire [31:0] data_to_addr_counter; // output of the mux in front of the address counter inputs
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wire [15:0] data_to_word_counter; // output of the mux in front of the byte counter input
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wire [15:0] decremented_word_count;
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wire [31:0] address_data_in; // from data_register_i
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wire [15:0] count_data_in; // from data_register_i
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wire [3:0] operation_in; // from data_register_i
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wire [31:0] data_to_biu; // from data_register_i
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wire [31:0] data_from_biu; // to data_out_shift_register
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wire [31:0] crc_data_out; // output of CRC module, to output shift register
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wire crc_data_in; // input to CRC module, either data_register_i[52] or data_out_shift_reg[0]
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wire crc_serial_out;
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wire [`DBG_OR1K_REGSELECT_SIZE-1:0] reg_select_data; // from data_register_i, input to internal register select register
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wire [31:0] out_reg_data; // parallel input to the output shift register
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reg [31:0] data_from_internal_reg; // data from internal reg. MUX to output shift register
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wire status_reg_wr;
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/////////////////////////////////////////////////
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// Combinatorial assignments
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assign module_cmd = ~(data_register_i[52]);
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assign operation_in = data_register_i[51:48];
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assign address_data_in = data_register_i[47:16];
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assign count_data_in = data_register_i[15:0];
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assign data_to_biu = data_register_i[52:21];
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assign reg_select_data = data_register_i[47:(47-(`DBG_OR1K_REGSELECT_SIZE-1))];
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////////////////////////////////////////////////
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// Operation decoder
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// These are only used before the operation is latched, so decode them from operation_in
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assign burst_instruction = (operation_in == `DBG_OR1K_CMD_BWRITE32) | (operation_in == `DBG_OR1K_CMD_BREAD32);
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assign intreg_instruction = ((operation_in == `DBG_OR1K_CMD_IREG_WR) | (operation_in == `DBG_OR1K_CMD_IREG_SEL));
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assign intreg_write = (operation_in == `DBG_OR1K_CMD_IREG_WR);
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// These are constant, the CPU module only does 32-bit accesses
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assign word_size_bits = 5'd31; // Bits is actually bits-1, to make the FSM easier
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assign address_increment = 3'd1; // This is only used to increment the address. SPRs are word-addressed.
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// This is the only thing that actually needs to be saved and 'decoded' from the latched opcode
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// It goes to the BIU each time a transaction is started.
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assign rd_op = operation[2];
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////////////////////////////////////////////////
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// Module-internal register select register (no, that's not redundant.)
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// Also internal register output MUX
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always @ (posedge tck_i or posedge rst_i)
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begin
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if(rst_i) internal_register_select = 1'h0;
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else if(regsel_ld_en) internal_register_select = reg_select_data;
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end
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// This is completely unnecessary here, since the module has only 1 internal
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// register. However, to make the module expandable, it is included anyway.
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always @ (internal_register_select or internal_reg_status)
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begin
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case(internal_register_select)
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`DBG_OR1K_INTREG_STATUS: data_from_internal_reg = {30'h0, internal_reg_status};
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default: data_from_internal_reg = {30'h0, internal_reg_status};
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endcase
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end
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////////////////////////////////////////////////////////////////////
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// Module-internal registers
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// These have generic read/write/select code, but
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// individual registers may have special behavior, defined here.
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// This is the status register, which holds the reset and stall states.
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assign status_reg_wr = (intreg_ld_en & (reg_select_data == `DBG_OR1K_INTREG_STATUS));
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adbg_or1k_status_reg or1k_statusreg_i (
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.data_i(data_register_i[(47-`DBG_OR1K_REGSELECT_SIZE):(47-(`DBG_OR1K_REGSELECT_SIZE+1))]),
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.we_i(status_reg_wr),
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.tck_i(tck_i),
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.bp_i(cpu_bp_i),
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.rst_i(rst_i),
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.cpu_clk_i(cpu_clk_i),
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.ctrl_reg_o(internal_reg_status),
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.cpu_stall_o(cpu_stall_o),
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.cpu_rst_o(cpu_rst_o)
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);
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///////////////////////////////////////////////
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// Address counter
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assign data_to_addr_counter = (addr_sel) ? incremented_address[31:0] : address_data_in;
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assign incremented_address = address_counter + address_increment;
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// Technically, since this data (sometimes) comes from the input shift reg, we should latch on
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// negedge, per the JTAG spec. But that makes things difficult when incrementing.
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always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state
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begin
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if(rst_i)
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address_counter <= 32'h0;
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else if(addr_ct_en)
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address_counter <= data_to_addr_counter;
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end
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////////////////////////////////////////
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// Opcode latch
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always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state
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begin
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if(rst_i)
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operation <= 4'h0;
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else if(op_reg_en)
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operation <= operation_in;
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end
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//////////////////////////////////////
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// Bit counter
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always @ (posedge tck_i or posedge rst_i)
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begin
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if(rst_i) bit_count <= 6'h0;
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else if(bit_ct_rst) bit_count <= 6'h0;
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else if(bit_ct_en) bit_count <= bit_count + 6'h1;
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end
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assign bit_count_max = (bit_count == word_size_bits) ? 1'b1 : 1'b0 ;
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assign bit_count_32 = (bit_count == 6'h20) ? 1'b1 : 1'b0;
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////////////////////////////////////////
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// Word counter
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assign data_to_word_counter = (word_ct_sel) ? decremented_word_count : count_data_in;
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assign decremented_word_count = word_count - 16'h1;
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// Technically, since this data (sometimes) comes from the input shift reg, we should latch on
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| 307 |
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// negedge, per the JTAG spec. But that makes things difficult when incrementing.
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|
|
always @ (posedge tck_i or posedge rst_i) // JTAG spec specifies latch on negative edge in UPDATE_DR state
|
| 309 |
|
|
begin
|
| 310 |
|
|
if(rst_i)
|
| 311 |
|
|
word_count <= 16'h0;
|
| 312 |
|
|
else if(word_ct_en)
|
| 313 |
|
|
word_count <= data_to_word_counter;
|
| 314 |
|
|
end
|
| 315 |
|
|
|
| 316 |
|
|
assign word_count_zero = (word_count == 16'h0);
|
| 317 |
|
|
|
| 318 |
|
|
/////////////////////////////////////////////////////
|
| 319 |
|
|
// Output register and TDO output MUX
|
| 320 |
|
|
|
| 321 |
|
|
assign out_reg_data = (out_reg_data_sel) ? data_from_internal_reg : data_from_biu;
|
| 322 |
|
|
|
| 323 |
|
|
always @ (posedge tck_i or posedge rst_i)
|
| 324 |
|
|
begin
|
| 325 |
|
|
if(rst_i) data_out_shift_reg <= 32'h0;
|
| 326 |
|
|
else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
|
| 327 |
|
|
else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[31:1]};
|
| 328 |
|
|
end
|
| 329 |
|
|
|
| 330 |
|
|
|
| 331 |
|
|
always @ (tdo_output_sel or data_out_shift_reg[0] or biu_ready or crc_match or crc_serial_out)
|
| 332 |
|
|
begin
|
| 333 |
|
|
if(tdo_output_sel == 2'h0) module_tdo_o <= biu_ready;
|
| 334 |
|
|
else if(tdo_output_sel == 2'h1) module_tdo_o <= data_out_shift_reg[0];
|
| 335 |
|
|
else if(tdo_output_sel == 2'h2) module_tdo_o <= crc_match;
|
| 336 |
|
|
else module_tdo_o <= crc_serial_out;
|
| 337 |
|
|
end
|
| 338 |
|
|
|
| 339 |
|
|
////////////////////////////////////////
|
| 340 |
|
|
// Bus Interface Unit (to OR1K SPR bus)
|
| 341 |
|
|
// It is assumed that the BIU has internal registers, and will
|
| 342 |
|
|
// latch address, operation, and write data on rising clock edge
|
| 343 |
|
|
// when strobe is asserted
|
| 344 |
|
|
|
| 345 |
|
|
adbg_or1k_biu or1k_biu_i (
|
| 346 |
|
|
// Debug interface signals
|
| 347 |
|
|
.tck_i (tck_i),
|
| 348 |
|
|
.rst_i (rst_i),
|
| 349 |
|
|
.data_i (data_to_biu),
|
| 350 |
|
|
.data_o (data_from_biu),
|
| 351 |
|
|
.addr_i (address_counter),
|
| 352 |
|
|
.strobe_i (biu_strobe),
|
| 353 |
|
|
.rd_wrn_i (rd_op), // If 0, then write op
|
| 354 |
|
|
.rdy_o (biu_ready),
|
| 355 |
|
|
// This bus has no error signal
|
| 356 |
|
|
|
| 357 |
|
|
// OR1K SPR bus signals
|
| 358 |
|
|
.cpu_clk_i(cpu_clk_i),
|
| 359 |
|
|
.cpu_addr_o(cpu_addr_o),
|
| 360 |
|
|
.cpu_data_i(cpu_data_i),
|
| 361 |
|
|
.cpu_data_o(cpu_data_o),
|
| 362 |
|
|
.cpu_stb_o(cpu_stb_o),
|
| 363 |
|
|
.cpu_we_o(cpu_we_o),
|
| 364 |
|
|
.cpu_ack_i(cpu_ack_i)
|
| 365 |
|
|
);
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
/////////////////////////////////////
|
| 370 |
|
|
// CRC module
|
| 371 |
|
|
|
| 372 |
|
|
assign crc_data_in = (crc_in_sel) ? tdi_i : data_out_shift_reg[0]; // MUX, write or read data
|
| 373 |
|
|
|
| 374 |
|
|
adbg_crc32 or1k_crc_i
|
| 375 |
|
|
(
|
| 376 |
|
|
.clk(tck_i),
|
| 377 |
|
|
.data(crc_data_in),
|
| 378 |
|
|
.enable(crc_en),
|
| 379 |
|
|
.shift(crc_shift_en),
|
| 380 |
|
|
.clr(crc_clr),
|
| 381 |
|
|
.rst(rst_i),
|
| 382 |
|
|
.crc_out(crc_data_out),
|
| 383 |
|
|
.serial_out(crc_serial_out)
|
| 384 |
|
|
);
|
| 385 |
|
|
|
| 386 |
|
|
assign crc_match = (data_register_i[52:21] == crc_data_out) ? 1'b1 : 1'b0;
|
| 387 |
|
|
|
| 388 |
|
|
////////////////////////////////////////
|
| 389 |
|
|
// Control FSM
|
| 390 |
|
|
|
| 391 |
|
|
// Definition of machine state values.
|
| 392 |
|
|
// Don't worry too much about the state encoding, the synthesis tool
|
| 393 |
|
|
// will probably re-encode it anyway.
|
| 394 |
|
|
|
| 395 |
|
|
`define STATE_idle 4'h0
|
| 396 |
|
|
`define STATE_Rbegin 4'h1
|
| 397 |
|
|
`define STATE_Rready 4'h2
|
| 398 |
|
|
`define STATE_Rstatus 4'h3
|
| 399 |
|
|
`define STATE_Rburst 4'h4
|
| 400 |
|
|
`define STATE_Wready 4'h5
|
| 401 |
|
|
`define STATE_Wwait 4'h6
|
| 402 |
|
|
`define STATE_Wburst 4'h7
|
| 403 |
|
|
`define STATE_Wstatus 4'h8
|
| 404 |
|
|
`define STATE_Rcrc 4'h9
|
| 405 |
|
|
`define STATE_Wcrc 4'ha
|
| 406 |
|
|
`define STATE_Wmatch 4'hb
|
| 407 |
|
|
|
| 408 |
|
|
reg [3:0] module_state; // FSM state
|
| 409 |
|
|
reg [3:0] module_next_state; // combinatorial signal, not actually a register
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
// sequential part of the FSM
|
| 414 |
|
|
always @ (posedge tck_i or posedge rst_i)
|
| 415 |
|
|
begin
|
| 416 |
|
|
if(rst_i)
|
| 417 |
|
|
module_state <= `STATE_idle;
|
| 418 |
|
|
else
|
| 419 |
|
|
module_state <= module_next_state;
|
| 420 |
|
|
end
|
| 421 |
|
|
|
| 422 |
|
|
|
| 423 |
|
|
// Determination of next state; purely combinatorial
|
| 424 |
|
|
always @ (module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2]
|
| 425 |
|
|
or word_count_zero or bit_count_max or data_register_i[52] or bit_count_32 or biu_ready
|
| 426 |
|
|
or module_cmd or intreg_write or decremented_word_count or burst_instruction)
|
| 427 |
|
|
begin
|
| 428 |
|
|
case(module_state)
|
| 429 |
|
|
`STATE_idle:
|
| 430 |
|
|
begin
|
| 431 |
|
|
if(module_cmd && module_select_i && update_dr_i && burst_instruction && operation_in[2]) module_next_state <= `STATE_Rbegin;
|
| 432 |
|
|
else if(module_cmd && module_select_i && update_dr_i && burst_instruction) module_next_state <= `STATE_Wready;
|
| 433 |
|
|
else module_next_state <= `STATE_idle;
|
| 434 |
|
|
end
|
| 435 |
|
|
|
| 436 |
|
|
`STATE_Rbegin:
|
| 437 |
|
|
begin
|
| 438 |
|
|
if(word_count_zero) module_next_state <= `STATE_idle; // set up a burst of size 0, illegal.
|
| 439 |
|
|
else module_next_state <= `STATE_Rready;
|
| 440 |
|
|
end
|
| 441 |
|
|
`STATE_Rready:
|
| 442 |
|
|
begin
|
| 443 |
|
|
if(module_select_i && capture_dr_i) module_next_state <= `STATE_Rstatus;
|
| 444 |
|
|
else module_next_state <= `STATE_Rready;
|
| 445 |
|
|
end
|
| 446 |
|
|
`STATE_Rstatus:
|
| 447 |
|
|
begin
|
| 448 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle;
|
| 449 |
|
|
else if (biu_ready) module_next_state <= `STATE_Rburst;
|
| 450 |
|
|
else module_next_state <= `STATE_Rstatus;
|
| 451 |
|
|
end
|
| 452 |
|
|
`STATE_Rburst:
|
| 453 |
|
|
begin
|
| 454 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle;
|
| 455 |
|
|
else if(bit_count_max && word_count_zero) module_next_state <= `STATE_Rcrc;
|
| 456 |
|
|
else if(bit_count_max) module_next_state <= `STATE_Rstatus;
|
| 457 |
|
|
else module_next_state <= `STATE_Rburst;
|
| 458 |
|
|
end
|
| 459 |
|
|
`STATE_Rcrc:
|
| 460 |
|
|
begin
|
| 461 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle;
|
| 462 |
|
|
// This doubles as the 'recovery' state, so stay here until update_dr_i.
|
| 463 |
|
|
else module_next_state <= `STATE_Rcrc;
|
| 464 |
|
|
end
|
| 465 |
|
|
|
| 466 |
|
|
`STATE_Wready:
|
| 467 |
|
|
begin
|
| 468 |
|
|
if(word_count_zero) module_next_state <= `STATE_idle;
|
| 469 |
|
|
else if(module_select_i && capture_dr_i) module_next_state <= `STATE_Wwait;
|
| 470 |
|
|
else module_next_state <= `STATE_Wready;
|
| 471 |
|
|
end
|
| 472 |
|
|
`STATE_Wwait:
|
| 473 |
|
|
begin
|
| 474 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
|
| 475 |
|
|
else if(module_select_i && data_register_i[52]) module_next_state <= `STATE_Wburst; // Got a start bit
|
| 476 |
|
|
else module_next_state <= `STATE_Wwait;
|
| 477 |
|
|
end
|
| 478 |
|
|
`STATE_Wburst:
|
| 479 |
|
|
begin
|
| 480 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
|
| 481 |
|
|
else if(bit_count_max) module_next_state <= `STATE_Wstatus;
|
| 482 |
|
|
else module_next_state <= `STATE_Wburst;
|
| 483 |
|
|
end
|
| 484 |
|
|
`STATE_Wstatus:
|
| 485 |
|
|
begin
|
| 486 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
|
| 487 |
|
|
else if(word_count_zero) module_next_state <= `STATE_Wcrc;
|
| 488 |
|
|
// can't wait until bus ready if multiple devices in chain...
|
| 489 |
|
|
// Would have to read postfix_bits, then send another start bit and push it through
|
| 490 |
|
|
// prefix_bits...potentially very inefficient.
|
| 491 |
|
|
else module_next_state <= `STATE_Wburst;
|
| 492 |
|
|
end
|
| 493 |
|
|
|
| 494 |
|
|
`STATE_Wcrc:
|
| 495 |
|
|
begin
|
| 496 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
|
| 497 |
|
|
else if(bit_count_32) module_next_state <= `STATE_Wmatch;
|
| 498 |
|
|
else module_next_state <= `STATE_Wcrc;
|
| 499 |
|
|
end
|
| 500 |
|
|
|
| 501 |
|
|
`STATE_Wmatch:
|
| 502 |
|
|
begin
|
| 503 |
|
|
if(update_dr_i) module_next_state <= `STATE_idle;
|
| 504 |
|
|
// This doubles as our recovery state, stay here until update_dr_i
|
| 505 |
|
|
else module_next_state <= `STATE_Wmatch;
|
| 506 |
|
|
end
|
| 507 |
|
|
|
| 508 |
|
|
default: module_next_state <= `STATE_idle; // shouldn't actually happen...
|
| 509 |
|
|
endcase
|
| 510 |
|
|
end
|
| 511 |
|
|
|
| 512 |
|
|
|
| 513 |
|
|
// Outputs of state machine, pure combinatorial
|
| 514 |
|
|
always @ (module_state or module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2]
|
| 515 |
|
|
or word_count_zero or bit_count_max or data_register_i[52] or biu_ready or intreg_instruction
|
| 516 |
|
|
or module_cmd or intreg_write or decremented_word_count)
|
| 517 |
|
|
begin
|
| 518 |
|
|
// Default everything to 0, keeps the case statement simple
|
| 519 |
|
|
addr_sel <= 1'b1; // Selects data for address_counter. 0 = data_register_i, 1 = incremented address count
|
| 520 |
|
|
addr_ct_en <= 1'b0; // Enable signal for address counter register
|
| 521 |
|
|
op_reg_en <= 1'b0; // Enable signal for 'operation' register
|
| 522 |
|
|
bit_ct_en <= 1'b0; // enable bit counter
|
| 523 |
|
|
bit_ct_rst <= 1'b0; // reset (zero) bit count register
|
| 524 |
|
|
word_ct_sel <= 1'b1; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count
|
| 525 |
|
|
word_ct_en <= 1'b0; // Enable byte counter register
|
| 526 |
|
|
out_reg_ld_en <= 1'b0; // Enable parallel load of data_out_shift_reg
|
| 527 |
|
|
out_reg_shift_en <= 1'b0; // Enable shift of data_out_shift_reg
|
| 528 |
|
|
tdo_output_sel <= 2'b1; // 1 = data reg, 0 = biu_ready, 2 = crc_match, 3 = CRC data
|
| 529 |
|
|
biu_strobe <= 1'b0;
|
| 530 |
|
|
crc_clr <= 1'b0;
|
| 531 |
|
|
crc_en <= 1'b0; // add the input bit to the CRC calculation
|
| 532 |
|
|
crc_in_sel <= 1'b0; // 0 = tdo, 1 = tdi
|
| 533 |
|
|
crc_shift_en <= 1'b0;
|
| 534 |
|
|
out_reg_data_sel <= 1'b1; // 0 = BIU data, 1 = internal register data
|
| 535 |
|
|
regsel_ld_en <= 1'b0;
|
| 536 |
|
|
intreg_ld_en <= 1'b0;
|
| 537 |
|
|
top_inhibit_o <= 1'b0; // Don't disable the top-level module in the default case
|
| 538 |
|
|
|
| 539 |
|
|
case(module_state)
|
| 540 |
|
|
`STATE_idle:
|
| 541 |
|
|
begin
|
| 542 |
|
|
addr_sel <= 1'b0;
|
| 543 |
|
|
word_ct_sel <= 1'b0;
|
| 544 |
|
|
|
| 545 |
|
|
// Operations for internal registers - stay in idle state
|
| 546 |
|
|
if(module_select_i & shift_dr_i) out_reg_shift_en <= 1'b1; // For module regs
|
| 547 |
|
|
if(module_select_i & capture_dr_i)
|
| 548 |
|
|
begin
|
| 549 |
|
|
out_reg_data_sel <= 1'b1; // select internal register data
|
| 550 |
|
|
out_reg_ld_en <= 1'b1; // For module regs
|
| 551 |
|
|
end
|
| 552 |
|
|
if(module_select_i & module_cmd & update_dr_i) begin
|
| 553 |
|
|
if(intreg_instruction) regsel_ld_en <= 1'b1; // For module regs
|
| 554 |
|
|
if(intreg_write) intreg_ld_en <= 1'b1; // For module regs
|
| 555 |
|
|
end
|
| 556 |
|
|
|
| 557 |
|
|
// Burst operations
|
| 558 |
|
|
if(module_next_state != `STATE_idle) begin // Do the same to receive read or write opcode
|
| 559 |
|
|
addr_ct_en <= 1'b1;
|
| 560 |
|
|
op_reg_en <= 1'b1;
|
| 561 |
|
|
bit_ct_rst <= 1'b1;
|
| 562 |
|
|
word_ct_en <= 1'b1;
|
| 563 |
|
|
crc_clr <= 1'b1;
|
| 564 |
|
|
end
|
| 565 |
|
|
end
|
| 566 |
|
|
|
| 567 |
|
|
`STATE_Rbegin:
|
| 568 |
|
|
begin
|
| 569 |
|
|
if(!word_count_zero) begin // Start a biu read transaction
|
| 570 |
|
|
biu_strobe <= 1'b1;
|
| 571 |
|
|
addr_sel <= 1'b1;
|
| 572 |
|
|
addr_ct_en <= 1'b1;
|
| 573 |
|
|
end
|
| 574 |
|
|
end
|
| 575 |
|
|
|
| 576 |
|
|
`STATE_Rready:
|
| 577 |
|
|
; // Just a wait state
|
| 578 |
|
|
|
| 579 |
|
|
`STATE_Rstatus:
|
| 580 |
|
|
begin
|
| 581 |
|
|
tdo_output_sel <= 2'h0;
|
| 582 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
| 583 |
|
|
|
| 584 |
|
|
if (module_next_state == `STATE_Rburst) begin
|
| 585 |
|
|
out_reg_data_sel <= 1'b0; // select BIU data
|
| 586 |
|
|
out_reg_ld_en <= 1'b1;
|
| 587 |
|
|
bit_ct_rst <= 1'b1;
|
| 588 |
|
|
word_ct_sel <= 1'b1;
|
| 589 |
|
|
word_ct_en <= 1'b1;
|
| 590 |
|
|
if(!(decremented_word_count == 0) && !word_count_zero) begin // Start a biu read transaction
|
| 591 |
|
|
biu_strobe <= 1'b1;
|
| 592 |
|
|
addr_sel <= 1'b1;
|
| 593 |
|
|
addr_ct_en <= 1'b1;
|
| 594 |
|
|
end
|
| 595 |
|
|
end
|
| 596 |
|
|
end
|
| 597 |
|
|
|
| 598 |
|
|
`STATE_Rburst:
|
| 599 |
|
|
begin
|
| 600 |
|
|
tdo_output_sel <= 2'h1;
|
| 601 |
|
|
out_reg_shift_en <= 1'b1;
|
| 602 |
|
|
bit_ct_en <= 1'b1;
|
| 603 |
|
|
crc_en <= 1'b1;
|
| 604 |
|
|
crc_in_sel <= 1'b0; // read data in output shift register LSB (tdo)
|
| 605 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
| 606 |
|
|
end
|
| 607 |
|
|
|
| 608 |
|
|
`STATE_Rcrc:
|
| 609 |
|
|
begin
|
| 610 |
|
|
// Just shift out the data, don't bother counting, we don't move on until update_dr_i
|
| 611 |
|
|
tdo_output_sel <= 2'h3;
|
| 612 |
|
|
crc_shift_en <= 1'b1;
|
| 613 |
|
|
top_inhibit_o <= 1'b1;
|
| 614 |
|
|
end
|
| 615 |
|
|
|
| 616 |
|
|
`STATE_Wready:
|
| 617 |
|
|
; // Just a wait state
|
| 618 |
|
|
|
| 619 |
|
|
`STATE_Wwait:
|
| 620 |
|
|
begin
|
| 621 |
|
|
tdo_output_sel <= 2'h1;
|
| 622 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
| 623 |
|
|
if(module_next_state == `STATE_Wburst) begin
|
| 624 |
|
|
bit_ct_en <= 1'b1;
|
| 625 |
|
|
word_ct_sel <= 1'b1; // Pre-decrement the byte count
|
| 626 |
|
|
word_ct_en <= 1'b1;
|
| 627 |
|
|
crc_en <= 1'b1; // CRC gets tdi_i, which is 1 cycle ahead of data_register_i, so we need the bit there now in the CRC
|
| 628 |
|
|
crc_in_sel <= 1'b1; // read data from tdi_i
|
| 629 |
|
|
end
|
| 630 |
|
|
end
|
| 631 |
|
|
|
| 632 |
|
|
`STATE_Wburst:
|
| 633 |
|
|
begin
|
| 634 |
|
|
bit_ct_en <= 1'b1;
|
| 635 |
|
|
tdo_output_sel <= 2'h1;
|
| 636 |
|
|
crc_en <= 1'b1;
|
| 637 |
|
|
crc_in_sel <= 1'b1; // read data from tdi_i
|
| 638 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
| 639 |
|
|
end
|
| 640 |
|
|
|
| 641 |
|
|
`STATE_Wstatus:
|
| 642 |
|
|
begin
|
| 643 |
|
|
tdo_output_sel <= 2'h0; // Send the status bit to TDO
|
| 644 |
|
|
// start transaction
|
| 645 |
|
|
biu_strobe <= 1'b1; // Start a BIU transaction
|
| 646 |
|
|
word_ct_sel <= 1'b1; // Decrement the byte count
|
| 647 |
|
|
word_ct_en <= 1'b1;
|
| 648 |
|
|
bit_ct_rst <= 1'b1; // Zero the bit count
|
| 649 |
|
|
addr_ct_en <= 1'b1; // Increment thte address counter
|
| 650 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
| 651 |
|
|
end
|
| 652 |
|
|
|
| 653 |
|
|
`STATE_Wcrc:
|
| 654 |
|
|
begin
|
| 655 |
|
|
bit_ct_en <= 1'b1;
|
| 656 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
| 657 |
|
|
if(module_next_state == `STATE_Wmatch) tdo_output_sel <= 2'h2; // This is when the 'match' bit is actually read
|
| 658 |
|
|
end
|
| 659 |
|
|
|
| 660 |
|
|
`STATE_Wmatch:
|
| 661 |
|
|
begin
|
| 662 |
|
|
tdo_output_sel <= 2'h2;
|
| 663 |
|
|
top_inhibit_o <= 1'b1; // in case of early termination
|
| 664 |
|
|
end
|
| 665 |
|
|
|
| 666 |
|
|
default: ;
|
| 667 |
|
|
endcase
|
| 668 |
|
|
end
|
| 669 |
|
|
|
| 670 |
|
|
|
| 671 |
|
|
endmodule
|
| 672 |
|
|
|
