| 1 |
3 |
nyawn |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// OR1K test app definitions ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// This file is part of the OR1K test application ////
|
| 6 |
|
|
//// http://www.opencores.org/cores/or1k/xess/ ////
|
| 7 |
|
|
//// ////
|
| 8 |
|
|
//// Description ////
|
| 9 |
|
|
//// DEfine target technology etc. Right now FIFOs are available ////
|
| 10 |
|
|
//// only for Xilinx Virtex FPGAs. (TARGET_VIRTEX) ////
|
| 11 |
|
|
//// ////
|
| 12 |
|
|
//// To Do: ////
|
| 13 |
|
|
//// - nothing really ////
|
| 14 |
|
|
//// ////
|
| 15 |
|
|
//// Author(s): ////
|
| 16 |
|
|
//// - Damjan Lampret, damjan.lampret@opencores.org ////
|
| 17 |
|
|
//// ////
|
| 18 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 19 |
|
|
//// ////
|
| 20 |
|
|
//// Copyright (C) 2001 Authors ////
|
| 21 |
|
|
//// ////
|
| 22 |
|
|
//// This source file may be used and distributed without ////
|
| 23 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 24 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 25 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 26 |
|
|
//// ////
|
| 27 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 28 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 29 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 30 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 31 |
|
|
//// later version. ////
|
| 32 |
|
|
//// ////
|
| 33 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 34 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 35 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 36 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 37 |
|
|
//// details. ////
|
| 38 |
|
|
//// ////
|
| 39 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 40 |
|
|
//// Public License along with this source; if not, download it ////
|
| 41 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 42 |
|
|
//// ////
|
| 43 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 44 |
|
|
//
|
| 45 |
|
|
// CVS Revision History
|
| 46 |
|
|
//
|
| 47 |
|
|
// $Log: xsv_fpga_defines.v,v $
|
| 48 |
|
|
// Revision 1.2 2008/07/11 08:16:01 Nathan
|
| 49 |
|
|
// Ran through dos2unix
|
| 50 |
|
|
//
|
| 51 |
|
|
// Revision 1.1 2008/07/08 19:11:54 Nathan
|
| 52 |
|
|
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
|
| 53 |
|
|
//
|
| 54 |
|
|
// Revision 1.4 2004/04/05 08:44:35 lampret
|
| 55 |
|
|
// Merged branch_qmem into main tree.
|
| 56 |
|
|
//
|
| 57 |
|
|
// Revision 1.2 2002/03/29 20:58:51 lampret
|
| 58 |
|
|
// Changed hardcoded address for fake MC to use a define.
|
| 59 |
|
|
//
|
| 60 |
|
|
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
|
| 61 |
|
|
// First import of the "new" XESS XSV environment.
|
| 62 |
|
|
//
|
| 63 |
|
|
//
|
| 64 |
|
|
//
|
| 65 |
|
|
|
| 66 |
|
|
//
|
| 67 |
|
|
// Define to target to Xilinx Virtex
|
| 68 |
|
|
//
|
| 69 |
|
|
//`define TARGET_VIRTEX
|
| 70 |
|
|
|
| 71 |
|
|
//
|
| 72 |
|
|
// Interrupts
|
| 73 |
|
|
//
|
| 74 |
|
|
`define APP_INT_RES1 1:0
|
| 75 |
|
|
`define APP_INT_UART 2
|
| 76 |
|
|
`define APP_INT_RES2 3
|
| 77 |
|
|
`define APP_INT_ETH 4
|
| 78 |
|
|
`define APP_INT_PS2 5
|
| 79 |
|
|
`define APP_INT_RES3 19:6
|
| 80 |
|
|
|
| 81 |
|
|
//
|
| 82 |
|
|
// Address map
|
| 83 |
|
|
//
|
| 84 |
|
|
`define APP_ADDR_DEC_W 3
|
| 85 |
|
|
`define APP_ADDR_SDRAM `APP_ADDR_DEC_W'b001
|
| 86 |
|
|
`define APP_ADDR_DEC2_W 8
|
| 87 |
|
|
`define APP_ADDR_OCRAM `APP_ADDR_DEC2_W'h00
|
| 88 |
|
|
`define APP_ADDR_DECP_W 8
|
| 89 |
|
|
//`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h99
|
| 90 |
|
|
`define APP_ADDR_VGA `APP_ADDR_DECP_W'h97
|
| 91 |
|
|
`define APP_ADDR_ETH `APP_ADDR_DECP_W'h92
|
| 92 |
|
|
`define APP_ADDR_AUDIO `APP_ADDR_DECP_W'h9d
|
| 93 |
|
|
`define APP_ADDR_UART `APP_ADDR_DECP_W'h90
|
| 94 |
|
|
`define APP_ADDR_PS2 `APP_ADDR_DECP_W'h94
|
| 95 |
|
|
`define APP_ADDR_RES1 `APP_ADDR_DECP_W'h9e
|
| 96 |
|
|
//`define APP_ADDR_RES2 `APP_ADDR_DECP_W'h9f
|
| 97 |
|
|
//`define APP_ADDR_FAKEMC 4'h6
|
| 98 |
|
|
|
| 99 |
|
|
// For simulation...
|
| 100 |
|
|
// `define DBG_IF_MODEL 1
|
