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//////////////////////////////////////////////////////////////////////
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//// ////
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//// adv_dbg_tb.v ////
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//// ////
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//// ////
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//// Testbench for the SoC Advanced Debug Interface. ////
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//// This testbench specifically tests the JTAG serial port ////
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//// ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencored.org) ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "tap_defines.v"
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`include "adbg_defines.v"
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`include "adbg_wb_defines.v"
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// Polynomial for the CRC calculation
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// Yes, it's backwards. Yes, this is on purpose.
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// To decrease logic + routing, we want to shift the CRC calculation
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// in the same direction we use to shift the data out, LSB first.
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`define DBG_CRC_POLY 32'hedb88320
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// These are indicies into an array which hold values for the JTAG outputs
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`define JTAG_TMS 0
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`define JTAG_TCK 1
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`define JTAG_TDO 2
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`define JTAG_TMS_bit 3'h1
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`define JTAG_TCK_bit 3'h2
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`define JTAG_TDO_bit 3'h4
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`define wait_jtag_period #50
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module adv_debug_tb;
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// Connections to the JTAG TAP
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reg jtag_tck_o;
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reg jtag_tms_o;
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reg jtag_tdo_o;
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wire jtag_tdi_i;
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// Connections between TAP and debug module
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wire capture_dr;
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wire shift_dr;
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wire pause_dr;
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wire update_dr;
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wire dbg_rst;
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wire dbg_tdi;
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wire dbg_tdo;
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wire dbg_sel;
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// Connections between the debug module and the wishbone
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`ifdef DBG_WISHBONE_SUPPORTED
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wire [31:0] wb_adr;
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wire [31:0] wb_dat_m;
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wire [31:0] wb_dat_s;
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wire wb_cyc;
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wire wb_stb;
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wire [3:0] wb_sel;
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wire wb_we;
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wire wb_ack;
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wire wb_err;
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reg wb_clk_i; // the wishbone clock
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reg wb_rst_i;
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`endif
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`ifdef DBG_CPU0_SUPPORTED
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wire cpu0_clk;
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wire [31:0]cpu0_addr;
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wire [31:0] cpu0_data_c;
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wire [31:0] cpu0_data_d;
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wire cpu0_bp;
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wire cpu0_stall;
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wire cpu0_stb;
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wire cpu0_we;
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wire cpu0_ack;
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wire cpu0_rst;
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`endif
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wire jsp_int;
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reg test_enabled;
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// Data which will be written to the WB interface
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reg [31:0] static_data32 [0:15];
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reg [15:0] static_data16 [0:15];
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reg [7:0] static_data8 [0:15];
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// Arrays to hold data read back from the WB interface, for comparison
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reg [31:0] input_data32 [0:15];
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reg [15:0] input_data16 [0:15];
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reg [7:0] input_data8 [0:15];
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reg [32:0] err_data; // holds the contents of the error register from the various modules
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reg failed;
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integer i;
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reg [63:0] jsp_data8;
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initial
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begin
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jtag_tck_o = 1'b0;
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jtag_tms_o = 1'b0;
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jtag_tdo_o = 1'b0;
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end
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// Provide the wishbone clock
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`ifdef DBG_WISHBONE_SUPPORTED
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initial
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begin
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wb_clk_i = 1'b0;
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forever #7 wb_clk_i = ~wb_clk_i; // Odd frequency ratio to test the synchronization
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end
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`endif
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// Start the test (and reset the wishbone)
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initial
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begin
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test_enabled = 1'b0;
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wb_rst_i = 1'b0;
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#100;
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wb_rst_i = 1'b1;
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#100;
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wb_rst_i = 1'b0;
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// Init the memory
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initialize_memory(32'h0,32'h16);
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#1 test_enabled<=#1 1'b1;
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end
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// This is the main test procedure
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always @ (posedge test_enabled)
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begin
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$display("Starting advanced debug JTAG serial port test");
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reset_jtag;
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#1000;
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check_idcode;
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#1000;
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// Select the debug module in the IR
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set_ir(`DEBUG);
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#1000;
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///////////////////////////////////////////////////////////////////
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// Test the JTAG serial port. We use the debug unit WB interface
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// to act as the CPU/WB master.
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////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////
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// Do an 8 byte transfer, JSP->WB
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$display("-------------------------------------------");
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$display("--- Test 1: 8 bytes JSP->WB");
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// Write 8 bytes from JTAG to WB
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$display("Selecting JSP module at time %t", $time);
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select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
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#200
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$display("JTAG putting 8 bytes to JSP module at time %t", $time);
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do_jsp_read_write(4'h8,jsp_data8); // 4 bits words to write, 64 bits output data
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// data returned in input_data8[]
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// Select the WB unit in the debug module, read the data written
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#1000;
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$display("Selecting Wishbone module at time %t", $time);
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select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
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failed <= 1'b0;
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for(i = 0; i < 8; i=i+1) begin
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do_module_burst_read(3'h1, 16'd1, 32'h0);
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//$display("WB read got 0x%x", input_data8[0]);
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if(input_data8[0] != i) begin
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failed = 1;
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$display("JSP-to-WB data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
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//$display("JTAG read got 0x%x", input_data8[i]);
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end
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end
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if(!failed) $display("WB-to-JSP data: 8 bytes OK! Test 1 passed!");
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/////////////////////////////////////////////////////
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// Do an 8-byte transfer, WB->JSP
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$display("-------------------------------------------");
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$display("--- Test 2: 8 bytes WB->JSP");
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// Put 8 bytes from the WB into the JSP
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#1000
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$display("WB putting 8 bytes to JSP module at time %t", $time);
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for(i = 0; i < 8; i=i+1) begin
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static_data8[0] = i;
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do_module_burst_write(3'h1, 16'd1, 32'h0);
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end
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// Get 8 bytes from the JSP
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#1000
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$display("Selecting JSP module at time %t", $time);
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select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
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#1000
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$display("JTAG getting 8 bytes from JSP module at time %t", $time);
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do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
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// data returned in input_data8[]
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failed <= 1'b0;
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for(i = 0; i < 8; i=i+1) begin
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if(i != input_data8[i]) begin
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failed = 1;
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$display("WB-to-JSP data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
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//$display("JTAG read got 0x%x", input_data8[i]);
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end
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end
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if(!failed) $display("WB-to-JSP data: 8 bytes OK! Test 2 passed!");
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//////////////////////////////////////
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// Write 4 bytes, then 4 more, JSP->WB (read all back at once)
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$display("-------------------------------------------");
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$display("--- Test 3: 4+4 bytes, JSP->WB");
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// Write 4 bytes from JTAG
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#1000
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$display("Selecting JSP module at time %t", $time);
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select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
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#200
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$display("JTAG putting 4 bytes to JSP module at time %t", $time);
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do_jsp_read_write(4'h4,jsp_data8); // 4 bits words to write, 64 bits output data
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do_jsp_read_write(4'h4,jsp_data8); // 4 bits words to write, 64 bits output data
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// data returned in input_data8[]
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// Select the WB unit in the debug module, read the data written
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#1000;
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$display("Selecting Wishbone module at time %t", $time);
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select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
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failed <= 1'b0;
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for(i = 0; i < 4; i=i+1) begin
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do_module_burst_read(3'h1, 16'd1, 32'h0);
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if(input_data8[0] != i) begin
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failed = 1;
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$display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
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end
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end
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for(i = 0; i < 4; i=i+1) begin
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do_module_burst_read(3'h1, 16'd1, 32'h0);
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if(input_data8[0] != i) begin
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failed = 1;
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$display("JSP-to-WB 4+4 data mismatch at index %d, wrote 0x%x, read 0x%x", i+4, i, input_data8[i]);
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end
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end
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if(!failed) $display("WB-to-JSP 4+4 data: 8 bytes OK! Test 3 passed!");
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////////////////////////////////////////
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// Read 8 from JTAG, put 4 to WB
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$display("-------------------------------------------");
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$display("--- Test 4: 8 bytes WB->JSP, 4 bytes JSP->WB");
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// Put 8 bytes from the WB into the JSP
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#1000
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$display("Selecting Wishbone module at time %t", $time);
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select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
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$display("WB putting 8 bytes to JSP module for R8W4 read at time %t", $time);
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for(i = 0; i < 8; i=i+1) begin
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static_data8[0] = i;
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do_module_burst_write(3'h1, 16'd1, 32'h0);
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end
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// Get 8 bytes from the JSP, put 4 to WB
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#1000
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$display("Selecting JSP module at time %t", $time);
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select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
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#1000
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$display("JTAG getting 8 and putting 4 at time %t", $time);
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do_jsp_read_write(4'h4,jsp_data8); // 4 bits words to write, 64 bits output data
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// data returned in input_data8[]
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failed <= 1'b0;
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for(i = 0; i < 8; i=i+1) begin
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316 |
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if(i != input_data8[i]) begin
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failed = 1;
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$display("R8W4 data mismatch getting JSP data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
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end
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end
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if(!failed) $display("R8W4: 8 JSP bytes OK!");
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// Remove the 4 bytes via the WB
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#1000;
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$display("Selecting Wishbone module at time %t", $time);
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select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
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failed <= 1'b0;
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for(i = 0; i < 4; i=i+1) begin
|
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do_module_burst_read(3'h1, 16'd1, 32'h0);
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if(input_data8[0] != i) begin
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failed = 1;
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$display("R8W4 data mismatch clearing WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
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end
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end
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if(!failed) $display("R8W4: 4 WB bytes OK!");
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336 |
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///////////////////////////////////////////////////
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338 |
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// Test putting more data than space available
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339 |
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340 |
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$display("-------------------------------------------");
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341 |
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$display("--- Test 5: Put 6 JSP->WB, then 6 more");
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342 |
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// put 6 to WB
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344 |
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#1000
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$display("Selecting JSP module at time %t", $time);
|
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select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
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347 |
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#1000
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348 |
|
|
$display("JTAG putting 6 at time %t", $time);
|
349 |
|
|
do_jsp_read_write(4'h6,jsp_data8); // 4 bits words to write, 64 bits output data
|
350 |
|
|
|
351 |
|
|
// put 6 more
|
352 |
|
|
#1000
|
353 |
|
|
$display("Selecting JSP module at time %t", $time);
|
354 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
355 |
|
|
#1000
|
356 |
|
|
$display("JTAG putting 6 at time %t", $time);
|
357 |
|
|
do_jsp_read_write(4'h6,jsp_data8); // 4 bits words to write, 64 bits output data
|
358 |
|
|
|
359 |
|
|
|
360 |
|
|
// Get the data back from the WB
|
361 |
|
|
#1000;
|
362 |
|
|
$display("Selecting Wishbone module at time %t", $time);
|
363 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
364 |
|
|
failed <= 1'b0;
|
365 |
|
|
for(i = 0; i < 6; i=i+1) begin
|
366 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h0);
|
367 |
|
|
if(input_data8[0] != i) begin
|
368 |
|
|
failed = 1;
|
369 |
|
|
$display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i, i, input_data8[i]);
|
370 |
|
|
end
|
371 |
|
|
end
|
372 |
|
|
for(i = 0; i < 2; i=i+1) begin
|
373 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h0);
|
374 |
|
|
if(input_data8[0] != i) begin
|
375 |
|
|
failed = 1;
|
376 |
|
|
$display("W6W6 data mismatch reading WB data at index %d, wrote 0x%x, read 0x%x", i+6, i, input_data8[i]);
|
377 |
|
|
end
|
378 |
|
|
end
|
379 |
|
|
if(!failed) $display("W6W6: 8 WB bytes OK!");
|
380 |
|
|
|
381 |
|
|
|
382 |
|
|
//////////////////////////////////////////
|
383 |
|
|
// Verify behavior of WB UART 16450-style registers
|
384 |
|
|
|
385 |
|
|
// Check LSR with both FIFOs empty
|
386 |
|
|
$display("-------------------------------------------");
|
387 |
|
|
$display("--- Test 6a: Check LSR with both FIFOs empty");
|
388 |
|
|
|
389 |
|
|
$display("Selecting Wishbone module at time %t", $time);
|
390 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
391 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h5);
|
392 |
|
|
if(input_data8[0] != 8'h60) begin
|
393 |
|
|
$display("LSR mismatch with both FIFOs empty, read 0x%x, expected 0x60", input_data8[0]);
|
394 |
|
|
end
|
395 |
|
|
else $display("LSR with both FIFOs empty OK!");
|
396 |
|
|
|
397 |
|
|
$display("-------------------------------------------");
|
398 |
|
|
$display("--- Test 6b: Check LSR with WB read data available");
|
399 |
|
|
|
400 |
|
|
#1000
|
401 |
|
|
$display("Selecting JSP module at time %t", $time);
|
402 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
403 |
|
|
$display("JTAG putting 1 at time %t", $time);
|
404 |
|
|
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
|
405 |
|
|
|
406 |
|
|
$display("Selecting Wishbone module at time %t", $time);
|
407 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
408 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h5);
|
409 |
|
|
if(input_data8[0] != 8'h61) begin
|
410 |
|
|
$display("LSR mismatch with WB read data available, read 0x%x, expected 0x61", input_data8[0]);
|
411 |
|
|
end
|
412 |
|
|
else $display("LSR with WB read data available OK!");
|
413 |
|
|
|
414 |
|
|
$display("-------------------------------------------");
|
415 |
|
|
$display("--- Test 6c: Check LSR with WB read data available and write FIFO not empty / full");
|
416 |
|
|
|
417 |
|
|
#1000
|
418 |
|
|
$display("Selecting Wishbone module at time %t", $time);
|
419 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
420 |
|
|
$display("WB putting 1 bytes to JSP module for LSR test at time %t", $time);
|
421 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h0);
|
422 |
|
|
|
423 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h5);
|
424 |
|
|
if(input_data8[0] != 8'h61) begin
|
425 |
|
|
$display("LSR mismatch with WB read data available and write FIFO not empty, read 0x%x, expected 0x61", input_data8[0]);
|
426 |
|
|
end
|
427 |
|
|
else $display("LSR with WB read data available and write FIFO not empty OK!");
|
428 |
|
|
|
429 |
|
|
// Fill the write FIFO
|
430 |
|
|
for(i = 0; i < 7; i = i + 1) begin
|
431 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h0);
|
432 |
|
|
end
|
433 |
|
|
|
434 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h5);
|
435 |
|
|
if(input_data8[0] != 8'h01) begin
|
436 |
|
|
$display("LSR mismatch with WB read data available and write FIFO full, read 0x%x, expected 0x01", input_data8[0]);
|
437 |
|
|
end
|
438 |
|
|
else $display("LSR with WB read data available and write FIFO full OK!");
|
439 |
|
|
|
440 |
|
|
$display("-------------------------------------------");
|
441 |
|
|
$display("--- Test 6d: Check LSR with write FIFO full");
|
442 |
|
|
|
443 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h0); // get/clear the read data
|
444 |
|
|
|
445 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h5);
|
446 |
|
|
if(input_data8[0] != 8'h00) begin
|
447 |
|
|
$display("LSR mismatch with WB write FIFO full, read 0x%x, expected 0x00", input_data8[0]);
|
448 |
|
|
end
|
449 |
|
|
else $display("LSR with WB write FIFO full OK!");
|
450 |
|
|
|
451 |
|
|
//////////////////////////////////////
|
452 |
|
|
// Test DLAB bit
|
453 |
|
|
// Now that we've tested the LSR, we can use it to verity the FIFO states
|
454 |
|
|
|
455 |
|
|
$display("-------------------------------------------");
|
456 |
|
|
$display("--- Test 7: test DLAB bit");
|
457 |
|
|
|
458 |
|
|
#1000
|
459 |
|
|
$display("Selecting JSP module at time %t", $time);
|
460 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
461 |
|
|
$display("JTAG putting 1 (and getting 8) at time %t", $time);
|
462 |
|
|
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
|
463 |
|
|
|
464 |
|
|
// Set the DLAB bit. This should prevent reads/writes to the FIFOs from the WB
|
465 |
|
|
#1000
|
466 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
467 |
|
|
|
468 |
|
|
#1000
|
469 |
|
|
$display("Setting DLAB bit it time %t", $time);
|
470 |
|
|
static_data8[0] = 8'h80;
|
471 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h00000003);
|
472 |
|
|
|
473 |
|
|
// Read from 0. This should not get the available byte.
|
474 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h0);
|
475 |
|
|
|
476 |
|
|
// Try to write the FIFO full. This should not put any bytes to the transmit FIFO
|
477 |
|
|
for(i = 0; i < 8; i = i + 1) begin
|
478 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h0);
|
479 |
|
|
end
|
480 |
|
|
|
481 |
|
|
// Check FIFO status in the LSR
|
482 |
|
|
$display("Checking LSR");
|
483 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h5);
|
484 |
|
|
if(input_data8[0] != 8'h61) begin
|
485 |
|
|
$display("LSR mismatch in DLAB inhibit test, read 0x%x, expected 0x61", input_data8[0]);
|
486 |
|
|
end
|
487 |
|
|
else $display("DLAB inhibit test OK!");
|
488 |
|
|
|
489 |
|
|
// Now clear the DLAB, and try again.
|
490 |
|
|
$display("Clearing DLAB at time %t", $time);
|
491 |
|
|
static_data8[0] = 8'h00;
|
492 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h3);
|
493 |
|
|
|
494 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h0); // Should empty the read FIFO
|
495 |
|
|
for(i = 0; i < 8; i = i + 1) begin
|
496 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h0); // Should un-empty the read FIFO
|
497 |
|
|
end
|
498 |
|
|
|
499 |
|
|
// Check FIFO status in the LSR
|
500 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h5);
|
501 |
|
|
if(input_data8[0] != 8'h00) begin
|
502 |
|
|
$display("LSR mismatch in DLAB test 2, read 0x%x, expected 0x00", input_data8[0]);
|
503 |
|
|
end
|
504 |
|
|
else $display("DLAB un-inhibit test OK!");
|
505 |
|
|
|
506 |
|
|
// Note WB write FIFO is full at this point
|
507 |
|
|
|
508 |
|
|
///////////////////////////////////////////////////
|
509 |
|
|
// Test interrupt functionality.
|
510 |
|
|
|
511 |
|
|
$display("-------------------------------------------");
|
512 |
|
|
$display("--- Test 8a: IER write");
|
513 |
|
|
|
514 |
|
|
// Write IER to 0
|
515 |
|
|
static_data8[0] = 8'h00;
|
516 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h1);
|
517 |
|
|
|
518 |
|
|
// Make sure it's 0
|
519 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h1);
|
520 |
|
|
if(input_data8[0] != 8'h00) begin
|
521 |
|
|
$display("Failed to set IER to 0x00, read 0x%x", input_data8[0]);
|
522 |
|
|
end
|
523 |
|
|
else $display("Set IER to 0: pass");
|
524 |
|
|
|
525 |
|
|
// Make sure int_o is not set
|
526 |
|
|
if(jsp_int) begin
|
527 |
|
|
$display("JSP Interrupt set when no interrupts enabled: FAIL");
|
528 |
|
|
end
|
529 |
|
|
else $display("JSP interrupt not set, interrupts disabled: OK");
|
530 |
|
|
|
531 |
|
|
// Write IER to 0x0F
|
532 |
|
|
static_data8[0] = 8'h0F;
|
533 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h1);
|
534 |
|
|
|
535 |
|
|
// Make sure it's 0x0F
|
536 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h1);
|
537 |
|
|
if(input_data8[0] != 8'h0F) begin
|
538 |
|
|
$display("Failed to set IER to 0x0F, read 0x%x", input_data8[0]);
|
539 |
|
|
end
|
540 |
|
|
else $display("Set IER to 0x0F: pass");
|
541 |
|
|
|
542 |
|
|
|
543 |
|
|
// Write IER to 0x03
|
544 |
|
|
static_data8[0] = 8'h03;
|
545 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h1);
|
546 |
|
|
|
547 |
|
|
// Make sure it's 0x03
|
548 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h1);
|
549 |
|
|
if(input_data8[0] != 8'h03) begin
|
550 |
|
|
$display("Failed to set IER to 0x03, read 0x%x", input_data8[0]);
|
551 |
|
|
end
|
552 |
|
|
else $display("Set IER to 0x03: pass");
|
553 |
|
|
|
554 |
|
|
////////////////////////////////////
|
555 |
|
|
// Test the int_o output
|
556 |
|
|
|
557 |
|
|
$display("-------------------------------------------");
|
558 |
|
|
$display("--- Test 8b: int_o output");
|
559 |
|
|
|
560 |
|
|
// Make sure int_o is (still) not set WB RD FIFO empty, WB WR FIFO is full
|
561 |
|
|
if(jsp_int) begin
|
562 |
|
|
$display("JSP Interrupt set when no int condition: FAIL");
|
563 |
|
|
end
|
564 |
|
|
else $display("JSP interrupt not set, no INT condition: OK");
|
565 |
|
|
|
566 |
|
|
// Check IIR for 'no active interrupt'
|
567 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h2);
|
568 |
|
|
if(input_data8[0] != 8'h01) begin
|
569 |
|
|
$display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x01", input_data8[0]);
|
570 |
|
|
end
|
571 |
|
|
else $display("IIR is 0x01 with no active interrupt: pass");
|
572 |
|
|
|
573 |
|
|
|
574 |
|
|
// Read a byte from the JSP, should trigger the 'THR empty' interrupt
|
575 |
|
|
#1000
|
576 |
|
|
$display("Selecting JSP module at time %t", $time);
|
577 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
578 |
|
|
$display("JTAG getting 8 at time %t", $time);
|
579 |
|
|
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
|
580 |
|
|
|
581 |
|
|
|
582 |
|
|
// Make sure int_o is (still) not set WB RD FIFO empty, WB WR FIFO is full
|
583 |
|
|
if(!jsp_int) begin
|
584 |
|
|
$display("JSP Interrupt not set when THR empty: FAIL");
|
585 |
|
|
end
|
586 |
|
|
else $display("JSP interrupt set for THR empty: OK");
|
587 |
|
|
|
588 |
|
|
#1000
|
589 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
590 |
|
|
|
591 |
|
|
// Check IIR for THR empty
|
592 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h2);
|
593 |
|
|
if(input_data8[0] != 8'h02) begin
|
594 |
|
|
$display("Wrong value for IIR with no active interrupt, read 0x%x, expected 0x02", input_data8[0]);
|
595 |
|
|
end
|
596 |
|
|
else $display("IIR is 0x02 with THR empty: pass");
|
597 |
|
|
|
598 |
|
|
// IIR read should have cleared int_o and changed IIR to 'no active interrupt'
|
599 |
|
|
if(jsp_int) begin
|
600 |
|
|
$display("JSP Interrupt set after IIR read: FAIL");
|
601 |
|
|
end
|
602 |
|
|
else $display("JSP interrupt not set after clearing THR INT with IIR read: OK");
|
603 |
|
|
|
604 |
|
|
// Check IIR for 'no active interrupt'
|
605 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h2);
|
606 |
|
|
if(input_data8[0] != 8'h01) begin
|
607 |
|
|
$display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
|
608 |
|
|
end
|
609 |
|
|
else $display("IIR is 0x01 after clearing THR INT with IIR read: pass");
|
610 |
|
|
|
611 |
|
|
// Write a byte from the WB, should trigger int_o
|
612 |
|
|
static_data8[0] = 8'h00;
|
613 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h0);
|
614 |
|
|
|
615 |
|
|
// check int_o, should be set
|
616 |
|
|
if(!jsp_int) begin
|
617 |
|
|
$display("JSP Interrupt not set when THR not full: FAIL");
|
618 |
|
|
end
|
619 |
|
|
else $display("JSP interrupt set for THR not full: OK");
|
620 |
|
|
|
621 |
|
|
// Write a byte from the JSP, should take precedence in IIR
|
622 |
|
|
#1000
|
623 |
|
|
$display("Selecting JSP module at time %t", $time);
|
624 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
625 |
|
|
$display("JTAG putting 1 at time %t", $time);
|
626 |
|
|
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
|
627 |
|
|
|
628 |
|
|
// check int_o, should be set
|
629 |
|
|
if(!jsp_int) begin
|
630 |
|
|
$display("JSP Interrupt not set when read data available: FAIL");
|
631 |
|
|
end
|
632 |
|
|
else $display("JSP interrupt set for read data available: OK");
|
633 |
|
|
|
634 |
|
|
// Check IIR, should show read data available
|
635 |
|
|
#1000
|
636 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
637 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h2);
|
638 |
|
|
if(input_data8[0] != 8'h4) begin
|
639 |
|
|
$display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x04", input_data8[0]);
|
640 |
|
|
end
|
641 |
|
|
else $display("IIR is 0x04 after putting a JSP byte: pass");
|
642 |
|
|
|
643 |
|
|
// Read the byte from the WB.
|
644 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h0);
|
645 |
|
|
|
646 |
|
|
// check int_o, should be set
|
647 |
|
|
if(!jsp_int) begin
|
648 |
|
|
$display("JSP Interrupt not set when THR not full: FAIL");
|
649 |
|
|
end
|
650 |
|
|
else $display("JSP interrupt set for THR not full: OK");
|
651 |
|
|
|
652 |
|
|
// Check IIR, should show THRE
|
653 |
|
|
#1000
|
654 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h2);
|
655 |
|
|
if(input_data8[0] != 8'h02) begin
|
656 |
|
|
$display("Wrong value for IIR after clearing RDA INT with WB read (THRE), read 0x%x, expected 0x02", input_data8[0]);
|
657 |
|
|
end
|
658 |
|
|
else $display("IIR is 0x02 after reading data with THRE: pass");
|
659 |
|
|
|
660 |
|
|
// check int_o, should be cleared
|
661 |
|
|
if(jsp_int) begin
|
662 |
|
|
$display("JSP Interrupt set after clearing THRE with IIR read: FAIL");
|
663 |
|
|
end
|
664 |
|
|
else $display("JSP interrupt not set, THRE cleared with IIR read: OK");
|
665 |
|
|
|
666 |
|
|
// Check IIR, should no no interrupt
|
667 |
|
|
#1000
|
668 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h2);
|
669 |
|
|
if(input_data8[0] != 8'h01) begin
|
670 |
|
|
$display("Wrong value for IIR after clearing THR INT with IIR read, read 0x%x, expected 0x01", input_data8[0]);
|
671 |
|
|
end
|
672 |
|
|
else $display("IIR is 0x01 after reading data with THRE: pass");
|
673 |
|
|
|
674 |
|
|
// Put a byte from the JSP
|
675 |
|
|
#1000
|
676 |
|
|
$display("Selecting JSP module at time %t", $time);
|
677 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
678 |
|
|
$display("JTAG putting 1 at time %t", $time);
|
679 |
|
|
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
|
680 |
|
|
|
681 |
|
|
|
682 |
|
|
// check int_o, should be set
|
683 |
|
|
if(!jsp_int) begin
|
684 |
|
|
$display("JSP Interrupt not set when read data available: FAIL");
|
685 |
|
|
end
|
686 |
|
|
else $display("JSP interrupt set for read data available: OK");
|
687 |
|
|
|
688 |
|
|
// check IIR, should show receive data available
|
689 |
|
|
#1000
|
690 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
691 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h2);
|
692 |
|
|
if(input_data8[0] != 8'h4) begin
|
693 |
|
|
$display("Wrong value for IIR with RDA, read 0x%x, expected 0x04", input_data8[0]);
|
694 |
|
|
end
|
695 |
|
|
else $display("IIR is 0x04 after putting a JSP byte: pass");
|
696 |
|
|
|
697 |
|
|
// Read the byte over WB
|
698 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h0);
|
699 |
|
|
|
700 |
|
|
|
701 |
|
|
// check int_o, should be cleared
|
702 |
|
|
if(jsp_int) begin
|
703 |
|
|
$display("JSP Interrupt set when no int condition: FAIL");
|
704 |
|
|
end
|
705 |
|
|
else $display("JSP interrupt not set, no INT condition: OK");
|
706 |
|
|
|
707 |
|
|
// check IIR, should show no active interrupt
|
708 |
|
|
#1000
|
709 |
|
|
do_module_burst_read(3'h1, 16'd1, 32'h2);
|
710 |
|
|
if(input_data8[0] != 8'h1) begin
|
711 |
|
|
$display("Wrong value for IIR with no active int, read 0x%x, expected 0x01", input_data8[0]);
|
712 |
|
|
end
|
713 |
|
|
else $display("IIR is 0x01 with no active interrupts: pass");
|
714 |
|
|
|
715 |
|
|
////////////////////////////////////
|
716 |
|
|
// Test the software resets
|
717 |
|
|
|
718 |
|
|
$display("-------------------------------------------");
|
719 |
|
|
$display("--- Test 9: Software WB/UART FIFO reset");
|
720 |
|
|
|
721 |
|
|
// First, test reset only JSP->WB FIFO
|
722 |
|
|
// Put a byte from the JSP
|
723 |
|
|
#1000
|
724 |
|
|
//$display("Selecting JSP module at time %t", $time);
|
725 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
726 |
|
|
//$display("JTAG putting 1 at time %t", $time);
|
727 |
|
|
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
|
728 |
|
|
|
729 |
|
|
// Put a byte from the WB
|
730 |
|
|
#1000
|
731 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
732 |
|
|
#500
|
733 |
|
|
static_data8[0] = 8'h00;
|
734 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h0);
|
735 |
|
|
|
736 |
|
|
// Reset the JSP->WB FIFO
|
737 |
|
|
#500
|
738 |
|
|
static_data8[0] = 8'h02;
|
739 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h2);
|
740 |
|
|
|
741 |
|
|
// To test, need to read the output from the transact function:
|
742 |
|
|
// Should be 1 byte available, 8 bytes free
|
743 |
|
|
#1000
|
744 |
|
|
//$display("Selecting JSP module at time %t", $time);
|
745 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
746 |
|
|
$display("Next line should show 1 byte available, 8 bytes free:");
|
747 |
|
|
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
|
748 |
|
|
|
749 |
|
|
|
750 |
|
|
// Second, test reset only WB->JSP FIFO
|
751 |
|
|
// Put a byte from the JSP
|
752 |
|
|
#1000
|
753 |
|
|
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
|
754 |
|
|
|
755 |
|
|
// Put a byte from the WB
|
756 |
|
|
#1000
|
757 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
758 |
|
|
#500
|
759 |
|
|
static_data8[0] = 8'h00;
|
760 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h0);
|
761 |
|
|
|
762 |
|
|
// Reset the WB->JSP FIFO
|
763 |
|
|
#500
|
764 |
|
|
static_data8[0] = 8'h04;
|
765 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h2);
|
766 |
|
|
|
767 |
|
|
// To test, need to read the output from the transact function:
|
768 |
|
|
// Should be 0 byte available, 7 bytes free
|
769 |
|
|
#1000
|
770 |
|
|
//$display("Selecting JSP module at time %t", $time);
|
771 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
772 |
|
|
$display("Next line should show 0 byte available, 7 bytes free:");
|
773 |
|
|
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
|
774 |
|
|
|
775 |
|
|
// Finally, test reset both directions
|
776 |
|
|
// Put a byte from the JSP
|
777 |
|
|
#1000
|
778 |
|
|
do_jsp_read_write(4'h1,jsp_data8); // 4 bits words to write, 64 bits output data
|
779 |
|
|
|
780 |
|
|
// Put a byte from the WB
|
781 |
|
|
#1000
|
782 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
783 |
|
|
#500
|
784 |
|
|
static_data8[0] = 8'h00;
|
785 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h0);
|
786 |
|
|
|
787 |
|
|
// Reset both FIFO
|
788 |
|
|
#500
|
789 |
|
|
static_data8[0] = 8'h06;
|
790 |
|
|
do_module_burst_write(3'h1, 16'd1, 32'h2);
|
791 |
|
|
|
792 |
|
|
// To test, need to read the output from the transact function:
|
793 |
|
|
// Should be 0 byte available, 8 bytes free
|
794 |
|
|
#1000
|
795 |
|
|
//$display("Selecting JSP module at time %t", $time);
|
796 |
|
|
select_debug_module(`DBG_TOP_JSP_DEBUG_MODULE);
|
797 |
|
|
$display("Next line should show 0 byte available, 8 bytes free:");
|
798 |
|
|
do_jsp_read_write(4'h0,jsp_data8); // 4 bits words to write, 64 bits output data
|
799 |
|
|
|
800 |
|
|
//////////////////////////////
|
801 |
|
|
// End of tests
|
802 |
|
|
|
803 |
|
|
$display("----------------------------------");
|
804 |
|
|
$display("--- ALL TESTS COMPLETE ---");
|
805 |
|
|
|
806 |
|
|
end
|
807 |
|
|
|
808 |
|
|
task initialize_memory;
|
809 |
|
|
input [31:0] start_addr;
|
810 |
|
|
input [31:0] length;
|
811 |
|
|
integer i;
|
812 |
|
|
reg [31:0] addr;
|
813 |
|
|
begin
|
814 |
|
|
|
815 |
|
|
jsp_data8 <= 64'h0706050403020100;
|
816 |
|
|
|
817 |
|
|
for (i=0; i<length; i=i+1)
|
818 |
|
|
begin
|
819 |
|
|
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
|
820 |
|
|
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
|
821 |
|
|
static_data8[i] <= i[7:0];
|
822 |
|
|
end
|
823 |
|
|
end
|
824 |
|
|
endtask
|
825 |
|
|
|
826 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
827 |
|
|
// Declaration and interconnection of components
|
828 |
|
|
|
829 |
|
|
// Top module
|
830 |
|
|
tap_top i_tap (
|
831 |
|
|
// JTAG pads
|
832 |
|
|
.tms_pad_i(jtag_tms_o),
|
833 |
|
|
.tck_pad_i(jtag_tck_o),
|
834 |
|
|
.trstn_pad_i(1'b1),
|
835 |
|
|
.tdi_pad_i(jtag_tdo_o),
|
836 |
|
|
.tdo_pad_o(jtag_tdi_i),
|
837 |
|
|
.tdo_padoe_o(),
|
838 |
|
|
|
839 |
|
|
// TAP states
|
840 |
|
|
.test_logic_reset_o(dbg_rst),
|
841 |
|
|
.run_test_idle_o(),
|
842 |
|
|
.shift_dr_o(shift_dr),
|
843 |
|
|
.pause_dr_o(pause_dr),
|
844 |
|
|
.update_dr_o(update_dr),
|
845 |
|
|
.capture_dr_o(capture_dr),
|
846 |
|
|
|
847 |
|
|
// Select signals for boundary scan or mbist
|
848 |
|
|
.extest_select_o(),
|
849 |
|
|
.sample_preload_select_o(),
|
850 |
|
|
.mbist_select_o(),
|
851 |
|
|
.debug_select_o(dbg_sel),
|
852 |
|
|
|
853 |
|
|
// TDO signal that is connected to TDI of sub-modules.
|
854 |
|
|
.tdi_o(dbg_tdo),
|
855 |
|
|
|
856 |
|
|
// TDI signals from sub-modules
|
857 |
|
|
.debug_tdo_i(dbg_tdi), // from debug module
|
858 |
|
|
.bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
|
859 |
|
|
.mbist_tdo_i(1'b0) // from Mbist Chain
|
860 |
|
|
);
|
861 |
|
|
|
862 |
|
|
|
863 |
|
|
// Top module
|
864 |
|
|
adbg_top i_dbg_module(
|
865 |
|
|
// JTAG signals
|
866 |
|
|
.tck_i(jtag_tck_o),
|
867 |
|
|
.tdi_i(dbg_tdo),
|
868 |
|
|
.tdo_o(dbg_tdi),
|
869 |
|
|
.rst_i(dbg_rst),
|
870 |
|
|
|
871 |
|
|
// TAP states
|
872 |
|
|
.shift_dr_i(shift_dr),
|
873 |
|
|
.pause_dr_i(pause_dr),
|
874 |
|
|
.update_dr_i(update_dr),
|
875 |
|
|
.capture_dr_i(capture_dr),
|
876 |
|
|
|
877 |
|
|
// Instructions
|
878 |
|
|
.debug_select_i(dbg_sel)
|
879 |
|
|
|
880 |
|
|
|
881 |
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
882 |
|
|
// WISHBONE common signals
|
883 |
|
|
,
|
884 |
|
|
.wb_clk_i(wb_clk_i),
|
885 |
|
|
.wb_rst_i(wb_rst_i),
|
886 |
|
|
|
887 |
|
|
// WISHBONE master interface
|
888 |
|
|
.wb_adr_o(wb_adr),
|
889 |
|
|
.wb_dat_o(wb_dat_m),
|
890 |
|
|
.wb_dat_i(wb_dat_s),
|
891 |
|
|
.wb_cyc_o(wb_cyc),
|
892 |
|
|
.wb_stb_o(wb_stb),
|
893 |
|
|
.wb_sel_o(wb_sel),
|
894 |
|
|
.wb_we_o(wb_we),
|
895 |
|
|
.wb_ack_i(wb_ack),
|
896 |
|
|
.wb_cab_o(),
|
897 |
|
|
.wb_err_i(wb_err),
|
898 |
|
|
.wb_cti_o(),
|
899 |
|
|
.wb_bte_o()
|
900 |
|
|
`endif
|
901 |
|
|
|
902 |
|
|
`ifdef DBG_JSP_SUPPORTED
|
903 |
|
|
// WISHBONE slave, including interrupt output
|
904 |
|
|
,
|
905 |
|
|
.wb_jsp_adr_i(wb_adr),
|
906 |
|
|
.wb_jsp_dat_o(wb_dat_s),
|
907 |
|
|
.wb_jsp_dat_i(wb_dat_m),
|
908 |
|
|
.wb_jsp_cyc_i(wb_cyc),
|
909 |
|
|
.wb_jsp_stb_i(wb_stb),
|
910 |
|
|
.wb_jsp_sel_i(wb_sel),
|
911 |
|
|
.wb_jsp_we_i(wb_we),
|
912 |
|
|
.wb_jsp_ack_o(wb_ack),
|
913 |
|
|
.wb_jsp_cab_i(),
|
914 |
|
|
.wb_jsp_err_o(wb_err),
|
915 |
|
|
.wb_jsp_cti_i(),
|
916 |
|
|
.wb_jsp_bte_i(),
|
917 |
|
|
.int_o(jsp_int)
|
918 |
|
|
`endif
|
919 |
|
|
|
920 |
|
|
);
|
921 |
|
|
|
922 |
|
|
|
923 |
|
|
|
924 |
|
|
///////////////////////////////////////////////////////////////////////////
|
925 |
|
|
// Higher-level chain manipulation functions
|
926 |
|
|
|
927 |
|
|
// calculate the CRC, up to 32 bits at a time
|
928 |
|
|
task compute_crc;
|
929 |
|
|
input [31:0] crc_in;
|
930 |
|
|
input [31:0] data_in;
|
931 |
|
|
input [5:0] length_bits;
|
932 |
|
|
output [31:0] crc_out;
|
933 |
|
|
integer i;
|
934 |
|
|
reg [31:0] d;
|
935 |
|
|
reg [31:0] c;
|
936 |
|
|
begin
|
937 |
|
|
crc_out = crc_in;
|
938 |
|
|
for(i = 0; i < length_bits; i = i+1) begin
|
939 |
|
|
d = (data_in[i]) ? 32'hffffffff : 32'h0;
|
940 |
|
|
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
|
941 |
|
|
//crc_out = {crc_out[30:0], 1'b0}; // original
|
942 |
|
|
crc_out = crc_out >> 1;
|
943 |
|
|
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
|
944 |
|
|
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
|
945 |
|
|
end
|
946 |
|
|
end
|
947 |
|
|
endtask
|
948 |
|
|
|
949 |
|
|
task check_idcode;
|
950 |
|
|
reg [63:0] readdata;
|
951 |
|
|
reg[31:0] idcode;
|
952 |
|
|
begin
|
953 |
|
|
set_ir(`IDCODE);
|
954 |
|
|
|
955 |
|
|
// Read the IDCODE in the DR
|
956 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
957 |
|
|
write_bit(3'h0); // capture_ir
|
958 |
|
|
write_bit(3'h0); // shift_ir
|
959 |
|
|
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
|
960 |
|
|
write_bit(`JTAG_TMS_bit); // update_ir
|
961 |
|
|
write_bit(3'h0); // idle
|
962 |
|
|
idcode = readdata[31:0];
|
963 |
|
|
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
|
964 |
|
|
end
|
965 |
|
|
endtask;
|
966 |
|
|
|
967 |
|
|
task select_debug_module;
|
968 |
|
|
input [1:0] moduleid;
|
969 |
|
|
reg validid;
|
970 |
|
|
begin
|
971 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
972 |
|
|
write_bit(3'h0); // capture_ir
|
973 |
|
|
write_bit(3'h0); // shift_ir
|
974 |
|
|
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
|
975 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
976 |
|
|
write_bit(3'h0); // idle
|
977 |
|
|
|
978 |
|
|
$display("Selecting module (%0x)", moduleid);
|
979 |
|
|
|
980 |
|
|
end
|
981 |
|
|
endtask
|
982 |
|
|
|
983 |
|
|
|
984 |
|
|
task send_module_burst_command;
|
985 |
|
|
input [3:0] opcode;
|
986 |
|
|
input [31:0] address;
|
987 |
|
|
input [15:0] burstlength;
|
988 |
|
|
reg [63:0] streamdata;
|
989 |
|
|
begin
|
990 |
|
|
streamdata = {11'h0,1'b0,opcode,address,burstlength};
|
991 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
992 |
|
|
write_bit(3'h0); // capture_ir
|
993 |
|
|
write_bit(3'h0); // shift_ir
|
994 |
|
|
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
|
995 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
996 |
|
|
write_bit(3'h0); // idle
|
997 |
|
|
end
|
998 |
|
|
endtask
|
999 |
|
|
|
1000 |
|
|
task select_module_internal_register; // Really just a read, with discarded data
|
1001 |
|
|
input [31:0] regidx;
|
1002 |
|
|
input [7:0] len; // the length of the register index data, we assume not more than 32
|
1003 |
|
|
reg[63:0] streamdata;
|
1004 |
|
|
begin
|
1005 |
|
|
streamdata = 64'h0;
|
1006 |
|
|
streamdata = streamdata | regidx;
|
1007 |
|
|
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
|
1008 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
1009 |
|
|
write_bit(3'h0); // capture_ir
|
1010 |
|
|
write_bit(3'h0); // shift_ir
|
1011 |
|
|
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
|
1012 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
1013 |
|
|
write_bit(3'h0); // idle
|
1014 |
|
|
end
|
1015 |
|
|
endtask
|
1016 |
|
|
|
1017 |
|
|
|
1018 |
|
|
task read_module_internal_register; // We assume the register is already selected
|
1019 |
|
|
//input [31:0] regidx;
|
1020 |
|
|
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
|
1021 |
|
|
output [63:0] instream;
|
1022 |
|
|
reg [63:0] bitmask;
|
1023 |
|
|
begin
|
1024 |
|
|
instream = 64'h0;
|
1025 |
|
|
// We shift out all 0's, which is a NOP to the debug unit
|
1026 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
1027 |
|
|
write_bit(3'h0); // capture_ir
|
1028 |
|
|
write_bit(3'h0); // shift_ir
|
1029 |
|
|
// Shift at least 5 bits, as this is the min, for a valid NOP
|
1030 |
|
|
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
|
1031 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
1032 |
|
|
write_bit(3'h0); // idle
|
1033 |
|
|
bitmask = 64'hffffffffffffffff;
|
1034 |
|
|
bitmask = bitmask << len;
|
1035 |
|
|
bitmask = ~bitmask;
|
1036 |
|
|
instream = instream & bitmask; // Cut off any unwanted excess bits
|
1037 |
|
|
end
|
1038 |
|
|
endtask
|
1039 |
|
|
|
1040 |
|
|
task write_module_internal_register;
|
1041 |
|
|
input [31:0] regidx; // the length of the register index data
|
1042 |
|
|
input [7:0] idxlen;
|
1043 |
|
|
input [63:0] writedata;
|
1044 |
|
|
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
|
1045 |
|
|
reg[63:0] streamdata;
|
1046 |
|
|
begin
|
1047 |
|
|
streamdata = 64'h0; // This will 0 the toplevel/module select bit
|
1048 |
|
|
streamdata = streamdata | writedata;
|
1049 |
|
|
streamdata = streamdata | (regidx << datalen);
|
1050 |
|
|
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
|
1051 |
|
|
|
1052 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
1053 |
|
|
write_bit(3'h0); // capture_ir
|
1054 |
|
|
write_bit(3'h0); // shift_ir
|
1055 |
|
|
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
|
1056 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
1057 |
|
|
write_bit(3'h0); // idle
|
1058 |
|
|
end
|
1059 |
|
|
endtask
|
1060 |
|
|
|
1061 |
|
|
// This includes the sending of the burst command
|
1062 |
|
|
task do_module_burst_read;
|
1063 |
|
|
input [5:0] word_size_bytes;
|
1064 |
|
|
input [15:0] word_count;
|
1065 |
|
|
input [31:0] start_address;
|
1066 |
|
|
reg [3:0] opcode;
|
1067 |
|
|
reg status;
|
1068 |
|
|
reg [63:0] instream;
|
1069 |
|
|
integer i;
|
1070 |
|
|
integer j;
|
1071 |
|
|
reg [31:0] crc_calc_i;
|
1072 |
|
|
reg [31:0] crc_calc_o; // temp signal...
|
1073 |
|
|
reg [31:0] crc_read;
|
1074 |
|
|
reg [5:0] word_size_bits;
|
1075 |
|
|
begin
|
1076 |
|
|
//$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
|
1077 |
|
|
instream = 64'h0;
|
1078 |
|
|
word_size_bits = word_size_bytes << 3;
|
1079 |
|
|
crc_calc_i = 32'hffffffff;
|
1080 |
|
|
|
1081 |
|
|
// Send the command
|
1082 |
|
|
case (word_size_bytes)
|
1083 |
|
|
3'h1: opcode = `DBG_WB_CMD_BREAD8;
|
1084 |
|
|
3'h2: opcode = `DBG_WB_CMD_BREAD16;
|
1085 |
|
|
3'h4: opcode = `DBG_WB_CMD_BREAD32;
|
1086 |
|
|
default:
|
1087 |
|
|
begin
|
1088 |
|
|
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
1089 |
|
|
opcode = `DBG_WB_CMD_BREAD32;
|
1090 |
|
|
end
|
1091 |
|
|
endcase
|
1092 |
|
|
|
1093 |
|
|
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
|
1094 |
|
|
|
1095 |
|
|
// Get us back to shift_dr mode to read a burst
|
1096 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
1097 |
|
|
write_bit(3'h0); // capture_ir
|
1098 |
|
|
write_bit(3'h0); // shift_ir
|
1099 |
|
|
|
1100 |
|
|
`ifdef ADBG_USE_HISPEED
|
1101 |
|
|
// Get 1 status bit, then word_size_bytes*8 bits
|
1102 |
|
|
status = 1'b0;
|
1103 |
|
|
j = 0;
|
1104 |
|
|
while(!status) begin
|
1105 |
|
|
read_write_bit(3'h0, status);
|
1106 |
|
|
j = j + 1;
|
1107 |
|
|
end
|
1108 |
|
|
|
1109 |
|
|
//if(j > 1) begin
|
1110 |
|
|
// $display("Took %0d tries before good status bit during burst read", j);
|
1111 |
|
|
//end
|
1112 |
|
|
`endif
|
1113 |
|
|
|
1114 |
|
|
// Now, repeat...
|
1115 |
|
|
for(i = 0; i < word_count; i=i+1) begin
|
1116 |
|
|
|
1117 |
|
|
`ifndef ADBG_USE_HISPEED
|
1118 |
|
|
// Get 1 status bit, then word_size_bytes*8 bits
|
1119 |
|
|
status = 1'b0;
|
1120 |
|
|
j = 0;
|
1121 |
|
|
while(!status) begin
|
1122 |
|
|
read_write_bit(3'h0, status);
|
1123 |
|
|
j = j + 1;
|
1124 |
|
|
end
|
1125 |
|
|
|
1126 |
|
|
//if(j > 1) begin
|
1127 |
|
|
// $display("Took %0d tries before good status bit during burst read", j);
|
1128 |
|
|
//end
|
1129 |
|
|
`endif
|
1130 |
|
|
|
1131 |
|
|
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
|
1132 |
|
|
//$display("Read 0x%0x", instream[31:0]);
|
1133 |
|
|
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
|
1134 |
|
|
crc_calc_i = crc_calc_o;
|
1135 |
|
|
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
|
1136 |
|
|
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
|
1137 |
|
|
else input_data32[i] = instream[31:0];
|
1138 |
|
|
end
|
1139 |
|
|
|
1140 |
|
|
// Read the data CRC from the debug module.
|
1141 |
|
|
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
|
1142 |
|
|
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
|
1143 |
|
|
//else $display("CRC OK!");
|
1144 |
|
|
|
1145 |
|
|
// Finally, shift out 5 0's, to make the next command a NOP
|
1146 |
|
|
// Not necessary, debug unit won't latch a new opcode at the end of a burst
|
1147 |
|
|
//jtag_write_stream(64'h0, 8'h5, 1);
|
1148 |
|
|
write_bit(`JTAG_TMS_bit); // update_ir
|
1149 |
|
|
write_bit(3'h0); // idle
|
1150 |
|
|
end
|
1151 |
|
|
endtask
|
1152 |
|
|
|
1153 |
|
|
|
1154 |
|
|
task do_module_burst_write;
|
1155 |
|
|
input [5:0] word_size_bytes;
|
1156 |
|
|
input [15:0] word_count;
|
1157 |
|
|
input [31:0] start_address;
|
1158 |
|
|
reg [3:0] opcode;
|
1159 |
|
|
reg status;
|
1160 |
|
|
reg [63:0] dataword;
|
1161 |
|
|
integer i;
|
1162 |
|
|
integer j;
|
1163 |
|
|
reg [31:0] crc_calc_i;
|
1164 |
|
|
reg [31:0] crc_calc_o;
|
1165 |
|
|
reg crc_match;
|
1166 |
|
|
reg [5:0] word_size_bits;
|
1167 |
|
|
begin
|
1168 |
|
|
//$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
|
1169 |
|
|
word_size_bits = word_size_bytes << 3;
|
1170 |
|
|
crc_calc_i = 32'hffffffff;
|
1171 |
|
|
|
1172 |
|
|
// Send the command
|
1173 |
|
|
case (word_size_bytes)
|
1174 |
|
|
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
|
1175 |
|
|
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
|
1176 |
|
|
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
|
1177 |
|
|
default:
|
1178 |
|
|
begin
|
1179 |
|
|
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
1180 |
|
|
opcode = `DBG_WB_CMD_BWRITE32;
|
1181 |
|
|
end
|
1182 |
|
|
endcase
|
1183 |
|
|
|
1184 |
|
|
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
|
1185 |
|
|
|
1186 |
|
|
// Get us back to shift_dr mode to write a burst
|
1187 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
1188 |
|
|
write_bit(3'h0); // capture_ir
|
1189 |
|
|
write_bit(3'h0); // shift_ir
|
1190 |
|
|
|
1191 |
|
|
|
1192 |
|
|
// Write a start bit (a 1) so it knows when to start counting
|
1193 |
|
|
write_bit(`JTAG_TDO_bit);
|
1194 |
|
|
|
1195 |
|
|
// Now, repeat...
|
1196 |
|
|
for(i = 0; i < word_count; i=i+1) begin
|
1197 |
|
|
// Write word_size_bytes*8 bits, then get 1 status bit
|
1198 |
|
|
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
|
1199 |
|
|
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
|
1200 |
|
|
else dataword = {56'h0, static_data8[i]};
|
1201 |
|
|
|
1202 |
|
|
|
1203 |
|
|
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
|
1204 |
|
|
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
|
1205 |
|
|
crc_calc_i = crc_calc_o;
|
1206 |
|
|
|
1207 |
|
|
|
1208 |
|
|
`ifndef ADBG_USE_HISPEED
|
1209 |
|
|
// Check if WB bus is ready
|
1210 |
|
|
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
|
1211 |
|
|
status = 1'b0;
|
1212 |
|
|
read_write_bit(3'h0, status);
|
1213 |
|
|
|
1214 |
|
|
if(!status) begin
|
1215 |
|
|
$display("Bad status bit during burst write, index %d", i);
|
1216 |
|
|
end
|
1217 |
|
|
`endif
|
1218 |
|
|
|
1219 |
|
|
//$display("Wrote 0x%0x", dataword);
|
1220 |
|
|
end
|
1221 |
|
|
|
1222 |
|
|
// Send the CRC we computed
|
1223 |
|
|
jtag_write_stream(crc_calc_o, 6'd32,0);
|
1224 |
|
|
|
1225 |
|
|
// Read the 'CRC match' bit, and go to exit1_dr
|
1226 |
|
|
read_write_bit(`JTAG_TMS_bit, crc_match);
|
1227 |
|
|
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
|
1228 |
|
|
//else $display("CRC OK!");
|
1229 |
|
|
|
1230 |
|
|
// Finally, shift out 5 0's, to make the next command a NOP
|
1231 |
|
|
// Not necessary, module will not latch new opcode during burst
|
1232 |
|
|
//jtag_write_stream(64'h0, 8'h5, 1);
|
1233 |
|
|
write_bit(`JTAG_TMS_bit); // update_ir
|
1234 |
|
|
write_bit(3'h0); // idle
|
1235 |
|
|
end
|
1236 |
|
|
|
1237 |
|
|
endtask
|
1238 |
|
|
|
1239 |
|
|
task do_jsp_read_write;
|
1240 |
|
|
input [3:0] words_to_put;
|
1241 |
|
|
input [63:0] outstream;
|
1242 |
|
|
reg [63:0] instream;
|
1243 |
|
|
integer i;
|
1244 |
|
|
integer j;
|
1245 |
|
|
integer snd;
|
1246 |
|
|
integer rcv;
|
1247 |
|
|
integer xfer_size;
|
1248 |
|
|
reg inbit;
|
1249 |
|
|
// reg shiftbit;
|
1250 |
|
|
begin
|
1251 |
|
|
|
1252 |
|
|
// Put us in shift mode
|
1253 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
1254 |
|
|
write_bit(3'h0); // capture_ir
|
1255 |
|
|
write_bit(3'h0); // shift_ir
|
1256 |
|
|
|
1257 |
|
|
`ifdef ADBG_JSP_SUPPORT_MULTI
|
1258 |
|
|
read_write_bit(`JTAG_TDO_bit,inbit); // Put the start bit
|
1259 |
|
|
`endif
|
1260 |
|
|
|
1261 |
|
|
// Put / get lengths
|
1262 |
|
|
jtag_read_write_stream({56'h0,words_to_put, 4'b0000}, 8'h8,0,instream);
|
1263 |
|
|
|
1264 |
|
|
`ifdef ADBG_JSP_SUPPORT_MULTI
|
1265 |
|
|
//shiftbit = instream[7];
|
1266 |
|
|
instream = (instream << 1);
|
1267 |
|
|
instream[0] = inbit;
|
1268 |
|
|
inbit = instream[8];
|
1269 |
|
|
`endif
|
1270 |
|
|
|
1271 |
|
|
$display("JSP got %d bytes available, %d bytes free", instream[7:4], instream[3:0]);
|
1272 |
|
|
|
1273 |
|
|
// Determine transfer size...
|
1274 |
|
|
rcv = instream[7:4];
|
1275 |
|
|
snd = words_to_put;
|
1276 |
|
|
if(instream[3:0] < words_to_put) snd = instream[3:0];
|
1277 |
|
|
xfer_size = snd;
|
1278 |
|
|
if(rcv > snd) xfer_size = rcv;
|
1279 |
|
|
|
1280 |
|
|
// *** Always do 8 bytes transfers, for testing
|
1281 |
|
|
// xfer_size = 8;
|
1282 |
|
|
// ***
|
1283 |
|
|
|
1284 |
|
|
$display("Doing JSP transfer of %d bytes", xfer_size);
|
1285 |
|
|
|
1286 |
|
|
// Put / get bytes.
|
1287 |
|
|
for(i = 0; i < xfer_size; i=i+1) begin
|
1288 |
|
|
#100
|
1289 |
|
|
jtag_read_write_stream(outstream>>(i*8), 8'h8,0,instream); // Length is in bits...
|
1290 |
|
|
`ifdef ADBG_JSP_SUPPORT_MULTI
|
1291 |
|
|
input_data8[i] = {instream[6:0], inbit};
|
1292 |
|
|
inbit = instream[7];
|
1293 |
|
|
`else
|
1294 |
|
|
input_data8[i] = instream[7:0]; // Move input data to where it can be gotten by main task
|
1295 |
|
|
`endif
|
1296 |
|
|
end
|
1297 |
|
|
|
1298 |
|
|
// JSP does not use the module_inhibit output, so last data bit must be a '0'
|
1299 |
|
|
// Excess writes are ignored. This will however pop a byte from the receive
|
1300 |
|
|
// FIFO, so make sure all data bytes have been fetched before this is sent.
|
1301 |
|
|
write_bit(`JTAG_TMS_bit); // exit_dr
|
1302 |
|
|
|
1303 |
|
|
// Put us back in idle mode
|
1304 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
1305 |
|
|
write_bit(3'h0); // idle
|
1306 |
|
|
|
1307 |
|
|
end
|
1308 |
|
|
endtask // do_jsp_read_write
|
1309 |
|
|
|
1310 |
|
|
|
1311 |
|
|
|
1312 |
|
|
// Puts a value in the TAP IR, assuming we start in IDLE state.
|
1313 |
|
|
// Returns to IDLE state when finished
|
1314 |
|
|
task set_ir;
|
1315 |
|
|
input [3:0] irval;
|
1316 |
|
|
begin
|
1317 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
1318 |
|
|
write_bit(`JTAG_TMS_bit); // select_ir_scan
|
1319 |
|
|
write_bit(3'h0); // capture_ir
|
1320 |
|
|
write_bit(3'h0); // shift_ir
|
1321 |
|
|
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
|
1322 |
|
|
write_bit(`JTAG_TMS_bit); // update_ir
|
1323 |
|
|
write_bit(3'h0); // idle
|
1324 |
|
|
end
|
1325 |
|
|
endtask
|
1326 |
|
|
|
1327 |
|
|
// Resets the TAP and puts it into idle mode
|
1328 |
|
|
task reset_jtag;
|
1329 |
|
|
integer i;
|
1330 |
|
|
begin
|
1331 |
|
|
for(i = 0; i < 8; i=i+1) begin
|
1332 |
|
|
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
|
1333 |
|
|
end
|
1334 |
|
|
write_bit(3'h0); // idle
|
1335 |
|
|
end
|
1336 |
|
|
endtask
|
1337 |
|
|
|
1338 |
|
|
|
1339 |
|
|
////////////////////////////////////////////////////////////////////////////
|
1340 |
|
|
// Tasks to write or read-write a string of data
|
1341 |
|
|
|
1342 |
|
|
task jtag_write_stream;
|
1343 |
|
|
input [63:0] stream;
|
1344 |
|
|
input [7:0] len;
|
1345 |
|
|
input set_last_bit;
|
1346 |
|
|
integer i;
|
1347 |
|
|
integer databit;
|
1348 |
|
|
reg [2:0] bits;
|
1349 |
|
|
begin
|
1350 |
|
|
for(i = 0; i < (len-1); i=i+1) begin
|
1351 |
|
|
databit = (stream >> i) & 1'h1;
|
1352 |
|
|
bits = databit << `JTAG_TDO;
|
1353 |
|
|
write_bit(bits);
|
1354 |
|
|
end
|
1355 |
|
|
|
1356 |
|
|
databit = (stream >> i) & 1'h1;
|
1357 |
|
|
bits = databit << `JTAG_TDO;
|
1358 |
|
|
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
|
1359 |
|
|
write_bit(bits);
|
1360 |
|
|
|
1361 |
|
|
end
|
1362 |
|
|
endtask
|
1363 |
|
|
|
1364 |
|
|
|
1365 |
|
|
task jtag_read_write_stream;
|
1366 |
|
|
input [63:0] stream;
|
1367 |
|
|
input [7:0] len;
|
1368 |
|
|
input set_last_bit;
|
1369 |
|
|
output [63:0] instream;
|
1370 |
|
|
integer i;
|
1371 |
|
|
integer databit;
|
1372 |
|
|
reg [2:0] bits;
|
1373 |
|
|
reg inbit;
|
1374 |
|
|
begin
|
1375 |
|
|
instream = 64'h0;
|
1376 |
|
|
for(i = 0; i < (len-1); i=i+1) begin
|
1377 |
|
|
databit = (stream >> i) & 1'h1;
|
1378 |
|
|
bits = databit << `JTAG_TDO;
|
1379 |
|
|
read_write_bit(bits, inbit);
|
1380 |
|
|
instream = (instream | (inbit << i));
|
1381 |
|
|
end
|
1382 |
|
|
|
1383 |
|
|
databit = (stream >> i) & 1'h1;
|
1384 |
|
|
bits = databit << `JTAG_TDO;
|
1385 |
|
|
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
|
1386 |
|
|
read_write_bit(bits, inbit);
|
1387 |
|
|
instream = (instream | (inbit << (len-1)));
|
1388 |
|
|
end
|
1389 |
|
|
endtask
|
1390 |
|
|
|
1391 |
|
|
/////////////////////////////////////////////////////////////////////////
|
1392 |
|
|
// Tasks which write or readwrite a single bit (including clocking)
|
1393 |
|
|
|
1394 |
|
|
task write_bit;
|
1395 |
|
|
input [2:0] bitvals;
|
1396 |
|
|
begin
|
1397 |
|
|
|
1398 |
|
|
// Set data
|
1399 |
|
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
1400 |
|
|
`wait_jtag_period;
|
1401 |
|
|
|
1402 |
|
|
// Raise clock
|
1403 |
|
|
jtag_out(bitvals | `JTAG_TCK_bit);
|
1404 |
|
|
`wait_jtag_period;
|
1405 |
|
|
|
1406 |
|
|
// drop clock (making output available in the SHIFT_xR states)
|
1407 |
|
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
1408 |
|
|
`wait_jtag_period;
|
1409 |
|
|
end
|
1410 |
|
|
endtask
|
1411 |
|
|
|
1412 |
|
|
task read_write_bit;
|
1413 |
|
|
input [2:0] bitvals;
|
1414 |
|
|
output l_tdi_val;
|
1415 |
|
|
begin
|
1416 |
|
|
|
1417 |
|
|
// read bit state
|
1418 |
|
|
l_tdi_val <= jtag_tdi_i;
|
1419 |
|
|
|
1420 |
|
|
// Set data
|
1421 |
|
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
1422 |
|
|
`wait_jtag_period;
|
1423 |
|
|
|
1424 |
|
|
// Raise clock
|
1425 |
|
|
jtag_out(bitvals | `JTAG_TCK_bit);
|
1426 |
|
|
`wait_jtag_period;
|
1427 |
|
|
|
1428 |
|
|
// drop clock (making output available in the SHIFT_xR states)
|
1429 |
|
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
1430 |
|
|
`wait_jtag_period;
|
1431 |
|
|
end
|
1432 |
|
|
endtask
|
1433 |
|
|
|
1434 |
|
|
/////////////////////////////////////////////////////////////////
|
1435 |
|
|
// Basic functions to set the state of the JTAG TAP I/F bits
|
1436 |
|
|
|
1437 |
|
|
task jtag_out;
|
1438 |
|
|
input [2:0] bitvals;
|
1439 |
|
|
begin
|
1440 |
|
|
|
1441 |
|
|
jtag_tck_o <= bitvals[`JTAG_TCK];
|
1442 |
|
|
jtag_tms_o <= bitvals[`JTAG_TMS];
|
1443 |
|
|
jtag_tdo_o <= bitvals[`JTAG_TDO];
|
1444 |
|
|
end
|
1445 |
|
|
endtask
|
1446 |
|
|
|
1447 |
|
|
|
1448 |
|
|
task jtag_inout;
|
1449 |
|
|
input [2:0] bitvals;
|
1450 |
|
|
output l_tdi_val;
|
1451 |
|
|
begin
|
1452 |
|
|
|
1453 |
|
|
jtag_tck_o <= bitvals[`JTAG_TCK];
|
1454 |
|
|
jtag_tms_o <= bitvals[`JTAG_TMS];
|
1455 |
|
|
jtag_tdo_o <= bitvals[`JTAG_TDO];
|
1456 |
|
|
|
1457 |
|
|
l_tdi_val <= jtag_tdi_i;
|
1458 |
|
|
end
|
1459 |
|
|
endtask
|
1460 |
|
|
|
1461 |
|
|
endmodule
|