1 |
3 |
nyawn |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// timescale.v ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// ////
|
6 |
|
|
//// This file is part of the SoC Debug Interface. ////
|
7 |
|
|
//// http://www.opencores.org/projects/DebugInterface/ ////
|
8 |
|
|
//// ////
|
9 |
|
|
//// Author(s): ////
|
10 |
|
|
//// Igor Mohor (igorm@opencores.org) ////
|
11 |
|
|
//// ////
|
12 |
|
|
//// ////
|
13 |
|
|
//// All additional information is avaliable in the README.txt ////
|
14 |
|
|
//// file. ////
|
15 |
|
|
//// ////
|
16 |
|
|
//////////////////////////////////////////////////////////////////////
|
17 |
|
|
//// ////
|
18 |
|
|
//// Copyright (C) 2000 - 2004 Authors ////
|
19 |
|
|
//// ////
|
20 |
|
|
//// This source file may be used and distributed without ////
|
21 |
|
|
//// restriction provided that this copyright statement is not ////
|
22 |
|
|
//// removed from the file and that any derivative work contains ////
|
23 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
24 |
|
|
//// ////
|
25 |
|
|
//// This source file is free software; you can redistribute it ////
|
26 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
27 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
28 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
29 |
|
|
//// later version. ////
|
30 |
|
|
//// ////
|
31 |
|
|
//// This source is distributed in the hope that it will be ////
|
32 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
33 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
34 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
35 |
|
|
//// details. ////
|
36 |
|
|
//// ////
|
37 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
38 |
|
|
//// Public License along with this source; if not, download it ////
|
39 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
40 |
|
|
//// ////
|
41 |
|
|
//////////////////////////////////////////////////////////////////////
|
42 |
|
|
//
|
43 |
|
|
// CVS Revision History
|
44 |
|
|
//
|
45 |
|
|
// $Log: timescale.v,v $
|
46 |
|
|
// Revision 1.1 2008/07/08 19:11:56 Nathan
|
47 |
|
|
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
|
48 |
|
|
//
|
49 |
|
|
// Revision 1.1 2008/06/18 18:34:48 Nathan
|
50 |
|
|
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
|
51 |
|
|
//
|
52 |
|
|
// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan
|
53 |
|
|
// Original from OpenCores
|
54 |
|
|
//
|
55 |
|
|
// Revision 1.4 2004/03/28 20:27:40 igorm
|
56 |
|
|
// New release of the debug interface (3rd. release).
|
57 |
|
|
//
|
58 |
|
|
// Revision 1.3 2004/01/17 17:01:25 mohor
|
59 |
|
|
// Almost finished.
|
60 |
|
|
//
|
61 |
|
|
// Revision 1.2 2003/12/23 14:26:01 mohor
|
62 |
|
|
// New version of the debug interface. Not finished, yet.
|
63 |
|
|
//
|
64 |
|
|
//
|
65 |
|
|
//
|
66 |
|
|
//
|
67 |
|
|
`timescale 1ns/10ps
|
68 |
|
|
|