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nyawn |
//////////////////////////////////////////////////////////////////////
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// File: CRC32.v
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// Date: Thu Nov 27 13:56:49 2003
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//
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// Copyright (C) 1999-2003 Easics NV.
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// This source file may be used and distributed without restriction
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// provided that this copyright statement is not removed from the file
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// and that any derivative work contains the original copyright notice
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// and the associated disclaimer.
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//
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
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// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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//
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// Purpose: Verilog module containing a synthesizable CRC function
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// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
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// * data width: 1
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//
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// Info: janz@easics.be (Jan Zegers)
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// http://www.easics.com
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//
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// Modified by Nathan Yawn for the Advanced Debug Module
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// Changes (C) 2008 Nathan Yawn
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///////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: adbg_crc32.v,v $
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// Revision 1.1 2008/07/22 20:28:29 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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//
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// Revision 1.3 2008/07/06 20:02:53 Nathan
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// Fixes for synthesis with Xilinx ISE (also synthesizable with
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// Quartus II 7.0). Ran through dos2unix.
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//
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// Revision 1.2 2008/06/20 19:22:10 Nathan
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// Reversed the direction of the CRC computation shift, for a more
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// hardware-efficient implementation.
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//
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//
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//
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//
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module adbg_crc32 (clk, data, enable, shift, clr, rst, crc_out, serial_out);
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input clk;
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input data;
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input enable;
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input shift;
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input clr;
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input rst;
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output [31:0] crc_out;
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output serial_out;
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reg [31:0] crc;
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wire [31:0] new_crc;
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// You may notice that the 'poly' in this implementation is backwards.
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// This is because the shift is also 'backwards', so that the data can
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// be shifted out in the same direction, which saves on logic + routing.
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assign new_crc[0] = crc[1];
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assign new_crc[1] = crc[2];
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assign new_crc[2] = crc[3];
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assign new_crc[3] = crc[4];
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assign new_crc[4] = crc[5];
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assign new_crc[5] = crc[6] ^ data ^ crc[0];
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assign new_crc[6] = crc[7];
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assign new_crc[7] = crc[8];
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assign new_crc[8] = crc[9] ^ data ^ crc[0];
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assign new_crc[9] = crc[10] ^ data ^ crc[0];
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assign new_crc[10] = crc[11];
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assign new_crc[11] = crc[12];
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assign new_crc[12] = crc[13];
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assign new_crc[13] = crc[14];
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assign new_crc[14] = crc[15];
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assign new_crc[15] = crc[16] ^ data ^ crc[0];
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assign new_crc[16] = crc[17];
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assign new_crc[17] = crc[18];
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assign new_crc[18] = crc[19];
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assign new_crc[19] = crc[20] ^ data ^ crc[0];
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assign new_crc[20] = crc[21] ^ data ^ crc[0];
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assign new_crc[21] = crc[22] ^ data ^ crc[0];
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assign new_crc[22] = crc[23];
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assign new_crc[23] = crc[24] ^ data ^ crc[0];
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assign new_crc[24] = crc[25] ^ data ^ crc[0];
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assign new_crc[25] = crc[26];
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assign new_crc[26] = crc[27] ^ data ^ crc[0];
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assign new_crc[27] = crc[28] ^ data ^ crc[0];
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assign new_crc[28] = crc[29];
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assign new_crc[29] = crc[30] ^ data ^ crc[0];
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assign new_crc[30] = crc[31] ^ data ^ crc[0];
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assign new_crc[31] = data ^ crc[0];
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always @ (posedge clk or posedge rst)
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begin
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if(rst)
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crc[31:0] <= #1 32'hffffffff;
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else if(clr)
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crc[31:0] <= #1 32'hffffffff;
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else if(enable)
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crc[31:0] <= #1 new_crc;
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else if (shift)
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crc[31:0] <= #1 {1'b0, crc[31:1]};
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end
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//assign crc_match = (crc == 32'h0);
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assign crc_out = crc; //[31];
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assign serial_out = crc[0];
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endmodule
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