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nyawn |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// adv_dbg_tb.v ////
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//// ////
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//// ////
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//// Testbench for the SoC Advanced Debug Interface. ////
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//// ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: adv_dbg_tb.v,v $
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nyawn |
// Revision 1.6 2010-01-16 02:15:22 Nathan
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// Updated to match changes in hardware. Added support for hi-speed mode.
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//
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// Revision 1.5 2010-01-08 01:41:07 Nathan
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// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
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//
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nyawn |
// Revision 1.4 2009/05/17 20:54:55 Nathan
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// Changed email address to opencores.org
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//
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// Revision 1.3 2008/07/11 08:18:47 Nathan
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// Added a bit to the CPU test. Added the hack that allows the driver to work with a Xilinx BSCAN device.
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//
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`include "tap_defines.v"
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nyawn |
`include "adbg_defines.v"
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`include "adbg_wb_defines.v"
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3 |
nyawn |
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// Polynomial for the CRC calculation
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// Yes, it's backwards. Yes, this is on purpose.
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// To decrease logic + routing, we want to shift the CRC calculation
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// in the same direction we use to shift the data out, LSB first.
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`define DBG_CRC_POLY 32'hedb88320
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// These are indicies into an array which hold values for the JTAG outputs
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`define JTAG_TMS 0
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`define JTAG_TCK 1
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`define JTAG_TDO 2
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`define JTAG_TMS_bit 3'h1
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`define JTAG_TCK_bit 3'h2
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`define JTAG_TDO_bit 3'h4
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`define wait_jtag_period #50
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module adv_debug_tb (
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jtag_tck_o,
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jtag_tms_o,
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jtag_tdo_o,
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jtag_tdi_i,
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wb_clk_o,
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sys_rstn_o
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);
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output jtag_tck_o;
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output jtag_tms_o;
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output jtag_tdo_o;
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input jtag_tdi_i;
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output wb_clk_o;
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output sys_rstn_o;
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// Connections to the JTAG TAP
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reg jtag_tck_o;
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reg jtag_tms_o;
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reg jtag_tdo_o;
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wire jtag_tdi_i;
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reg wb_clk_o;
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reg sys_rst_o;
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reg sys_rstn_o;
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reg test_enabled;
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// Data which will be written to the WB interface
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reg [31:0] static_data32 [0:15];
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reg [15:0] static_data16 [0:15];
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reg [7:0] static_data8 [0:15];
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// Arrays to hold data read back from the WB interface, for comparison
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reg [31:0] input_data32 [0:15];
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reg [15:0] input_data16 [0:15];
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reg [7:0] input_data8 [0:15];
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reg [32:0] err_data; // holds the contents of the error register from the various modules
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reg failed;
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integer i;
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initial
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begin
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jtag_tck_o = 1'b0;
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jtag_tms_o = 1'b0;
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jtag_tdo_o = 1'b0;
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end
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// Provide the wishbone / CPU / system clock
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initial
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begin
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wb_clk_o = 1'b0;
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forever #5 wb_clk_o = ~wb_clk_o;
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end
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initial
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begin
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sys_rstn_o = 1'b1;
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#200 sys_rstn_o = 1'b0;
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#5000 sys_rstn_o = 1'b1;
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end
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// Start the test (and reset the wishbone)
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initial
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begin
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test_enabled = 1'b0;
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// Init the memory
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initialize_memory(32'h0,32'h16);
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#5 test_enabled<= 1'b1;
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end
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// This is the main test procedure
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always @ (posedge test_enabled)
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begin
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$display("Starting advanced debug test");
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reset_jtag;
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#6000;
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check_idcode;
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#1000;
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// Select the debug module in the IR
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set_ir(`DEBUG);
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#1000;
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`ifdef DBG_CPU0_SUPPORTED
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// STALL the CPU, so it won't interfere with WB tests
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// Select the CPU0 unit in the debug module
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#1000;
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$display("Selecting CPU0 module at time %t", $time);
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select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
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// Set the stall bit...holding the CPU in reset prevents WB access (?)
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$display("Setting reset and stall bits at time %t", $time);
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write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
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#1000;
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`endif
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///////////////////////////////////////////////////////////////////
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// Test the Wishbone unit
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////////////////////////////////////////////////////////////////////
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`ifdef DBG_WISHBONE_SUPPORTED
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// Select the WB unit in the debug module
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#1000;
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$display("Selecting Wishbone module at time %t", $time);
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select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
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// Reset the error bit
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write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen
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#1000;
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/////////////////////////////////
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// Test 8-bit WB access
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failed = 0;
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$display("Testing WB 8-bit burst write at time %t: resetting ", $time);
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do_module_burst_write(3'h1, 16'd16, 32'h87); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
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#1000;
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$display("Testing WB 8-bit burst read at time %t", $time);
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do_module_burst_read(3'h1, 16'd16, 32'h87);
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#1000;
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for(i = 0; i < 16; i = i+1) begin
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if(static_data8[i] != input_data8[i]) begin
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failed = 1;
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$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data8[i], input_data8[i]);
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end
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end
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if(!failed) $display("8-bit read/write OK!");
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/////////////////////////////////
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// Test 16-bit WB access
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failed = 0;
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$display("Testing WB 16-bit burst write at time %t", $time);
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do_module_burst_write(3'h2, 16'd16, 32'h22); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
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#1000;
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$display("Testing WB 16-bit burst read at time %t", $time);
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do_module_burst_read(3'h2, 16'd16, 32'h22);
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#1000;
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for(i = 0; i < 16; i = i+1) begin
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if(static_data16[i] != input_data16[i]) begin
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failed = 1;
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$display("16-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data16[i], input_data16[i]);
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end
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end
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if(!failed) $display("16-bit read/write OK!");
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////////////////////////////////////
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// Test 32-bit WB access
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failed = 0;
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$display("Testing WB 32-bit burst write at time %t", $time);
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do_module_burst_write(3'h4, 16'd16, 32'h100); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
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#1000;
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$display("Testing WB 32-bit burst read at time %t", $time);
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do_module_burst_read(3'h4, 16'd16, 32'h100);
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#1000;
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for(i = 0; i < 16; i = i+1) begin
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if(static_data32[i] != input_data32[i]) begin
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failed = 1;
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$display("32-bit data mismatch at index %d, wrote 0x%x, read 0x%x", i, static_data32[i], input_data32[i]);
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end
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end
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if(!failed) $display("32-bit read/write OK!");
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////////////////////////////////
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// Test error register
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err_data = 33'h0;
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// Select and reset the error register
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write_module_internal_register(`DBG_WB_INTREG_ERROR, `DBG_WB_REGSELECT_SIZE, 64'h1, 8'h1); // regidx,idxlen,writedata, datalen;
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//i_wb.cycle_response(`ERR_RESPONSE, 2, 0); // response type, wait cycles, retry_cycles
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do_module_burst_write(3'h4, 16'd4, 32'hdeaddead); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
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read_module_internal_register(8'd33, err_data); // get the error register
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$display("Error bit is %d, error address is %x", err_data[0], err_data>>1);
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`endif // WB module supported
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///////////////////////////////////////////////////////////////////
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// Test CPU0 unit
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////////////////////////////////////////////////////////////////////
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`ifdef DBG_CPU0_SUPPORTED
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// Select the CPU0 unit in the debug module
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#1000;
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$display("Selecting CPU0 module at time %t", $time);
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select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
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// Set the stall bit (clear the reset bit)
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$display("Setting reset and stall bits at time %t", $time);
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write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h2); // idx, idxlen, data, datalen
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#1000;
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// Make sure CPU stalled
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$display("Testing reset and stall bits at time %t", $time);
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read_module_internal_register(8'd2, err_data); // We assume the register is already selected
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$display("Reset and stall bits are %x", err_data);
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#1000;
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// Write some opcodes into the memory
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select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
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static_data32[0] = 32'hE0000005;/* l.xor r0,r0,r0 */
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static_data32[1] = 32'h9C200000; /* l.addi r1,r0,0x0 */
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static_data32[2] = 32'h18400000;/* l.movhi r2,0x4000 */
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static_data32[3] = 32'hA8420030;/* l.ori r2,r2,0x30 */
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static_data32[4] = 32'h9C210001;/* l.addi r1,r1,1 */
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static_data32[5] = 32'h9C210001; /* l.addi r1,r1,1 */
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static_data32[6] = 32'hD4020800;/* l.sw 0(r2),r1 */
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static_data32[7] = 32'h9C210001;/* l.addi r1,r1,1 */
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static_data32[8] = 32'h84620000;/* l.lwz r3,0(r2) */
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static_data32[9] = 32'h03FFFFFB;/* l.j loop2 */
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static_data32[10] = 32'hE0211800;/* l.add r1,r1,r3 */
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do_module_burst_write(3'h4, 16'd11, 32'h0); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
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#1000;
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select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
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#1000;
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$display("Enabling CPU exceptions at time %t", $time);
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static_data32[0] = 32'h1; // enable exceptions
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do_module_burst_write(3'h4, 16'd1, 32'd17); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
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#1000;
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$display("Set \'trap causes stall\' at time %t", $time);
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static_data32[0] = 32'h00002000; // Trap causes stall
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do_module_burst_write(3'h4, 16'd1, (6 << 11)+20); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
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#1000;
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$display("Set PC at time %t", $time);
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static_data32[0] = 32'h0; // Set PC
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do_module_burst_write(3'h4, 16'd1, 32'd16); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
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#1000;
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$display("Set step bit at time %t", $time);
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static_data32[0] = (1 << 22); // set step bit
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do_module_burst_write(3'h4, 16'd1, (6<<11) + 16); // 3-bit word size (bytes), 16-bit word count, 32-bit start address
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333 |
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334 |
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// Unstall x11
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335 |
|
|
for(i = 0; i < 11; i = i + 1)
|
336 |
|
|
begin
|
337 |
|
|
#1000;
|
338 |
|
|
$display("Unstall (%d/11) at time %t", i, $time);
|
339 |
|
|
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
|
340 |
|
|
end
|
341 |
|
|
|
342 |
|
|
#1000;
|
343 |
|
|
#1000;
|
344 |
|
|
#1000;
|
345 |
|
|
|
346 |
|
|
$display("Getting NPC at time %t", $time);
|
347 |
|
|
do_module_burst_read(3'h4, 16'd1, 32'd16);
|
348 |
|
|
|
349 |
|
|
$display("NPC = %x, expected 0x00000010", input_data32[0]);
|
350 |
|
|
|
351 |
|
|
$display("Getting PPC at time %t", $time);
|
352 |
|
|
do_module_burst_read(3'h4, 16'd1, 32'd18);
|
353 |
|
|
$display("PPC = %x, expected 0x00000028", input_data32[0]);
|
354 |
|
|
|
355 |
|
|
#1000;
|
356 |
|
|
$display("Getting R1 at time %t", $time);
|
357 |
|
|
do_module_burst_read(3'h4, 16'd1, 32'h401); // Word size, count, addr; save old instr
|
358 |
|
|
$display("R1 = %d, expected 5", input_data32[0]);
|
359 |
|
|
|
360 |
|
|
#1000;
|
361 |
|
|
$display("Un-set step bit at %t", $time);
|
362 |
|
|
static_data32[0] = 32'h0; // Trap causes stall
|
363 |
|
|
do_module_burst_write(3'h4, 16'd1, (6 << 11)+16);
|
364 |
|
|
|
365 |
|
|
// Put a trap instr at 0x20
|
366 |
|
|
#1000;
|
367 |
|
|
$display("Select WB at %t", $time);
|
368 |
|
|
select_debug_module(`DBG_TOP_WISHBONE_DEBUG_MODULE);
|
369 |
|
|
#1000;
|
370 |
|
|
$display("Save old instr at %t", $time);
|
371 |
|
|
do_module_burst_read(3'h4, 16'd1, 32'h20); // Save old instr
|
372 |
|
|
#1000;
|
373 |
|
|
$display("Put trap instr at %t", $time);
|
374 |
|
|
static_data32[0] = 32'h21000001; /* l.trap */
|
375 |
|
|
do_module_burst_write(3'h4, 16'd1, 32'h20); // put new instr
|
376 |
|
|
#1000;
|
377 |
|
|
$display("Select CPU0 at %t", $time);
|
378 |
|
|
select_debug_module(`DBG_TOP_CPU0_DEBUG_MODULE);
|
379 |
|
|
#1000;
|
380 |
|
|
$display("Set PC to 0x24 at %t", $time);
|
381 |
|
|
static_data32[0] = 32'h24;
|
382 |
|
|
do_module_burst_write(3'h4, 16'd1, 32'd16); // Set PC to 0x24
|
383 |
|
|
#1000;
|
384 |
|
|
$display("Unstall at time %t", $time);
|
385 |
|
|
write_module_internal_register(32'h0, 8'h1, 32'h0, 8'h2); // idx, idxlen, data, datalen
|
386 |
|
|
|
387 |
|
|
// We assume it stalls again here...
|
388 |
|
|
#1000;
|
389 |
|
|
|
390 |
|
|
err_data = 1;
|
391 |
|
|
while(err_data != 0)
|
392 |
|
|
begin
|
393 |
|
|
$display("Testing for stall at %t", $time);
|
394 |
|
|
read_module_internal_register(8'd2, err_data); // We assume the register is already selected
|
395 |
|
|
#1000;
|
396 |
|
|
end
|
397 |
|
|
|
398 |
|
|
|
399 |
|
|
// *** The software self-test does 2 separate reads here...
|
400 |
|
|
$display("Getting NPC at time %t", $time);
|
401 |
|
|
do_module_burst_read(3'h4, 16'd3, 32'd16);
|
402 |
|
|
|
403 |
|
|
$display("NPC = %x, expected 0x00000024", input_data32[0]);
|
404 |
|
|
$display("PPC = %x, expected 0x00000020", input_data32[2]);
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
|
408 |
|
|
`endif
|
409 |
|
|
|
410 |
|
|
|
411 |
|
|
end
|
412 |
|
|
|
413 |
|
|
task initialize_memory;
|
414 |
|
|
input [31:0] start_addr;
|
415 |
|
|
input [31:0] length;
|
416 |
|
|
integer i;
|
417 |
|
|
reg [31:0] addr;
|
418 |
|
|
begin
|
419 |
|
|
|
420 |
|
|
for (i=0; i<length; i=i+1)
|
421 |
|
|
begin
|
422 |
|
|
static_data32[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
|
423 |
|
|
static_data16[i] <= {i[7:0], i[7:0]+ 2'd1};
|
424 |
|
|
static_data8[i] <= i[7:0];
|
425 |
|
|
end
|
426 |
|
|
end
|
427 |
|
|
endtask
|
428 |
|
|
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
///////////////////////////////////////////////////////////////////////////
|
432 |
|
|
// Higher-level chain manipulation functions
|
433 |
|
|
|
434 |
|
|
// calculate the CRC, up to 32 bits at a time
|
435 |
|
|
task compute_crc;
|
436 |
|
|
input [31:0] crc_in;
|
437 |
|
|
input [31:0] data_in;
|
438 |
|
|
input [5:0] length_bits;
|
439 |
|
|
output [31:0] crc_out;
|
440 |
|
|
integer i;
|
441 |
|
|
reg [31:0] d;
|
442 |
|
|
reg [31:0] c;
|
443 |
|
|
begin
|
444 |
|
|
crc_out = crc_in;
|
445 |
|
|
for(i = 0; i < length_bits; i = i+1) begin
|
446 |
|
|
d = (data_in[i]) ? 32'hffffffff : 32'h0;
|
447 |
|
|
c = (crc_out[0]) ? 32'hffffffff : 32'h0;
|
448 |
|
|
//crc_out = {crc_out[30:0], 1'b0}; // original
|
449 |
|
|
crc_out = crc_out >> 1;
|
450 |
|
|
crc_out = crc_out ^ ((d ^ c) & `DBG_CRC_POLY);
|
451 |
|
|
//$display("CRC Itr %d, inbit = %d, crc = 0x%x", i, data_in[i], crc_out);
|
452 |
|
|
end
|
453 |
|
|
end
|
454 |
|
|
endtask
|
455 |
|
|
|
456 |
|
|
task check_idcode;
|
457 |
|
|
reg [63:0] readdata;
|
458 |
|
|
reg[31:0] idcode;
|
459 |
|
|
begin
|
460 |
|
|
set_ir(`IDCODE);
|
461 |
|
|
|
462 |
|
|
// Read the IDCODE in the DR
|
463 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
464 |
|
|
write_bit(3'h0); // capture_ir
|
465 |
|
|
write_bit(3'h0); // shift_ir
|
466 |
|
|
jtag_read_write_stream(64'h0, 8'd32, 1, readdata); // write data, exit_1
|
467 |
|
|
write_bit(`JTAG_TMS_bit); // update_ir
|
468 |
|
|
write_bit(3'h0); // idle
|
469 |
|
|
idcode = readdata[31:0];
|
470 |
|
|
$display("Got TAP IDCODE 0x%x, expected 0x%x", idcode, `IDCODE_VALUE);
|
471 |
|
|
end
|
472 |
|
|
endtask;
|
473 |
|
|
|
474 |
|
|
task select_debug_module;
|
475 |
|
|
input [1:0] moduleid;
|
476 |
|
|
reg validid;
|
477 |
|
|
begin
|
478 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
479 |
|
|
write_bit(3'h0); // capture_ir
|
480 |
|
|
write_bit(3'h0); // shift_ir
|
481 |
|
|
jtag_write_stream({1'b1,moduleid}, 8'h3, 1); // write data, exit_1
|
482 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
483 |
|
|
write_bit(3'h0); // idle
|
484 |
|
|
|
485 |
|
|
$display("Selecting module (%0x)", moduleid);
|
486 |
|
|
|
487 |
|
|
// Read back the status to make sure a valid chain is selected
|
488 |
|
|
/* Pointless, the newly selected module would respond instead...
|
489 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
490 |
|
|
write_bit(3'h0); // capture_ir
|
491 |
|
|
write_bit(3'h0); // shift_ir
|
492 |
|
|
read_write_bit(`JTAG_TMS_bit, validid); // get data, exit_1
|
493 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
494 |
|
|
write_bit(3'h0); // idle
|
495 |
|
|
|
496 |
|
|
if(validid) $display("Selected valid module (%0x)", moduleid);
|
497 |
|
|
else $display("Failed to select module (%0x)", moduleid);
|
498 |
|
|
*/
|
499 |
|
|
end
|
500 |
|
|
endtask
|
501 |
|
|
|
502 |
|
|
|
503 |
|
|
task send_module_burst_command;
|
504 |
|
|
input [3:0] opcode;
|
505 |
|
|
input [31:0] address;
|
506 |
|
|
input [15:0] burstlength;
|
507 |
|
|
reg [63:0] streamdata;
|
508 |
|
|
begin
|
509 |
|
|
streamdata = {11'h0,1'b0,opcode,address,burstlength};
|
510 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
511 |
|
|
write_bit(3'h0); // capture_ir
|
512 |
|
|
write_bit(3'h0); // shift_ir
|
513 |
|
|
jtag_write_stream(streamdata, 8'd53, 1); // write data, exit_1
|
514 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
515 |
|
|
write_bit(3'h0); // idle
|
516 |
|
|
end
|
517 |
|
|
endtask
|
518 |
|
|
|
519 |
|
|
task select_module_internal_register; // Really just a read, with discarded data
|
520 |
|
|
input [31:0] regidx;
|
521 |
|
|
input [7:0] len; // the length of the register index data, we assume not more than 32
|
522 |
|
|
reg[63:0] streamdata;
|
523 |
|
|
begin
|
524 |
|
|
streamdata = 64'h0;
|
525 |
|
|
streamdata = streamdata | regidx;
|
526 |
|
|
streamdata = streamdata | (`DBG_WB_CMD_IREG_SEL << len);
|
527 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
528 |
|
|
write_bit(3'h0); // capture_ir
|
529 |
|
|
write_bit(3'h0); // shift_ir
|
530 |
|
|
jtag_write_stream(streamdata, (len+5), 1); // write data, exit_1
|
531 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
532 |
|
|
write_bit(3'h0); // idle
|
533 |
|
|
end
|
534 |
|
|
endtask
|
535 |
|
|
|
536 |
|
|
|
537 |
|
|
task read_module_internal_register; // We assume the register is already selected
|
538 |
|
|
//input [31:0] regidx;
|
539 |
|
|
input [7:0] len; // the length of the data desired, we assume a max of 64 bits
|
540 |
|
|
output [63:0] instream;
|
541 |
|
|
reg [63:0] bitmask;
|
542 |
|
|
begin
|
543 |
|
|
instream = 64'h0;
|
544 |
|
|
// We shift out all 0's, which is a NOP to the debug unit
|
545 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
546 |
|
|
write_bit(3'h0); // capture_ir
|
547 |
|
|
write_bit(3'h0); // shift_ir
|
548 |
|
|
// Shift at least 5 bits, as this is the min, for a valid NOP
|
549 |
|
|
jtag_read_write_stream(64'h0, len+4,1,instream); // exit_1
|
550 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
551 |
|
|
write_bit(3'h0); // idle
|
552 |
|
|
bitmask = 64'hffffffffffffffff;
|
553 |
|
|
bitmask = bitmask << len;
|
554 |
|
|
bitmask = ~bitmask;
|
555 |
|
|
instream = instream & bitmask; // Cut off any unwanted excess bits
|
556 |
|
|
end
|
557 |
|
|
endtask
|
558 |
|
|
|
559 |
|
|
task write_module_internal_register;
|
560 |
|
|
input [31:0] regidx; // the length of the register index data
|
561 |
|
|
input [7:0] idxlen;
|
562 |
|
|
input [63:0] writedata;
|
563 |
|
|
input [7:0] datalen; // the length of the data to write. We assume the two length combined are 59 or less.
|
564 |
|
|
reg[63:0] streamdata;
|
565 |
|
|
begin
|
566 |
|
|
streamdata = 64'h0; // This will 0 the toplevel/module select bit
|
567 |
|
|
streamdata = streamdata | writedata;
|
568 |
|
|
streamdata = streamdata | (regidx << datalen);
|
569 |
|
|
streamdata = streamdata | (`DBG_WB_CMD_IREG_WR << (idxlen+datalen));
|
570 |
|
|
|
571 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
572 |
|
|
write_bit(3'h0); // capture_ir
|
573 |
|
|
write_bit(3'h0); // shift_ir
|
574 |
|
|
jtag_write_stream(streamdata, (idxlen+datalen+5), 1); // write data, exit_1
|
575 |
|
|
write_bit(`JTAG_TMS_bit); // update_dr
|
576 |
|
|
write_bit(3'h0); // idle
|
577 |
|
|
end
|
578 |
|
|
endtask
|
579 |
|
|
|
580 |
|
|
// This includes the sending of the burst command
|
581 |
|
|
task do_module_burst_read;
|
582 |
|
|
input [5:0] word_size_bytes;
|
583 |
|
|
input [15:0] word_count;
|
584 |
|
|
input [31:0] start_address;
|
585 |
|
|
reg [3:0] opcode;
|
586 |
|
|
reg status;
|
587 |
|
|
reg [63:0] instream;
|
588 |
|
|
integer i;
|
589 |
|
|
integer j;
|
590 |
|
|
reg [31:0] crc_calc_i;
|
591 |
|
|
reg [31:0] crc_calc_o; // temp signal...
|
592 |
|
|
reg [31:0] crc_read;
|
593 |
|
|
reg [5:0] word_size_bits;
|
594 |
|
|
begin
|
595 |
|
|
$display("Doing burst read, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
|
596 |
|
|
instream = 64'h0;
|
597 |
|
|
word_size_bits = word_size_bytes << 3;
|
598 |
|
|
crc_calc_i = 32'hffffffff;
|
599 |
|
|
|
600 |
|
|
// Send the command
|
601 |
|
|
case (word_size_bytes)
|
602 |
|
|
3'h1: opcode = `DBG_WB_CMD_BREAD8;
|
603 |
|
|
3'h2: opcode = `DBG_WB_CMD_BREAD16;
|
604 |
|
|
3'h4: opcode = `DBG_WB_CMD_BREAD32;
|
605 |
|
|
default:
|
606 |
|
|
begin
|
607 |
|
|
$display("Tried burst read with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
608 |
|
|
opcode = `DBG_WB_CMD_BREAD32;
|
609 |
|
|
end
|
610 |
|
|
endcase
|
611 |
|
|
|
612 |
|
|
send_module_burst_command(opcode,start_address, word_count); // returns to state idle
|
613 |
|
|
|
614 |
|
|
// This charming kludge provides ONE TCK, in case a xilinx BSCAN TAP is used,
|
615 |
|
|
// because the FSM needs it between the read burst command and the actual
|
616 |
|
|
// read burst. Blech.
|
617 |
|
|
#500;
|
618 |
|
|
set_ir(`IDCODE);
|
619 |
|
|
#500;
|
620 |
|
|
set_ir(`DEBUG);
|
621 |
|
|
#500;
|
622 |
|
|
|
623 |
|
|
// Get us back to shift_dr mode to read a burst
|
624 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
625 |
|
|
write_bit(3'h0); // capture_ir
|
626 |
|
|
write_bit(3'h0); // shift_ir
|
627 |
|
|
|
628 |
32 |
nyawn |
`ifdef ADBG_USE_HISPEED
|
629 |
|
|
// Get 1 status bit, then word_size_bytes*8 bits
|
630 |
|
|
status = 1'b0;
|
631 |
|
|
j = 0;
|
632 |
|
|
while(!status) begin
|
633 |
|
|
read_write_bit(3'h0, status);
|
634 |
|
|
j = j + 1;
|
635 |
|
|
end
|
636 |
|
|
|
637 |
|
|
if(j > 1) begin
|
638 |
|
|
$display("Took %0d tries before good status bit during burst read", j);
|
639 |
|
|
end
|
640 |
|
|
`endif
|
641 |
|
|
|
642 |
3 |
nyawn |
// Now, repeat...
|
643 |
|
|
for(i = 0; i < word_count; i=i+1) begin
|
644 |
32 |
nyawn |
|
645 |
|
|
`ifndef ADBG_USE_HISPEED
|
646 |
3 |
nyawn |
// Get 1 status bit, then word_size_bytes*8 bits
|
647 |
|
|
status = 1'b0;
|
648 |
|
|
j = 0;
|
649 |
|
|
while(!status) begin
|
650 |
|
|
read_write_bit(3'h0, status);
|
651 |
|
|
j = j + 1;
|
652 |
|
|
end
|
653 |
|
|
|
654 |
|
|
if(j > 1) begin
|
655 |
|
|
$display("Took %0d tries before good status bit during burst read", j);
|
656 |
|
|
end
|
657 |
32 |
nyawn |
`endif
|
658 |
3 |
nyawn |
|
659 |
|
|
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
|
660 |
|
|
//$display("Read 0x%0x", instream[31:0]);
|
661 |
|
|
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
|
662 |
|
|
crc_calc_i = crc_calc_o;
|
663 |
|
|
if(word_size_bytes == 1) input_data8[i] = instream[7:0];
|
664 |
|
|
else if(word_size_bytes == 2) input_data16[i] = instream[15:0];
|
665 |
|
|
else input_data32[i] = instream[31:0];
|
666 |
|
|
end
|
667 |
|
|
|
668 |
|
|
// Read the data CRC from the debug module.
|
669 |
|
|
jtag_read_write_stream(64'h0, 6'd32, 1, crc_read);
|
670 |
|
|
if(crc_calc_o != crc_read) $display("CRC ERROR! Computed 0x%x, read CRC 0x%x", crc_calc_o, crc_read);
|
671 |
|
|
else $display("CRC OK!");
|
672 |
|
|
|
673 |
|
|
// Finally, shift out 5 0's, to make the next command a NOP
|
674 |
|
|
// Not necessary, debug unit won't latch a new opcode at the end of a burst
|
675 |
|
|
//jtag_write_stream(64'h0, 8'h5, 1);
|
676 |
|
|
write_bit(`JTAG_TMS_bit); // update_ir
|
677 |
|
|
write_bit(3'h0); // idle
|
678 |
|
|
end
|
679 |
|
|
endtask
|
680 |
|
|
|
681 |
|
|
|
682 |
|
|
task do_module_burst_write;
|
683 |
|
|
input [5:0] word_size_bytes;
|
684 |
|
|
input [15:0] word_count;
|
685 |
|
|
input [31:0] start_address;
|
686 |
|
|
reg [3:0] opcode;
|
687 |
|
|
reg status;
|
688 |
|
|
reg [63:0] dataword;
|
689 |
|
|
integer i;
|
690 |
|
|
integer j;
|
691 |
|
|
reg [31:0] crc_calc_i;
|
692 |
|
|
reg [31:0] crc_calc_o;
|
693 |
|
|
reg crc_match;
|
694 |
|
|
reg [5:0] word_size_bits;
|
695 |
|
|
begin
|
696 |
|
|
$display("Doing burst write, word size %d, word count %d, start address 0x%x", word_size_bytes, word_count, start_address);
|
697 |
|
|
word_size_bits = word_size_bytes << 3;
|
698 |
|
|
crc_calc_i = 32'hffffffff;
|
699 |
|
|
|
700 |
|
|
// Send the command
|
701 |
|
|
case (word_size_bytes)
|
702 |
|
|
3'h1: opcode = `DBG_WB_CMD_BWRITE8;
|
703 |
|
|
3'h2: opcode = `DBG_WB_CMD_BWRITE16;
|
704 |
|
|
3'h4: opcode = `DBG_WB_CMD_BWRITE32;
|
705 |
|
|
default:
|
706 |
|
|
begin
|
707 |
|
|
$display("Tried burst write with invalid word size (%0x), defaulting to 4-byte words", word_size_bytes);
|
708 |
|
|
opcode = `DBG_WB_CMD_BWRITE32;
|
709 |
|
|
end
|
710 |
|
|
endcase
|
711 |
|
|
|
712 |
|
|
send_module_burst_command(opcode, start_address, word_count); // returns to state idle
|
713 |
|
|
|
714 |
|
|
// Get us back to shift_dr mode to write a burst
|
715 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
716 |
|
|
write_bit(3'h0); // capture_ir
|
717 |
|
|
write_bit(3'h0); // shift_ir
|
718 |
|
|
|
719 |
|
|
|
720 |
|
|
// Write a start bit (a 1) so it knows when to start counting
|
721 |
|
|
write_bit(`JTAG_TDO_bit);
|
722 |
|
|
|
723 |
|
|
// Now, repeat...
|
724 |
|
|
for(i = 0; i < word_count; i=i+1) begin
|
725 |
|
|
// Write word_size_bytes*8 bits, then get 1 status bit
|
726 |
|
|
if(word_size_bytes == 4) dataword = {32'h0, static_data32[i]};
|
727 |
|
|
else if(word_size_bytes == 2) dataword = {48'h0, static_data16[i]};
|
728 |
|
|
else dataword = {56'h0, static_data8[i]};
|
729 |
|
|
|
730 |
|
|
|
731 |
|
|
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
|
732 |
|
|
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
|
733 |
|
|
crc_calc_i = crc_calc_o;
|
734 |
|
|
|
735 |
32 |
nyawn |
`ifndef ADBG_USE_HISPEED
|
736 |
3 |
nyawn |
// Check if WB bus is ready
|
737 |
|
|
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
|
738 |
|
|
status = 1'b0;
|
739 |
|
|
read_write_bit(3'h0, status);
|
740 |
|
|
|
741 |
|
|
if(!status) begin
|
742 |
|
|
$display("Bad status bit during burst write, index %d", i);
|
743 |
|
|
end
|
744 |
32 |
nyawn |
`endif
|
745 |
3 |
nyawn |
|
746 |
|
|
//$display("Wrote 0x%0x", dataword);
|
747 |
|
|
end
|
748 |
|
|
|
749 |
|
|
// Send the CRC we computed
|
750 |
|
|
jtag_write_stream(crc_calc_o, 6'd32,0);
|
751 |
|
|
|
752 |
|
|
// Read the 'CRC match' bit, and go to exit1_dr
|
753 |
|
|
read_write_bit(`JTAG_TMS_bit, crc_match);
|
754 |
|
|
if(!crc_match) $display("CRC ERROR! match bit after write is %d (computed CRC 0x%x)", crc_match, crc_calc_o);
|
755 |
|
|
else $display("CRC OK!");
|
756 |
|
|
|
757 |
|
|
// Finally, shift out 5 0's, to make the next command a NOP
|
758 |
|
|
// Not necessary, module will not latch new opcode during burst
|
759 |
|
|
//jtag_write_stream(64'h0, 8'h5, 1);
|
760 |
|
|
write_bit(`JTAG_TMS_bit); // update_ir
|
761 |
|
|
write_bit(3'h0); // idle
|
762 |
|
|
end
|
763 |
|
|
|
764 |
|
|
endtask
|
765 |
|
|
|
766 |
|
|
|
767 |
|
|
// Puts a value in the TAP IR, assuming we start in IDLE state.
|
768 |
|
|
// Returns to IDLE state when finished
|
769 |
|
|
task set_ir;
|
770 |
|
|
input [3:0] irval;
|
771 |
|
|
begin
|
772 |
|
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
773 |
|
|
write_bit(`JTAG_TMS_bit); // select_ir_scan
|
774 |
|
|
write_bit(3'h0); // capture_ir
|
775 |
|
|
write_bit(3'h0); // shift_ir
|
776 |
|
|
jtag_write_stream({60'h0,irval}, 8'h4, 1); // write data, exit_1
|
777 |
|
|
write_bit(`JTAG_TMS_bit); // update_ir
|
778 |
|
|
write_bit(3'h0); // idle
|
779 |
|
|
end
|
780 |
|
|
endtask
|
781 |
|
|
|
782 |
|
|
// Resets the TAP and puts it into idle mode
|
783 |
|
|
task reset_jtag;
|
784 |
|
|
integer i;
|
785 |
|
|
begin
|
786 |
|
|
for(i = 0; i < 8; i=i+1) begin
|
787 |
|
|
write_bit(`JTAG_TMS_bit); // 5 TMS should put us in test_logic_reset mode
|
788 |
|
|
end
|
789 |
|
|
write_bit(3'h0); // idle
|
790 |
|
|
end
|
791 |
|
|
endtask
|
792 |
|
|
|
793 |
|
|
|
794 |
|
|
////////////////////////////////////////////////////////////////////////////
|
795 |
|
|
// Tasks to write or read-write a string of data
|
796 |
|
|
|
797 |
|
|
task jtag_write_stream;
|
798 |
|
|
input [63:0] stream;
|
799 |
|
|
input [7:0] len;
|
800 |
|
|
input set_last_bit;
|
801 |
|
|
integer i;
|
802 |
|
|
integer databit;
|
803 |
|
|
reg [2:0] bits;
|
804 |
|
|
begin
|
805 |
|
|
for(i = 0; i < (len-1); i=i+1) begin
|
806 |
|
|
databit = (stream >> i) & 1'h1;
|
807 |
|
|
bits = databit << `JTAG_TDO;
|
808 |
|
|
write_bit(bits);
|
809 |
|
|
end
|
810 |
|
|
|
811 |
|
|
databit = (stream >> i) & 1'h1;
|
812 |
|
|
bits = databit << `JTAG_TDO;
|
813 |
|
|
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
|
814 |
|
|
write_bit(bits);
|
815 |
|
|
|
816 |
|
|
end
|
817 |
|
|
endtask
|
818 |
|
|
|
819 |
|
|
|
820 |
|
|
task jtag_read_write_stream;
|
821 |
|
|
input [63:0] stream;
|
822 |
|
|
input [7:0] len;
|
823 |
|
|
input set_last_bit;
|
824 |
|
|
output [63:0] instream;
|
825 |
|
|
integer i;
|
826 |
|
|
integer databit;
|
827 |
|
|
reg [2:0] bits;
|
828 |
|
|
reg inbit;
|
829 |
|
|
begin
|
830 |
|
|
instream = 64'h0;
|
831 |
|
|
for(i = 0; i < (len-1); i=i+1) begin
|
832 |
|
|
databit = (stream >> i) & 1'h1;
|
833 |
|
|
bits = databit << `JTAG_TDO;
|
834 |
|
|
read_write_bit(bits, inbit);
|
835 |
|
|
instream = (instream | (inbit << i));
|
836 |
|
|
end
|
837 |
|
|
|
838 |
|
|
databit = (stream >> i) & 1'h1;
|
839 |
|
|
bits = databit << `JTAG_TDO;
|
840 |
|
|
if(set_last_bit) bits = (bits | `JTAG_TMS_bit);
|
841 |
|
|
read_write_bit(bits, inbit);
|
842 |
|
|
instream = (instream | (inbit << (len-1)));
|
843 |
|
|
end
|
844 |
|
|
endtask
|
845 |
|
|
|
846 |
|
|
/////////////////////////////////////////////////////////////////////////
|
847 |
|
|
// Tasks which write or readwrite a single bit (including clocking)
|
848 |
|
|
|
849 |
|
|
task write_bit;
|
850 |
|
|
input [2:0] bitvals;
|
851 |
|
|
begin
|
852 |
|
|
|
853 |
|
|
// Set data
|
854 |
|
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
855 |
|
|
`wait_jtag_period;
|
856 |
|
|
|
857 |
|
|
// Raise clock
|
858 |
|
|
jtag_out(bitvals | `JTAG_TCK_bit);
|
859 |
|
|
`wait_jtag_period;
|
860 |
|
|
|
861 |
|
|
// drop clock (making output available in the SHIFT_xR states)
|
862 |
|
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
863 |
|
|
`wait_jtag_period;
|
864 |
|
|
end
|
865 |
|
|
endtask
|
866 |
|
|
|
867 |
|
|
task read_write_bit;
|
868 |
|
|
input [2:0] bitvals;
|
869 |
|
|
output l_tdi_val;
|
870 |
|
|
begin
|
871 |
|
|
|
872 |
|
|
// read bit state
|
873 |
|
|
l_tdi_val <= jtag_tdi_i;
|
874 |
|
|
|
875 |
|
|
// Set data
|
876 |
|
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
877 |
|
|
`wait_jtag_period;
|
878 |
|
|
|
879 |
|
|
// Raise clock
|
880 |
|
|
jtag_out(bitvals | `JTAG_TCK_bit);
|
881 |
|
|
`wait_jtag_period;
|
882 |
|
|
|
883 |
|
|
// drop clock (making output available in the SHIFT_xR states)
|
884 |
|
|
jtag_out(bitvals & ~(`JTAG_TCK_bit));
|
885 |
|
|
`wait_jtag_period;
|
886 |
|
|
end
|
887 |
|
|
endtask
|
888 |
|
|
|
889 |
|
|
/////////////////////////////////////////////////////////////////
|
890 |
|
|
// Basic functions to set the state of the JTAG TAP I/F bits
|
891 |
|
|
|
892 |
|
|
task jtag_out;
|
893 |
|
|
input [2:0] bitvals;
|
894 |
|
|
begin
|
895 |
|
|
|
896 |
|
|
jtag_tck_o <= bitvals[`JTAG_TCK];
|
897 |
|
|
jtag_tms_o <= bitvals[`JTAG_TMS];
|
898 |
|
|
jtag_tdo_o <= bitvals[`JTAG_TDO];
|
899 |
|
|
end
|
900 |
|
|
endtask
|
901 |
|
|
|
902 |
|
|
|
903 |
|
|
task jtag_inout;
|
904 |
|
|
input [2:0] bitvals;
|
905 |
|
|
output l_tdi_val;
|
906 |
|
|
begin
|
907 |
|
|
|
908 |
|
|
jtag_tck_o <= bitvals[`JTAG_TCK];
|
909 |
|
|
jtag_tms_o <= bitvals[`JTAG_TMS];
|
910 |
|
|
jtag_tdo_o <= bitvals[`JTAG_TDO];
|
911 |
|
|
|
912 |
|
|
l_tdi_val <= jtag_tdi_i;
|
913 |
|
|
end
|
914 |
|
|
endtask
|
915 |
|
|
|
916 |
|
|
endmodule
|