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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  wb_slave_behavioral.v                                       ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////      Tadej Markovic, tadej@opencores.org                     ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: wb_slave_behavioral.v,v $
// Revision 1.1  2008/07/08 19:11:57  Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram.  Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.2  2008/06/26 20:54:44  Nathan
// Testbench modified to use WB behavioral model instead of an onchip_ram.  Added test of WB error register.
//
// Revision 1.1  2008/06/18 18:34:49  Nathan
// Initial working version.  Only Wishbone module implemented.  Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1  2008/05/14 12:07:36  Nathan
// Original from OpenCores
//
// Revision 1.3  2004/03/28 20:27:40  igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.2  2004/01/15 10:47:13  mohor
// Working.
//
// Revision 1.1  2003/12/23 14:26:01  mohor
// New version of the debug interface. Not finished, yet.
//
//
//
//
 
//`include "timescale.v"
`include "wb_model_defines.v"
module wb_slave_behavioral
(
        CLK_I,
        RST_I,
        ACK_O,
        ADR_I,
        CYC_I,
        DAT_O,
        DAT_I,
        ERR_O,
        RTY_O,
        SEL_I,
        STB_I,
        WE_I,
        CAB_I
);
 
/*------------------------------------------------------------------------------------------------------
WISHBONE signals
------------------------------------------------------------------------------------------------------*/
input                   CLK_I;
input                   RST_I;
output                  ACK_O;
input   `WB_ADDR_TYPE   ADR_I;
input                   CYC_I;
output  `WB_DATA_TYPE   DAT_O;
input   `WB_DATA_TYPE   DAT_I;
output                  ERR_O;
output                  RTY_O;
input   `WB_SEL_TYPE    SEL_I;
input                   STB_I;
input                   WE_I;
input                   CAB_I;
 
reg     `WB_DATA_TYPE   DAT_O;
 
/*------------------------------------------------------------------------------------------------------
Asynchronous dual-port RAM signals for storing and fetching the data
------------------------------------------------------------------------------------------------------*/
//reg     `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
reg     `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
reg     `WB_DATA_TYPE mem_wr_data_out;
reg     `WB_DATA_TYPE mem_rd_data_in;
 
/*------------------------------------------------------------------------------------------------------
Maximum values for WAIT and RETRY counters and which response !!!
------------------------------------------------------------------------------------------------------*/
reg     [2:0]  a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
reg     [8:0]  wait_cyc;
reg     [7:0]  max_retry;
 
// assign registers to default state while in reset
// always@(RST_I)
// begin
//   if (RST_I)
//   begin
//     a_e_r_resp <= 3'b000; // do not respond
//     wait_cyc   <= 8'b0; // no wait cycles
//     max_retry  <= 8'h0; // no retries
//   end
// end //reset
 
task cycle_response;
  input [2:0]  ack_err_rty_resp; // acknowledge, error or retry response input flags
  input [8:0]  wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
  input [7:0]  retry_cycles; // noumber of retry cycles before acknowledge cycle
begin
  // assign values
  a_e_r_resp <= #1 ack_err_rty_resp;
  wait_cyc   <= #1 wait_cycles;
  max_retry  <= #1 retry_cycles;
end
endtask // cycle_response
 
/*------------------------------------------------------------------------------------------------------
Tasks for writing and reading to and from memory !!!
------------------------------------------------------------------------------------------------------*/
reg    `WB_ADDR_TYPE task_wr_adr_i;
reg    `WB_ADDR_TYPE task_rd_adr_i;
reg    `WB_DATA_TYPE task_dat_i;
reg    `WB_DATA_TYPE task_dat_o;
reg    `WB_SEL_TYPE  task_sel_i;
reg                  task_wr_data;
reg                  task_data_written;
reg    `WB_DATA_TYPE task_mem_wr_data;
 
// write to memory
task wr_mem;
  input  `WB_ADDR_TYPE adr_i;
  input  `WB_DATA_TYPE dat_i;
  input  `WB_SEL_TYPE  sel_i;
begin
  task_data_written = 0;
  task_wr_adr_i = adr_i;
  task_dat_i = dat_i;
  task_sel_i = sel_i;
  task_wr_data = 1;
  wait(task_data_written);
  task_wr_data = 0;
end
endtask
 
// read from memory
task rd_mem;
  input  `WB_ADDR_TYPE adr_i;
  output `WB_DATA_TYPE dat_o;
  input  `WB_SEL_TYPE  sel_i;
begin
  task_rd_adr_i = adr_i;
  task_sel_i = sel_i;
  #1;
  dat_o = task_dat_o;
end
endtask
 
/*------------------------------------------------------------------------------------------------------
Internal signals and logic
------------------------------------------------------------------------------------------------------*/
reg            calc_ack;
reg            calc_err;
reg            calc_rty;
 
reg     [7:0]  retry_cnt;
reg     [7:0]  retry_num;
reg            retry_expired;
 
// Retry counter
always@(posedge RST_I or posedge CLK_I)
begin
  if (RST_I)
    retry_cnt <= #1 8'h00;
  else
  begin
    if (calc_ack || calc_err)
      retry_cnt <= #1 8'h00;
    else if (calc_rty)
      retry_cnt <= #1 retry_num;
  end
end
 
always@(retry_cnt or max_retry)
begin
  if (retry_cnt < max_retry)
  begin
    retry_num = retry_cnt + 1'b1;
    retry_expired = 1'b0;
  end
  else
  begin
    retry_num = retry_cnt;
    retry_expired = 1'b1;
  end
end
 
reg     [8:0]  wait_cnt;
reg     [8:0]  wait_num;
reg            wait_expired;
 
// Wait counter
always@(posedge RST_I or posedge CLK_I)
begin
  if (RST_I)
    wait_cnt <= #1 9'h0;
  else
  begin
    if (wait_expired || ~STB_I)
      wait_cnt <= #1 9'h0;
    else
      wait_cnt <= #1 wait_num;
  end
end
 
always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
begin
  if ((wait_cyc > 0) && (STB_I))
  begin
    if (wait_cnt < wait_cyc)
    begin
      wait_num = wait_cnt + 1'b1;
      wait_expired = 1'b0;
      calc_ack = 1'b0;
      calc_err = 1'b0;
      calc_rty = 1'b0;
    end
    else
    begin
      wait_num = wait_cnt;
      wait_expired = 1'b1;
      if (a_e_r_resp == 3'b100)
      begin
        calc_ack = 1'b1;
        calc_err = 1'b0;
        calc_rty = 1'b0;
      end
      else
      if (a_e_r_resp == 3'b010)
      begin
        calc_ack = 1'b0;
        calc_err = 1'b1;
        calc_rty = 1'b0;
      end
      else
      if (a_e_r_resp == 3'b001)
      begin
        calc_err = 1'b0;
        if (retry_expired)
        begin
          calc_ack = 1'b1;
          calc_rty = 1'b0;
        end
        else
        begin
          calc_ack = 1'b0;
          calc_rty = 1'b1;
        end
      end
      else
      begin
        calc_ack = 1'b0;
        calc_err = 1'b0;
        calc_rty = 1'b0;
      end
    end
  end
  else
  if ((wait_cyc == 0) && (STB_I))
  begin
    wait_num = 9'h0;
    wait_expired = 1'b1;
    if (a_e_r_resp == 3'b100)
    begin
      calc_ack = 1'b1;
      calc_err = 1'b0;
      calc_rty = 1'b0;
    end
    else if (a_e_r_resp == 3'b010)
    begin
      calc_ack = 1'b0;
      calc_err = 1'b1;
      calc_rty = 1'b0;
    end
    else if (a_e_r_resp == 3'b001)
    begin
      calc_err = 1'b0;
      if (retry_expired)
      begin
        calc_ack = 1'b1;
        calc_rty = 1'b0;
      end
      else
      begin
        calc_ack = 1'b0;
        calc_rty = 1'b1;
      end
    end
    else
    begin
      calc_ack = 1'b0;
      calc_err = 1'b0;
      calc_rty = 1'b0;
    end
  end
  else
  begin
    wait_num = 9'h0;
    wait_expired = 1'b0;
    calc_ack = 1'b0;
    calc_err = 1'b0;
    calc_rty = 1'b0;
  end
end
 
wire rd_sel = (CYC_I && STB_I && ~WE_I);
wire wr_sel = (CYC_I && STB_I && WE_I);
 
// Generate cycle termination signals
assign ACK_O = calc_ack && STB_I;
assign ERR_O = calc_err && STB_I;
assign RTY_O = calc_rty && STB_I;
 
// Assign address to asynchronous memory
always@(RST_I or ADR_I)
begin
  if (RST_I) // this is added because at start of test bench we need address change in order to get data!
  begin
    #1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
  end
  else
  begin
//    #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];
    #1 mem_rd_data_in = wb_memory[ADR_I[21:2]];
  end
end
 
// Data input/output interface
always@(rd_sel or mem_rd_data_in or RST_I)
begin
  if (RST_I)
    DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;       // assign outputs to unknown state while in reset
  else if (rd_sel)
    DAT_O <=#1 mem_rd_data_in;
  else
    DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
end
 
 
always@(RST_I or task_rd_adr_i)
begin
  if (RST_I)
    task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
  else
    task_dat_o = wb_memory[task_rd_adr_i[21:2]];
end
always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or
        mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or
        SEL_I or task_sel_i)
begin
  if (task_wr_data)
  begin
    task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];
 
    if (task_sel_i[3])
      task_mem_wr_data[31:24] = task_dat_i[31:24];
    if (task_sel_i[2])
      task_mem_wr_data[23:16] = task_dat_i[23:16];
    if (task_sel_i[1])
      task_mem_wr_data[15: 8] = task_dat_i[15: 8];
    if (task_sel_i[0])
      task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
 
    wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
    task_data_written = 1;
  end
  else if (wr_sel && CLK_I)
  begin
//    mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
    mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
 
    if (SEL_I[3])
      mem_wr_data_out[31:24] = DAT_I[31:24];
    if (SEL_I[2])
      mem_wr_data_out[23:16] = DAT_I[23:16];
    if (SEL_I[1])
      mem_wr_data_out[15: 8] = DAT_I[15: 8];
    if (SEL_I[0])
      mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];
 
//    wb_memory[ADR_I[25:2]]  <= mem_wr_data_out; // write data
    wb_memory[ADR_I[21:2]]      = mem_wr_data_out; // write data
  end
end
 
endmodule

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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [bench/] [simulated_system/] [wb_slave_behavioral.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	nyawn	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// wb_slave_behavioral.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Debug Interface. ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Tadej Markovic, tadej@opencores.org ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: wb_slave_behavioral.v,v $`
46			`// Revision 1.1 2008/07/08 19:11:57 Nathan`
47			`// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.`
48			`//`
49			`// Revision 1.2 2008/06/26 20:54:44 Nathan`
50			`// Testbench modified to use WB behavioral model instead of an onchip_ram. Added test of WB error register.`
51			`//`
52			`// Revision 1.1 2008/06/18 18:34:49 Nathan`
53			`// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.`
54			`//`
55			`// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan`
56			`// Original from OpenCores`
57			`//`
58			`// Revision 1.3 2004/03/28 20:27:40 igorm`
59			`// New release of the debug interface (3rd. release).`
60			`//`
61			`// Revision 1.2 2004/01/15 10:47:13 mohor`
62			`// Working.`
63			`//`
64			`// Revision 1.1 2003/12/23 14:26:01 mohor`
65			`// New version of the debug interface. Not finished, yet.`
66			`//`
67			`//`
68			`//`
69			`//`
70
71			//`include "timescale.v"
72			`include "wb_model_defines.v"
73			`module wb_slave_behavioral`
74			`(`
75			`CLK_I,`
76			`RST_I,`
77			`ACK_O,`
78			`ADR_I,`
79			`CYC_I,`
80			`DAT_O,`
81			`DAT_I,`
82			`ERR_O,`
83			`RTY_O,`
84			`SEL_I,`
85			`STB_I,`
86			`WE_I,`
87			`CAB_I`
88			`);`
89
90			`/*------------------------------------------------------------------------------------------------------`
91			`WISHBONE signals`
92			`------------------------------------------------------------------------------------------------------*/`
93			`input CLK_I;`
94			`input RST_I;`
95			`output ACK_O;`
96			input `WB_ADDR_TYPE ADR_I;
97			`input CYC_I;`
98			output `WB_DATA_TYPE DAT_O;
99			input `WB_DATA_TYPE DAT_I;
100			`output ERR_O;`
101			`output RTY_O;`
102			input `WB_SEL_TYPE SEL_I;
103			`input STB_I;`
104			`input WE_I;`
105			`input CAB_I;`
106
107			reg `WB_DATA_TYPE DAT_O;
108
109			`/*------------------------------------------------------------------------------------------------------`
110			`Asynchronous dual-port RAM signals for storing and fetching the data`
111			`------------------------------------------------------------------------------------------------------*/`
112			//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
113			reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
114			reg `WB_DATA_TYPE mem_wr_data_out;
115			reg `WB_DATA_TYPE mem_rd_data_in;
116
117			`/*------------------------------------------------------------------------------------------------------`
118			`Maximum values for WAIT and RETRY counters and which response !!!`
119			`------------------------------------------------------------------------------------------------------*/`
120			`reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !`
121			`reg [8:0] wait_cyc;`
122			`reg [7:0] max_retry;`
123
124			`// assign registers to default state while in reset`
125			`// always@(RST_I)`
126			`// begin`
127			`// if (RST_I)`
128			`// begin`
129			`// a_e_r_resp <= 3'b000; // do not respond`
130			`// wait_cyc <= 8'b0; // no wait cycles`
131			`// max_retry <= 8'h0; // no retries`
132			`// end`
133			`// end //reset`
134
135			`task cycle_response;`
136			`input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags`
137			`input [8:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)`
138			`input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle`
139			`begin`
140			`// assign values`
141			`a_e_r_resp <= #1 ack_err_rty_resp;`
142			`wait_cyc <= #1 wait_cycles;`
143			`max_retry <= #1 retry_cycles;`
144			`end`
145			`endtask // cycle_response`
146
147			`/*------------------------------------------------------------------------------------------------------`
148			`Tasks for writing and reading to and from memory !!!`
149			`------------------------------------------------------------------------------------------------------*/`
150			reg `WB_ADDR_TYPE task_wr_adr_i;
151			reg `WB_ADDR_TYPE task_rd_adr_i;
152			reg `WB_DATA_TYPE task_dat_i;
153			reg `WB_DATA_TYPE task_dat_o;
154			reg `WB_SEL_TYPE task_sel_i;
155			`reg task_wr_data;`
156			`reg task_data_written;`
157			reg `WB_DATA_TYPE task_mem_wr_data;
158
159			`// write to memory`
160			`task wr_mem;`
161			input `WB_ADDR_TYPE adr_i;
162			input `WB_DATA_TYPE dat_i;
163			input `WB_SEL_TYPE sel_i;
164			`begin`
165			`task_data_written = 0;`
166			`task_wr_adr_i = adr_i;`
167			`task_dat_i = dat_i;`
168			`task_sel_i = sel_i;`
169			`task_wr_data = 1;`
170			`wait(task_data_written);`
171			`task_wr_data = 0;`
172			`end`
173			`endtask`
174
175			`// read from memory`
176			`task rd_mem;`
177			input `WB_ADDR_TYPE adr_i;
178			output `WB_DATA_TYPE dat_o;
179			input `WB_SEL_TYPE sel_i;
180			`begin`
181			`task_rd_adr_i = adr_i;`
182			`task_sel_i = sel_i;`
183			`#1;`
184			`dat_o = task_dat_o;`
185			`end`
186			`endtask`
187
188			`/*------------------------------------------------------------------------------------------------------`
189			`Internal signals and logic`
190			`------------------------------------------------------------------------------------------------------*/`
191			`reg calc_ack;`
192			`reg calc_err;`
193			`reg calc_rty;`
194
195			`reg [7:0] retry_cnt;`
196			`reg [7:0] retry_num;`
197			`reg retry_expired;`
198
199			`// Retry counter`
200			`always@(posedge RST_I or posedge CLK_I)`
201			`begin`
202			`if (RST_I)`
203			`retry_cnt <= #1 8'h00;`
204			`else`
205			`begin`
206			`if (calc_ack \|\| calc_err)`
207			`retry_cnt <= #1 8'h00;`
208			`else if (calc_rty)`
209			`retry_cnt <= #1 retry_num;`
210			`end`
211			`end`
212
213			`always@(retry_cnt or max_retry)`
214			`begin`
215			`if (retry_cnt < max_retry)`
216			`begin`
217			`retry_num = retry_cnt + 1'b1;`
218			`retry_expired = 1'b0;`
219			`end`
220			`else`
221			`begin`
222			`retry_num = retry_cnt;`
223			`retry_expired = 1'b1;`
224			`end`
225			`end`
226
227			`reg [8:0] wait_cnt;`
228			`reg [8:0] wait_num;`
229			`reg wait_expired;`
230
231			`// Wait counter`
232			`always@(posedge RST_I or posedge CLK_I)`
233			`begin`
234			`if (RST_I)`
235			`wait_cnt <= #1 9'h0;`
236			`else`
237			`begin`
238			`if (wait_expired \|\| ~STB_I)`
239			`wait_cnt <= #1 9'h0;`
240			`else`
241			`wait_cnt <= #1 wait_num;`
242			`end`
243			`end`
244
245			`always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)`
246			`begin`
247			`if ((wait_cyc > 0) && (STB_I))`
248			`begin`
249			`if (wait_cnt < wait_cyc)`
250			`begin`
251			`wait_num = wait_cnt + 1'b1;`
252			`wait_expired = 1'b0;`
253			`calc_ack = 1'b0;`
254			`calc_err = 1'b0;`
255			`calc_rty = 1'b0;`
256			`end`
257			`else`
258			`begin`
259			`wait_num = wait_cnt;`
260			`wait_expired = 1'b1;`
261			`if (a_e_r_resp == 3'b100)`
262			`begin`
263			`calc_ack = 1'b1;`
264			`calc_err = 1'b0;`
265			`calc_rty = 1'b0;`
266			`end`
267			`else`
268			`if (a_e_r_resp == 3'b010)`
269			`begin`
270			`calc_ack = 1'b0;`
271			`calc_err = 1'b1;`
272			`calc_rty = 1'b0;`
273			`end`
274			`else`
275			`if (a_e_r_resp == 3'b001)`
276			`begin`
277			`calc_err = 1'b0;`
278			`if (retry_expired)`
279			`begin`
280			`calc_ack = 1'b1;`
281			`calc_rty = 1'b0;`
282			`end`
283			`else`
284			`begin`
285			`calc_ack = 1'b0;`
286			`calc_rty = 1'b1;`
287			`end`
288			`end`
289			`else`
290			`begin`
291			`calc_ack = 1'b0;`
292			`calc_err = 1'b0;`
293			`calc_rty = 1'b0;`
294			`end`
295			`end`
296			`end`
297			`else`
298			`if ((wait_cyc == 0) && (STB_I))`
299			`begin`
300			`wait_num = 9'h0;`
301			`wait_expired = 1'b1;`
302			`if (a_e_r_resp == 3'b100)`
303			`begin`
304			`calc_ack = 1'b1;`
305			`calc_err = 1'b0;`
306			`calc_rty = 1'b0;`
307			`end`
308			`else if (a_e_r_resp == 3'b010)`
309			`begin`
310			`calc_ack = 1'b0;`
311			`calc_err = 1'b1;`
312			`calc_rty = 1'b0;`
313			`end`
314			`else if (a_e_r_resp == 3'b001)`
315			`begin`
316			`calc_err = 1'b0;`
317			`if (retry_expired)`
318			`begin`
319			`calc_ack = 1'b1;`
320			`calc_rty = 1'b0;`
321			`end`
322			`else`
323			`begin`
324			`calc_ack = 1'b0;`
325			`calc_rty = 1'b1;`
326			`end`
327			`end`
328			`else`
329			`begin`
330			`calc_ack = 1'b0;`
331			`calc_err = 1'b0;`
332			`calc_rty = 1'b0;`
333			`end`
334			`end`
335			`else`
336			`begin`
337			`wait_num = 9'h0;`
338			`wait_expired = 1'b0;`
339			`calc_ack = 1'b0;`
340			`calc_err = 1'b0;`
341			`calc_rty = 1'b0;`
342			`end`
343			`end`
344
345			`wire rd_sel = (CYC_I && STB_I && ~WE_I);`
346			`wire wr_sel = (CYC_I && STB_I && WE_I);`
347
348			`// Generate cycle termination signals`
349			`assign ACK_O = calc_ack && STB_I;`
350			`assign ERR_O = calc_err && STB_I;`
351			`assign RTY_O = calc_rty && STB_I;`
352
353			`// Assign address to asynchronous memory`
354			`always@(RST_I or ADR_I)`
355			`begin`
356			`if (RST_I) // this is added because at start of test bench we need address change in order to get data!`
357			`begin`
358			#1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
359			`end`
360			`else`
361			`begin`
362			`// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];`
363			`#1 mem_rd_data_in = wb_memory[ADR_I[21:2]];`
364			`end`
365			`end`
366
367			`// Data input/output interface`
368			`always@(rd_sel or mem_rd_data_in or RST_I)`
369			`begin`
370			`if (RST_I)`
371			DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset
372			`else if (rd_sel)`
373			`DAT_O <=#1 mem_rd_data_in;`
374			`else`
375			DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
376			`end`
377
378
379			`always@(RST_I or task_rd_adr_i)`
380			`begin`
381			`if (RST_I)`
382			task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
383			`else`
384			`task_dat_o = wb_memory[task_rd_adr_i[21:2]];`
385			`end`
386			`always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or`
387			`mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or`
388			`SEL_I or task_sel_i)`
389			`begin`
390			`if (task_wr_data)`
391			`begin`
392			`task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];`
393
394			`if (task_sel_i[3])`
395			`task_mem_wr_data[31:24] = task_dat_i[31:24];`
396			`if (task_sel_i[2])`
397			`task_mem_wr_data[23:16] = task_dat_i[23:16];`
398			`if (task_sel_i[1])`
399			`task_mem_wr_data[15: 8] = task_dat_i[15: 8];`
400			`if (task_sel_i[0])`
401			`task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];`
402
403			`wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data`
404			`task_data_written = 1;`
405			`end`
406			`else if (wr_sel && CLK_I)`
407			`begin`
408			`// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written`
409			`mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written`
410
411			`if (SEL_I[3])`
412			`mem_wr_data_out[31:24] = DAT_I[31:24];`
413			`if (SEL_I[2])`
414			`mem_wr_data_out[23:16] = DAT_I[23:16];`
415			`if (SEL_I[1])`
416			`mem_wr_data_out[15: 8] = DAT_I[15: 8];`
417			`if (SEL_I[0])`
418			`mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];`
419
420			`// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data`
421			`wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data`
422			`end`
423			`end`
424
425			`endmodule`